Figure 9-5 shows APLL1 and APLL2 are in cascaded mode from APLL3, VCO3 is held around its nominal center frequency of 2457.6 MHz while APLL1 and APLL2 lock. Subsequently, APLL3 locks the VCO3 frequency to the external XO input and operates in free-run mode. Cascaded PLLs lock to a divided frequency from the source VCO. Once a valid DPLL reference input is detected beyond a minimum valid time, the DPLLs begin lock acquisition. Each DPLL TDC compares the phase of the selected reference input clock and the FB divider clock from the respective VCO and generates a digital correction word corresponding to the phase error. At beginning, the TDC simply cancels out the phase error with no filtering correction word. Then subsequent correction words are filtered by the DLF, and the DLF output adjusts the APLL N divider SDM to pull the VCO frequency into lock with the reference input.

Using the VCBO as a cascade source to APLL1 or APLL2 provides the APLL a high-frequency, ultra-low-jitter reference clock. This unique cascading feature can provide improved close in phase noise performance if the XO/TCXO/OCXO is a low frequency or has poor phase noise performance. Note that in cascaded DPLL operation the best jitter performance and frequency stability will be achieved after DPLL3 locked.

DPLL3 lock status will impact DPLL1 and DPLL2 lock status. If APLL3 is in free-run mode or holdover mode, the VCBO frequency offset ppm value could introduce a similar frequency offset at APLL1 and APLL2 outputs even though DPLL1 and DPLL2 can stay in locked status. In this configuration example, ensure DPLL3 and APLL3 are locked first, toggle PLL1 or PLL2 enable cycle (APLLx_EN bit = 0 → 1) to calibrate VCO1 or VCO2, and then double check PLL1 or PLL2 lock status.

In above example, APLL3 is upstream PLL, while APLL1 and APLL2 are downstream PLLs. If there are system start-up requirements on the clock sequencing, APLL1 or APLL2 also can be configured as the upstream PLL.

When cascading PLLs, the downstream APLL may use the DPLL or bypass and power down the DPLL depending on performance requirements. If DPLL1 and DPLL2 are disabled from above APLL cascaded mode, then DPLL3-only cascade mode may be used (Figure 9-6). In this case, VCO1 or VCO2 can track the VCO3 domain during DPLL3 lock acquisition and locked modes, allowing APLL1 or APLL2's clock domain to be synchronized to the DPLL3 reference input.

When a DPLL is disabled, it is recommended to use the 24-bit numerator and programmable 24-bit denominator instead of the fixed 40-bit denominator to eliminate frequency error from APLL reference to output.

Do not cascade one VCO output to both the DPLL reference and APLL reference of the same DPLL/APLL pair.

Figure 9-5 APLL Cascaded with DPLLs Enabled Example

Figure 9-6 APLL Cascaded with DPLLs Disabled Example