SNAS750B November 2020 – March 2021 LMK5C33216
PRODUCTION DATA
Each APLL has a 40-bit fractional-N divider to support high-resolution frequency synthesis and very low phase noise and jitter, has the ability to tune its VCO frequency through sigma-delta modulator (SDM) control in DPLL mode. In cascaded mode, each APLL has the ability to lock its VCO frequency to another VCO frequency.
In free-run mode, APLL3 uses the XO input as an initial reference clock to its VCO3. APLL3's PFD compares the fractional-N divided clock with its reference clock and generates a control signal. The control signal is filtered by the APLL3 loop filter to generate VCO3's control voltage to set its output frequency. The SDM modulates the N divider ratio to get the desired fractional ratio between the PFD input and the VCO3 output. APLL1 or APLL2 operates similar to APLL3. User can select the reference from either the VCO3 clock or XO clock.
In DPLL mode, the APLL fractional SDM is controlled by the DPLL loop to pull the VCO frequency into lock with the DPLL reference input. For example, as Figure 9-6, if DPLL1 or DPLL2 is disabled, the respective APLL1 or APLL2 derives its reference from VCO3, then VCO1 or VCO2 will be effectively locked to the DPLL3 reference input, assuming there is no synthesis error introduced by the fractional N divide ratio of APLL1 or APLL2.