SNAS750B November   2020  – March 2021 LMK5C33216

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Diagrams
  8. 8 Parameter Measurement Information
    1. 8.1 Differential Voltage Measurement Terminology
    2. 8.2 Output Clock Test Configurations
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
      1. 9.2.1 PLL Architecture Overview
      2. 9.2.2 DPLL
        1. 9.2.2.1 Independent DPLL Operation
        2. 9.2.2.2 Cascaded DPLL Operation
        3. 9.2.2.3 APLL Cascaded with DPLL
      3. 9.2.3 APLL-Only Mode
    3. 9.3 Feature Description
      1. 9.3.1  Oscillator Input (XO)
      2. 9.3.2  Reference Inputs
      3. 9.3.3  Clock Input Interfacing and Termination
      4. 9.3.4  Reference Input Mux Selection
        1. 9.3.4.1 Automatic Input Selection
        2. 9.3.4.2 Manual Input Selection
      5. 9.3.5  Hitless Switching
        1. 9.3.5.1 Hitless Switching with Phase Cancellation
        2. 9.3.5.2 Hitless Switching With Phase Slew Control
        3. 9.3.5.3 Hitless Switching With 1-PPS Inputs
      6. 9.3.6  Gapped Clock Support on Reference Inputs
      7. 9.3.7  Input Clock and PLL Monitoring, Status, and Interrupts
        1. 9.3.7.1 XO Input Monitoring
        2. 9.3.7.2 Reference Input Monitoring
          1. 9.3.7.2.1 Reference Validation Timer
          2. 9.3.7.2.2 Frequency Monitoring
          3. 9.3.7.2.3 Missing Pulse Monitor (Late Detect)
          4. 9.3.7.2.4 Runt Pulse Monitor (Early Detect)
          5. 9.3.7.2.5 Phase Valid Monitor for 1-PPS Inputs
        3. 9.3.7.3 PLL Lock Detectors
        4. 9.3.7.4 Tuning Word History
        5. 9.3.7.5 Status Outputs
        6. 9.3.7.6 Interrupt
      8. 9.3.8  PLL Relationships
        1. 9.3.8.1  PLL Frequency Relationships
          1. 9.3.8.1.1 APLL Phase Detector Frequency
          2. 9.3.8.1.2 APLL VCO Frequency
          3. 9.3.8.1.3 DPLL TDC Frequency
          4. 9.3.8.1.4 DPLL VCO Frequency
          5. 9.3.8.1.5 Clock Output Frequency
        2. 9.3.8.2  Analog PLLs (APLL1, APLL2, APLL3)
        3. 9.3.8.3  APLL Reference Paths
          1. 9.3.8.3.1 APLL XO Doubler
          2. 9.3.8.3.2 APLL XO Reference (R) Divider
        4. 9.3.8.4  APLL Phase Frequency Detector (PFD) and Charge Pump
        5. 9.3.8.5  APLL Feedback Divider Paths
          1. 9.3.8.5.1 APLL N Divider with SDM
        6. 9.3.8.6  APLL Loop Filters (LF1, LF2, LF3)
        7. 9.3.8.7  APLL Voltage Controlled Oscillators (VCO1, VCO2, VCO3)
          1. 9.3.8.7.1 VCO Calibration
        8. 9.3.8.8  APLL VCO Clock Distribution Paths
        9. 9.3.8.9  DPLL Reference (R) Divider Paths
        10. 9.3.8.10 DPLL Time-to-Digital Converter (TDC)
        11. 9.3.8.11 DPLL Loop Filter (DLF)
        12. 9.3.8.12 DPLL Feedback (FB) Divider Path
      9. 9.3.9  Output Clock Distribution
      10. 9.3.10 Output Channel Muxes
      11. 9.3.11 Output Dividers (OD)
      12. 9.3.12 SYSREF
      13. 9.3.13 Output Delay
      14. 9.3.14 Clock Outputs (OUTx_P/N)
        1. 9.3.14.1 Differential Output
        2. 9.3.14.2 LVCMOS Output
        3. 9.3.14.3 Output Auto-Mute During LOL
      15. 9.3.15 Glitchless Output Clock Start-Up
      16. 9.3.16 Clock Output Interfacing and Termination
      17. 9.3.17 Output Synchronization (SYNC)
      18. 9.3.18 Zero-Delay Mode (ZDM) Synchronization
      19. 9.3.19 Time of Day (ToD) Counter
        1. 9.3.19.1 Configuring ToD Functionality
        2. 9.3.19.2 SPI as a Trigger Source
        3. 9.3.19.3 GPIO Pin as a ToD Trigger Source
          1. 9.3.19.3.1 An Example: Making a time measurement using ToD and GPIO1 as trigger
        4. 9.3.19.4 ToD Timing
        5. 9.3.19.5 Other ToD Behavior
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Start-Up
        1. 9.4.1.1 ROM Selection
        2. 9.4.1.2 EEPROM Overlay
      2. 9.4.2 DPLL Operating States
        1. 9.4.2.1 Free-Run
        2. 9.4.2.2 Lock Acquisition
        3. 9.4.2.3 DPLL Locked
        4. 9.4.2.4 Holdover
      3. 9.4.3 PLL Start-Up Sequence
      4. 9.4.4 Digitally-Controlled Oscillator (DCO) Frequency and Phase Adjustment
        1. 9.4.4.1 DPLL DCO Control
          1. 9.4.4.1.1 DPLL DCO Relative Adjustment Frequency Step Size
          2. 9.4.4.1.2 APLL DCO Frequency Step Size
      5. 9.4.5 APLL Frequency Control
      6. 9.4.6 Zero-Delay Mode Synchronization
    5. 9.5 Programming
      1. 9.5.1 Interface and Control
      2. 9.5.2 I2C Serial Interface
        1. 9.5.2.1 I2C Block Register Transfers
      3. 9.5.3 SPI Serial Interface
        1. 9.5.3.1 SPI Block Register Transfer
      4. 9.5.4 Register Map Generation
      5. 9.5.5 General Register Programming Sequence
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Device Start-Up Sequence
      2. 10.1.2 Power Down (PD#) Pin
      3. 10.1.3 Strap Pins for Start-Up
      4. 10.1.4 ROM and EEPROM
      5. 10.1.5 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
        1. 10.1.5.1 Power-On Reset (POR) Circuit
        2. 10.1.5.2 Powering Up From a Single-Supply Rail
        3. 10.1.5.3 Power Up From Split-Supply Rails
        4. 10.1.5.4 Non-Monotonic or Slow Power-Up Supply Ramp
      6. 10.1.6 Slow or Delayed XO Start-Up
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
    3. 10.3 Do's and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Bypassing
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Reliability
      1. 12.3.1 Support for PCB Temperature up to 105°C
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Glossary
    6. 13.6 Electrostatic Discharge Caution
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

Over Recommended Operating Conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IDDPD# Total Supply Current
(all supply pins, 3.3 V)		 Device powered-down (PD# pin held low) 132 mA
IDDCFG1 Total Supply Current
(all supply pins, 3.3 V)		 DPLL3 with 10 MHz input.  APLL2 = 5625 MHz, APLL3 = 2457.6 MHz.  Outputs: 4x  491.52 MHz HSDS. 4x 7.68 MHz HSDS SYSREF.  2x 312.5 MHz LVDS. 875 1050 mA
Reference Input Characteristics (INx)
fIN Input frequency range
 		 INx; Single Ended - LVCMOS input 1E-6 200 MHz
INx; Differential input 5 800
VIH LVCMOS Input high voltage DC-coupled input mode 1.2 VDD + 0.3 V
VIL LVCMOS Input low voltage 0.5 V
VIN-SE Single-ended input voltage swing AC-coupled input mode 0.4 2 Vpp
VIN-DIFF Differential input voltage swing,
peak-peak (|VP – VN| x 2)		 Differential input 0.4 2 Vpp
VICM Input Common Mode Differential input 0.1 2 V
dV/dt Input slew rate Single-ended input, non-driven input tied to GND 0.2 0.5 V/ns
Differential input 0.2 0.5 V/ns
IDC Input Clock Duty Cycle Non 1 PPS signal 40 60 %
tPULSE-1PPS 1PPS pulse width for input 1 PPS signal 100 ns
IIN-DC DC input leakage current Single pin INx_P or INx_N, 50-Ω and 100-Ω internal terminations disabled, AC coupled mode enabled or disabled -350 350 µA
XO/TCXO Input Characteristics (XO)
fCLK Input frequency range 10 100 MHz
VIH LVCMOS Input high voltage DC-coupled input mode 1.4 VDD + 0.3 V
VIL LVCMOS Input low voltage 0.8 V
VIN-SE Single-ended input voltage swing AC-coupled input mode 0.4 VDD + 0.3 Vpp
dV/dt Input slew rate 0.2 0.5 V/ns
IDC Input duty cycle 40 60 %
IIN-DC DC Input leakage current Single pin XO_P, 50-Ω and 100-Ω internal terminations disabled -350 350 µA
APLL/VCO Characteristics
fVCO1 VCO1 Frequency range 4.8 5.35 GHz
fVCO2 VCO2 Frequency range 5.6 5.95 GHz
fVCO3 VCO3 Frequency range 2.457477120 2.4576 2.457722880 GHz
LVDS Output Characteristics (OUTx)
fOUT Maximum output frequency(2) 1000 MHz
VOD Output voltage swing (|VOH - VOL|) OUT_x_AMP = 0, VOS = 1.2 V 300 mV
OUT_x_AMP = 1, VOS = 1.2 V 400 mV
OUT_x_AMP = 2, VOS = 1.2 V 500 mV
OUT_x_AMP = 3, VOS 1.2 V 600 mV
VOUT-DIFF Differential output voltage swing,
peak-to-peak		 2×VOD V
VOS Output common mode OUT_x_AMP = 1,
DC shift setting 2		 0.7 V
OUT_x_AMP = 1,
DC shift setting 4		 0.8 V
OUT_x_AMP = 1,
DC shift setting 6		 1.0 V
OUT_x_AMP = 1,
DC shift setting 8		 1.2 V
OUT_x_AMP = 1,
DC shift setting 10		 1.4 V
OUT_x_AMP = 1,
DC shift setting 12		 1.6 V
tSK Output-to-output skew, same group(4) Same post divider, output divide values, and output format 50 ps
tSK_GRP Output-to-output skew, between groups(4) Same post divider, output divide values, and output format.    Not including OUT14 and OUT15. 80 ps
Same post divider, output divide values, and output format 150 ps
tR/tF Output rise/fall time 20% to 80%, < 500 MHz 150 300 ps
± 100 mV around center point 50 150 ps
PNFLOOR Output phase noise floor(3)
(fOFFSET > 10 MHz)		 122.88 MHz -160 dBc/Hz
ODC Output duty cycle(10) 45 55 %
HSDS Output Characteristics (OUTx)
fOUT Maximum output frequency(2) 1000 MHz
VOD Output voltage swing (|VOH - VOL|) OUT_x_AMP = 1, boost off, VOS = 1.2 V 400 mV
OUT_x_AMP = 2, boost on, VOS = 1.2 V 800 mV
OUT_x_AMP = 3, boost off, VOS = 1.2 V 600 mV
OUT_x_AMP = 2, boost on, VOS = 1.6 V 800 mV
OUT_x_AMP = 3, boost on, VOS = 1.2 V 850 mV
OUT_x_AMP = 3, boost on, VOS = 1.6 V 910 mV
VOUT-DIFF Differential output voltage swing,
peak-to-peak		 2×VOD V
VOS Output common mode OUT_x_AMP = 1,
boost on, DC shift setting 2		 0.8 V
OUT_x_AMP = 1,
boost on, DC shift setting 4		 1.0 V
OUT_x_AMP = 1,
boost on, DC shift setting 6		 1.2 V
OUT_x_AMP = 1,
boost on, DC shift setting 8		 1.4 V
OUT_x_AMP = 1,
boost on, DC shift setting 10		 1.6 V
tSK Output-to-output skew, same group(4) Same post divider, output divide values, and output format 50 ps
tSK_GRP Output-to-output skew, between groups(4) Same post divider, output divide values, and output format.  Not including OUT14 and OUT15. 80 ps
Same post divider, output divide values, and output format. 150 ps
tR/tF Output rise/fall time 20% to 80%, < 500 MHz 130 300 ps
± 100 mV around center point 50 120 ps
PNFLOOR Output phase noise floor(3)
(fOFFSET > 10 MHz)		 122.88 MHz -162 dBc/Hz
ODC Output duty cycle(10) 45 55 %
LVPECL Output Characteristics (OUTx)
fOUT Maximum output frequency(2) 1000 MHz
VOD Output voltage swing (|VOH - VOL|) OUT_x_AMP = 0, VOS = 1.2 V 450 mV
OUT_x_AMP = 1, VOS = 1.2 V 600 mV
OUT_x_AMP = 2, VOS = 1.2 V 800 mV
OUT_x_AMP = 2, VOS = 1.6 V 700 mV
OUT_x_AMP = 3, VOS = 1.2 V 930 mV
OUT_x_AMP = 3, VOS = 1.6 V 840 mV
VOUT-DIFF Differential output voltage swing,
peak-to-peak		 2×VOD V
VOS Output common mode OUT_x_AMP = 1,
DC shift setting 2		 0.7 V
OUT_x_AMP = 1,
DC shift setting 4		 0.8 V
OUT_x_AMP = 1,
DC shift setting 6		 1.0 V
OUT_x_AMP = 1,
DC shift setting 8		 1.2 V
OUT_x_AMP = 1,
DC shift setting 10		 1.4 V
OUT_x_AMP = 1,
DC shift setting 12		 1.5 V
tSK Output-to-output skew, same group(4) Same post divider, output divide values, and output format 50 ps
tSK_GRP Output-to-output skew, between groups(4) Same post divider, output divide values, and output format 80 ps
Same post divider, output divide values, and output format.  Not including OUT14 and OUT15. 150 ps
tR/tF Output rise/fall time 20% to 80% 150 300 ps
± 100 mV around center point 200 ps
PNFLOOR Output phase noise floor(3)
(fOFFSET > 10 MHz)		 122.88 MHz -162 dBc/Hz
ODC Output duty cycle(10) 45 55 %
CML Open Collector Output Characteristics (OUTx)
fOUT Output frequency(2) OUT4 or OUT6 CML open collector outputs 3000 MHz
VOD Output voltage swing (|VOH - VOL|) Normal swing, OUT_x_AMP = 1, 2949.12 MHz 400 600 mV
VOD Output voltage swing (|VOH - VOL|) High swing,  OUT_x_AMP = 2, 2949.12 MHz 600 800 mV
VOUT-DIFF Differential output voltage swing,
peak-to-peak		 2×VOD Vpp
tSK Output-to-output skew Same post divider, output divide values, and output type 50 ps
tR/tF Output rise/fall time 20% to 80%, 2949.12 MHz 150 300 ps
± 100 mV around center point, 2949.12 MHz 25 100 ps
PNFLOOR Output duty cycle(10) 2949.12 MHz -156 dBc/Hz
ODC Output duty cycle 45 55 %
1.8-V LVCMOS Output Characteristics (OUT0/1)
fOUT Maximum output frequency 200 MHz
VOH Output high voltage IOH = 1 mA 1.5 V
VOL Output low voltage IOL = 1 mA 0.2 V
IOH Output high current VO = 0.9 V -18 mA
IOL Output low current 18 mA
tR/tF Output rise/fall time 20% to 80% 150 ps
tSK Output-to-output skew Same post divider, output divide values, and output type 100 ps
Same post divider, output divide values, LVCMOS-to-DIFF 1.5 ns
PNFLOOR Output phase noise floor
(fOFFSET > 10 MHz)		 66.66 MHz -155 dBc/Hz
ODC Output duty cycle(10) 45 55 %
ROUT Output impedance 50 Ω
2.65-V LVCMOS Output Characteristics (OUT0/1)
fOUT Maximum output frequency 200 MHz
VOH Output high voltage IOH = 1 mA 2.3 V
VOL Output low voltage IOL = 1 mA 0.2 V
IOH Output high current VO = 1.25 V -25 mA
IOL Output low current 25 mA
tR/tF Output rise/fall time 20% to 80% 150 ps
tSK Output-to-output skew Same post divider, output divide values, and output type 100 ps
Same post divider, output divide values, LVCMOS-to-DIFF 1.5 ns
PNFLOOR Output phase noise floor
(fOFFSET > 10 MHz)		 66.66 MHz -155 dBc/Hz
ODC Output duty cycle(10) 45 55 %
ROUT Output impedance 50 Ω
3-Level Logic Input Characteristics (GPIO0, GPIO1, GPIO2, SCS_ADD)
VIH Input high voltage 1.4 V
VIM Input mid voltage 0.6 1 V
VIM Input mid voltage self-bias Input floating with internal bias and PD# pulled low 0.7 0.9 V
VIL Input low voltage 0.4 V
IIH Input high current VIH = VDD -40 40 µA
IIL Input low current VIL = GND -40 40 µA
CIN Input capacitance 2 pF
2-Level Logic Input Characteristics (PD#, SCK, SDIO, SCS_ADD; GPIO0, GPIO1 and GPIO2 after power up)
VIH Input high voltage 1.2 V
VIL Input low voltage 0.4 V
IIH Input high current VIH = VDD, except PD# -40 40 µA
IIL Input low current VIL = GND, except PD# -40 40 µA
CIN Input capacitance 2 pF
Logic Output Characteristics (GPIO0, GPIO1, GPIO2, SDIO)
VOH Output high voltage IOH = 1 mA 2.4 V
VOL Output low voltage IOL = 1 mA 0.4 V
tR/tF Output rise/fall time 20% to 80%, LVCMOS mode, 1 kΩ to GND 500 ps
SPI Timing Requirements (SDIO, SCK, SCS_ADD)
fSCK SPI clock rate 20 MHz
SPI clock rate; during SRAM read and write operations 5 MHz
t1 SCS to SCK setup time (start communication cycle) 10 ns
t2 SDI to SCK setup time 10 ns
t3 SDI to SCK hold time 10 ns
t4 SCK high time 25 ns
t5 SCK low time 25 ns
t6 SCK to SDO valid read-back data 20 ns
t7 SCS pulse width 20 ns
t8 SCK to SCS setup time (end communication cycle) 10 ns
I2C Timing Requirements (SDIO, SCK)
VIH Input high voltage 1.2 V
VIL Input low voltage 0.5 V
IIH Input leakage -15 15 µA
VOL Output low voltage IOL = 3 mA 0.3 V
fSCL I2C clock rate Standard 100 kHz
Fast mode 400
tSU(START) START condition setup time SCL high before SDA low 0.6 µs
tH(START) START condition hold time SCL low after SDA low 0.6 µs
tW(SCLH) SCL pulse width high 0.6 µs
tW(SCLL) SCL pulse width low 1.3 µs
tSU(SDA) SDA setup time 100 ns
tH(SDA) SDA hold time SDA valid after SCL low 0 0.9 µs
tR(IN) SDA/SCL input rise time 300 ns
tF(IN) SDA/SCL input fall time 300 ns
tF(OUT) SDA output fall time CBUS ≤ 400 pF 300 ns
tSU(STOP) STOP condition setup time 0.6 µs
tBUS Bus free time between STOP and START 1.3 µs
Other Characteristics
tPHO-VAR Input-to-output phase offset variation over PVT Zero delay mode, RF clocks only, INx = 122.88 MHz, OUTx = 2949.12 MHz or 2457.6 MHz or 1474.56 MHz or 1228.8 MHz or 737.28 MHz or 614.4 MHz or 153.6 MHz or 122.88 MHz   -200 200 ps
tANA-DEL-ERR Analog delay error for any step setting(9) VCBO = 2457.6 MHz, PLL3_PRI_DIV = ÷5, OUTx = 491.52 MHz, Analog Delay step = 32.8 ps -16 16 ps
tDIG-DEL Digital delay step size on device clock and SYSREF outputs SYSREF analog delay off for half cycle steps and OUT_x_y_SR_CH_DIV_BYPASS = 1 ½ VCO post divider cycle
PSNR Spur induced by power supply noise (VN = 50 mVpp)(5) (6) Vcc = 3.3V, HSDS, LVDS, and LVPECL output -75 dBc
SPUR Highest Spur level at 100 Hz to 40 MHz offset(6) (7) fOUTx = 122.88 MHz from VCO3, VCO2 = 5625 MHz, and VCO1 = 5000 MHz -90 dBc
Highest spur level within12 kHz to 40 MHz band(6) (7) fOUTx = 122.88 MHz, AC-DIFF or LVDS (all outputs operating with differential level and no SYSREF) -75 dBc
PLL Clock Output Performance Characteristics
RJ1 RMS phase jitter of DPLL1/APLL1 (12 kHz to 20 MHz)(3) (7) XO = 38.88 MHz, APLL1 = 5000 MHz or 5156.25 MHz, OUTx = 312.5 or 322.265625 MHz, all differential output types 200 250 fs RMS
RJ2 RMS phase jitter of DPLL2/APLL2 (12 kHz to 20 MHz)(3) (7) XO = 38.88 MHz, APLL2 = 5898.24 MHz or 5650 MHz, OUTx = 245.76 MHz or 312.5 MHz, all differential output types 120 180 fs RMS
RJ3 RMS phase jitter of DPLL3/APLL3 (12 kHz to 20 MHz)(3) (7) XO = 38.88 MHz, APLL3 = 2457.6 MHz, OUTx = 245.76 MHz, all differential output types 50 80 fs RMS
RJ4 RMS phase jitter of DPLL3/APLL3 (12 kHz to 20 MHz)(3) (7) XO = 38.88 MHz, APLL3 = 2457.6 MHz, OUTx = 491.52 MHz, all differential output types 40 70 fs RMS
PN-APLL3 Phase Noise of DPLL3/APLL3 at 800 kHz offset 38.88 MHz XO, VCO3 = 2457.6 MHz, 2457.6 MHz CML output -147 dBc/Hz
PNTDC Output close-in phase noise for DPLL1 and DPLL2
(fOFFSET = 100 Hz)		 122.88 MHz AC-DIFF or LVDS, TCXO = 38.88 MHz, fTDC > 20 MHz, DPLL-BW = 1 kHz -116 dBc/Hz
Output close-in phase noise for DPLL3
(fOFFSET = 100 Hz)		 122.88 MHz AC-DIFF or LVDS, TCXO = 38.88 MHz, fTDC > 20 MHz, DPLL-BW = 1 kHz -110 dBc/Hz
BW DPLL bandwidth range(8) Programmed bandwidth setting 0.01 4000 Hz
JPK DPLL closed-loop jitter peaking(11) fIN = 25 MHz, fOUT = 10 MHz, DPLL BW = 0.1 Hz or 10 Hz 0.1 dB
JTOL Jitter tolerance Compliant with G.8262 Options 1 and 2, Jitter modulation = 10 Hz, 25.78125 Gbps 6455 UI p-p
tHITLESS Phase transient during hitless switch Valid for a single switchover event between two clock inputs at the same frequency 122.88 MHz -100 100 ps
fHITLESS Frequency transient during hitless switch Valid for a single switchover event between two clock inputs at the same frequency 122.88 MHz -10 10 ppb
(2) Total device current can be estimated by summing the individual IDD_x and IDDO_x per pin for all blocks enabled in a given configuration.
(5) Configuration A (All blocks on): fREF[0:1] = 156.25 MHz, 10 MHz, fXO = 38.88 MHz. All DPLLs and APLLs enabled, fVCO1 = 5 GHz, fVCO2 = 5.625 GHz, fVCO3 = 2.4576 GHz, PLL1_P1 = 5, PLL2_P1 = 9, PLL3_P1 = 5.  All outputs on.
(6) Configuration B (All blocks on): fREF[0:1] = 25 MHz, fXO = 38.88 MHz. DPLL[3:1]/APLL[3:1] enabled, fVCO1 = 5.15625 GHz, fVCO2 = 6.25 GHz, fVCO3 = 2.4576 GHz, PLL1_P1 = 8, PLL2_P1 = 5
(1) In order to meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all
input clocks is 0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input
slew rate is reduced.
(2) An output frequency over the fOUT max spec is possible, but the output swing may be less than the VOD min spec.
(3) Any output clock except OUT2, OUT3, OUT14, or OUT15.
(4) Output groups are (OUT0 and 1), (OUT2 and 3), (OUT4 to 7), (OUT8 to 13) and (OUT14 and 15).
(5) PSNR is the single-sideband spur level (in dBc) measured when sinusoidal noise with amplitude VN and frequency between 100 kHz and 1 MHz is injected onto VDD and VDDO_x pins.
(6) DJSPUR (ps pk-pk) = [2 × 10(dBc/20) / (π × fOUT) × 1E6], where dBc is the PSNR or SPUR level (in dBc) and fOUT is the output frequency (in MHz).
(7) Excludes output crosstalk and integer-boundary spurs.
(8) DPLL loop bandwidth must be less than 1/100 of TDC frequency and less than 1/10 of APLL loop bandwidth.
(9) Analog delay step size and worst case time error is a function of the input frequency to the SYSREF block and analog delay block configuration.  Maximum analog delay error is half the analog delay step size.
(10) Parameter is specified for PLL outputs divided from either VCO domain.
(11) The TICS Pro software configures the closed-loop jitter peaking for 0.1 dB or less based on the programmed DPLL bandwidth setting.