8.3.1 Programmable Gain Amplifier

The LMP91050 offers two programmable gain modes (low or high) with four programmable gain settings each. The purpose of the gain mode is to enable thermopiles with larger dark voltage levels. All gain settings are accessible through bits GAIN1 and GAIN2[1:0]. The low-gain mode has a range of 167 V/V to 1335 V/V while the high-gain mode has a range of 1002 V/V to 7986 V/V. The PGA is referenced to the internally generated VCM. Input signal, referenced to this VCM voltage, should be within ±2 mV (see VINMAX_HGM specification) in high-gain mode. In the low gain mode the first stage will provide a gain of 42 V/V instead of 250 V/V, thus allowing a larger maximum input signal up to ±12 mV (VINMAX_LGM).

8.3.2 External Filter

The LMP91050 offers two different measurement modes selectable through EXT_FILT bit. EXT_FILT bit is present in the Device configuration register and is programmable through SPI.

An external filter can be applied when EXT_FILT = 1. A typical band pass filter is shown in the picture below. Resistor and capacitor can be connected to the CMOUT pin of the LMP91050 as shown. Discrete component values have been added for reference.

Figure 21. Typical Bandpass Filter

8.3.3 Offset Adjust

Procedure of the offset adjust is to first measure the dark signal, program the DAC to adjust, and then measure in a second cycle the residual of the dark signal for further signal manipulation within the µC. The signal source is expected to have an offset component (dark signal) larger than the actual signal. During the dark phase, the time when no light is detected by the sensor, the µC can program LMP91050 internal DAC to compensate for a measured offset. A low output offset voltage temperature drift (TCVOS) ensures system accuracy over temperature. See Figure 22 below which plots the maximum TCVOS allowed over a given temperature drift in order to achieve n bit system accuracy.

Figure 22. System Accuracy vs. TCVOS and Temperature Drift

8.3.4 Common-Mode Generation

As the offset of the sensor is bipolar, there is a need to supply a VCM to the sensor. This can be programmed as 1.15 V or 2.59 V (approximately mid rail of 3.3-V or 5-V supply). TI does not recommend to use 2.59-V VCM with a 3.3-V supply

8.3.5 CSB

Chip Select is a active-low signal. CSB needs to be asserted throughout a transaction. That is, CSB should not pulse between the Instruction Byte and the Data Byte of a single transaction.

CSB may be permanently tied low for a 2-wire SPI communication protocol.

8.5.1 SPI Interface

An SPI interface is available in order to program the device parameters like PGA gain of two stages, enabling external filter, enabling power for PGAs, offset adjust and common-mode (VCM) voltage.

8.5.1.2 Communication Protocol

Communication on the SPI normally involves Write and Read transactions. Write transaction consists of single Write Command Byte, followed by single Data byte. The following figure shows the SPI Interface Protocol for write transaction.

Figure 23. SPI Interface Protocol

For Read transactions, user first needs to write into a SDIO mode enable register for enabling the SPI read mode. Once the device is enabled for Reading, the data is driven out on the SDIO pin during the Data field of the Read Transaction. SDIO pin is designed as a bidirectional pin for this purpose. Figure 24 shows the Read transaction. The sequence of commands that need to be issued by the SPI Master to enable SPI read mode is shown in Figure 25.

Figure 24. Read Transaction

Figure 25. Enable SDIO Mode for Reading SPI Registers

Table 4. Register Descriptions

8.6.1 Device Configuration

8.6.2 DAC Configuration

The output DC level will shift according to the formula Vout_shift = -33.8mV * (NDAC - 128).

8.6.3 SDIO Mode

Write-only