SNAS696C March   2017  – April 2019 LMX2594

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Reference Oscillator Input
      2. 7.3.2  Reference Path
        1. 7.3.2.1 OSCin Doubler (OSC_2X)
        2. 7.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 7.3.2.3 Programmable Multiplier (MULT)
        4. 7.3.2.4 Post-R Divider (PLL_R)
        5. 7.3.2.5 State Machine Clock
      3. 7.3.3  PLL Phase Detector and Charge Pump
      4. 7.3.4  N-Divider and Fractional Circuitry
      5. 7.3.5  MUXout Pin
        1. 7.3.5.1 Lock Detect
        2. 7.3.5.2 Readback
      6. 7.3.6  VCO (Voltage-Controlled Oscillator)
        1. 7.3.6.1 VCO Calibration
        2. 7.3.6.2 Determining the VCO Gain
      7. 7.3.7  Channel Divider
      8. 7.3.8  Output Buffer
      9. 7.3.9  Power-Down Modes
      10. 7.3.10 Phase Synchronization
        1. 7.3.10.1 General Concept
        2. 7.3.10.2 Categories of Applications for SYNC
        3. 7.3.10.3 Procedure for Using SYNC
        4. 7.3.10.4 SYNC Input Pin
      11. 7.3.11 Phase Adjust
      12. 7.3.12 Fine Adjustments for Phase Adjust and Phase SYNC
      13. 7.3.13 Ramping Function
        1. 7.3.13.1 Manual Pin Ramping
          1. 7.3.13.1.1 Manual Pin Ramping Example
        2. 7.3.13.2 Automatic Ramping
          1. 7.3.13.2.1 Automatic Ramping Example (Triangle Wave)
      14. 7.3.14 SYSREF
        1. 7.3.14.1 Programmable Fields
        2. 7.3.14.2 Input and Output Pin Formats
          1. 7.3.14.2.1 Input Format for SYNC and SysRefReq Pins
          2. 7.3.14.2.2 SYSREF Output Format
        3. 7.3.14.3 Examples
        4. 7.3.14.4 SYSREF Procedure
      15. 7.3.15 SysRefReq Pin
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Recommended Initial Power-Up Sequence
      2. 7.5.2 Recommended Sequence for Changing Frequencies
      3. 7.5.3 General Programming Requirements
    6. 7.6 Register Maps
      1. 7.6.1  General Registers R0, R1, & R7
        1. Table 24. Field Descriptions
      2. 7.6.2  Input Path Registers
        1. Table 25. Field Descriptions
      3. 7.6.3  Charge Pump Registers (R13, R14)
        1. Table 26. Field Descriptions
      4. 7.6.4  VCO Calibration Registers
        1. Table 27. Field Descriptions
      5. 7.6.5  N Divider, MASH, and Output Registers
        1. Table 28. Field Descriptions
      6. 7.6.6  SYNC and SysRefReq Input Pin Register
        1. Table 29. Field Descriptions
      7. 7.6.7  Lock Detect Registers
        1. Table 30. Field Descriptions
      8. 7.6.8  MASH_RESET
        1. Table 31. Field Descriptions
      9. 7.6.9  SysREF Registers
        1. Table 32. Field Descriptions
      10. 7.6.10 CHANNEL Divider Registers
        1. Table 33. Field Descriptions
      11. 7.6.11 Ramping and Calibration Fields
        1. Table 34. Field Descriptions
      12. 7.6.12 Ramping Registers
        1. 7.6.12.1 Ramp Limits
          1. Table 35. Field Descriptions
        2. 7.6.12.2 Ramping Triggers, Burst Mode, and RAMP0_RST
          1. Table 36. Field Descriptions
        3. 7.6.12.3 Ramping Configuration
          1. Table 37. Field Descriptions
      13. 7.6.13 Readback Registers
        1. Table 38. Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 OSCin Configuration
      2. 8.1.2 OSCin Slew Rate
      3. 8.1.3 RF Output Buffer Power Control
      4. 8.1.4 RF Output Buffer Pullup
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.1 General Registers R0, R1, & R7

Figure 35. Registers Excluding Address
Address D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
R0 RAMP_EN VCO_PHASE_SYNC_EN 1 0 0 1 OUT_MUTE FCAL_HPFD_ADJ FCAL_LPFD_ADJ 1 FCAL_EN MUXOUT_LD_SEL RESET POWERDOWN
R1 0 0 0 0 1 0 0 0 0 0 0 0 1 CAL_CLK_DIV
R7 0 OUT_FORCE 0 0 0 0 0 0 1 0 1 1 0 0 1 0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 24. Field Descriptions

Location Field Type Reset Description
R0[15] RAMP_EN R/W 0 0: Disable frequency ramping mode
1: Enable frequency ramping mode
R0[14] VCO_PHASE_SYNC R/W 0 0: Disable phase SYNC mode
1: Enable phase SYNC mode
R0[9] OUT_MUTE R/W 0 Mute the outputs when the VCO is calibrating.
0: Disabled. If disabled, also be sure to enable OUT_FORCE
1: Enabled. If enabled, also be sure to disable OUT_FORCE
R0[8:7] FCAL_HPFD_ADJ R/W Set this field in accordance to the phase-detector frequency for optimal VCO calibration.
0: fPD ≤ 100 MHz
1: 100 MHz < fPD ≤ 150 MHz
2: 150 MHz < fPD ≤ 200 MHz
3: fPD >200 MHz
R0[6:5] FCAL_LPFD_ADJ R/W 0 Set this field in accordance to the phase detector frequency for optimal VCO calibration.
0: fPD ≥ 10 MHz
1: 10 MHz > fPD ≥ 5 MHz
2: 5 MHz > fPD ≥ 2.5 MHz
3: fPD < 2.5 MHz
R0[3] FCAL_EN R/W 0 Enable the VCO frequency calibration. Also note that the action of programming this bit to a 1 activates the VCO calibration
R0[2] MUXOUT_LD_SEL R/W 0 Selects the state of the function of the MUXout pin
0: Readback
1: Lock detect
R0[1] RESET R/W 0 Resets and holds all state machines and registers to default value.
0: Normal operation
1: Reset
R0[0] POWERDOWN R/W 0 Powers down entire device
0: Normal operation
1: Powered down
R1[2:0] CAL_CLK_DIV R/W 3 Sets divider for VCO calibration state machine clock based on input frequency.
0: Divide by 1. Use for fOSC ≤ 200 MHz
1: Divide by 2. Use for fOSC ≤ 400 MHz
2: Divide by 4. Use for fOSC ≤ 800 MHz
3: Divide by 8. All fOSC

If user is not concerned with lock time, it is recommended to set this value to 3. By slowing down the VCO calibration, the best and most repeatable VCO phase noise can be attained
R7[14] OUT_FORCE R/W 0 Works with OUT_MUTE in disabling outputs when VCO calibrating.