SNAS783C June   2020  – February 2021 LMX2820

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Reference Oscillator Input
      2. 7.3.2  Input Path
        1. 7.3.2.1 Input Path Doubler (OSC_2X)
        2. 7.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 7.3.2.3 Programmable Input Multiplier (MULT)
        4. 7.3.2.4 R Divider (PLL_R)
      3. 7.3.3  PLL Phase Detector and Charge Pump
      4. 7.3.4  N Divider and Fractional Circuitry
        1. 7.3.4.1 Integer N Divide Portion (PLL_N)
        2. 7.3.4.2 Fractional N Divide Portion (PLL_NUM and PLL_DEN)
        3. 7.3.4.3 Modulator Order (MASH_ORDER)
      5. 7.3.5  LD Pin Lock Detect
      6. 7.3.6  MUXOUT Pin and Readback
      7. 7.3.7  Internal VCO
        1. 7.3.7.1 VCO Calibration
          1. 7.3.7.1.1 Determining the VCO Gain and Ranges
      8. 7.3.8  Channel Divider
      9. 7.3.9  Output Frequency Doubler
      10. 7.3.10 Output Buffer
      11. 7.3.11 Power-Down Modes
      12. 7.3.12 Phase Synchronization for Multiple Devices
        1. 7.3.12.1 SYNC Categories
        2. 7.3.12.2 Phase Adjust
          1. 7.3.12.2.1 Using MASH_SEED to Create a Phase Shift
          2. 7.3.12.2.2 Static vs. Dynamic Phase Adjust
          3. 7.3.12.2.3 Fine Adjustments to Phase Adjust
      13. 7.3.13 SYSREF
      14. 7.3.14 Fast VCO Calibration
      15. 7.3.15 Double Buffering (Shadow Registers)
      16. 7.3.16 Output Mute Pin and Ping Pong Approaches
    4. 7.4 Device Functional Modes
      1. 7.4.1 External VCO Mode
      2. 7.4.2 External Feedback Input Pins
        1. 7.4.2.1 PFDIN External Feedback Mode
        2. 7.4.2.2 RFIN External Feedback Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Treatment of Unused Pins
      2. 8.1.2 External Loop Filter
      3. 8.1.3 Using Instant Calibration
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Initialization and Power-on Sequencing
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

3.15 V ≤ VCC ≤ 3.45 V, –40 °C ≤ TA ≤ 85 °C. Typical values are at VCC = 3.3 V, 25 °C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
ICC Supply current One direct RF output(1) 500 mA
One divided down RF output(2) 580
One RF output with VCO doubler enabled(3) 590
RFIN External Feedback Mode, Internal VCO 530
PFDIN External Feedback Mode, Internal VCO(5) 455
External VCO Mode(4) 290
ICCPOR Power-on-reset current 234
ICCPD Power-down current 10
INPUT SIGNAL PATH
fOSCin OSCin input frequency OSC_2X = 0 (Doubler bypassed) 5 1400 MHz
OSC_2X = 1 (Doubler enabled);
Single-ended input buffer		 5 250
VOSCin OSCin input voltage(6) Single-ended input buffer 0.3 3.6 Vpp
Differential input buffer 0.1 1
fMULTin Multiplier input frequency MULT ≥ 3 30 70 MHz
fMULTout Multiplier output frequency 180 250
PLL
fPD Phase detector frequency(7) Integer channel 5 400 MHz
1st and 2nd order modulator 5 300
3rd order modulator 5 225
ICPout Charge pump current CPG = 1 1.4 mA
CPG = 8 2.8
CPG = 4 5.6
CPG = 12 8.4
CPG = 15 15.4
PNPLL_1/f Normalized PLL 1/f noise(8) –134 dBc/Hz
PNPLL_Flat Normalized PLL noise floor(8) Integer channel(9) –236
Fractional channel(10) –236
fRFIN RFin input frequency 1000 22600 MHz
PRFIN RFin input power –10 5 dBm
RLRFIN RFin return loss 2 GHz ≤ fRFin ≤ 22 GHz −8 dB
fPFDIN PFDin input frequency 20 2000 MHz
vPFDIN PFDin input voltage 0.2 2 Vpp
VCO
fVCO VCO frequency 5650 11300 MHz
PNVCO Open-loop VCO phase noise fVCO = 6.0 GHz 10 kHz -77.0 dBc/Hz
100 kHz -110.3
1 MHz -131.9
10 MHz -151.0
100 MHz -159.5
fVCO = 6.8 GHz 10 kHz -76.5
100 kHz -109.3
1 MHz -130.7
10 MHz -149.8
100 MHz -159.3
fVCO = 7.6 GHz 10 kHz -75.8
100 kHz -108.5
1 MHz -130.2
10 MHz -149.2
100 MHz -159.2
fVCO = 8.4 GHz 10 kHz -74.7
100 kHz -107.6
1 MHz -129.4
10 MHz -148.8
100 MHz -159.0
fVCO = 9.4 GHz 10 kHz -76.0
100 kHz -105.5
1 MHz -128.0
10 MHz -147.4
100 MHz -157.9
fVCO = 10.2 GHz 10 kHz -75.9
100 kHz -105.6
1 MHz -127.5
10 MHz -146.8
100 MHz -157.6
fVCO = 11.2 GHz 10 kHz -75.4
100 kHz -104.4
1 MHz -126.4
10 MHz -145.8
100 MHz -156.5
KVCO VCO gain fVCO = 6.0 GHz 95 MHz/V
fVCO = 6.8 GHz 108
fVCO = 7.6 GHz 131
fVCO = 8.4 GHz 140
fVCO = 9.4 GHz 149
fVCO = 10.2 GHz 156
fVCO = 11.2 GHz 139
tVCOcal VCO calibration time fOSCin = fPD = 100 MHz;
Switch between 5.65 GHz and 11.3 GHz;
Using Instant Calibration
0.47 μF capacitor at VbiasVCO pin		 2.5 µs
|ΔTCL| Allowable temperature drift(11) VCO not being recalibrated;
–40 °C ≤ TA ≤ 85 °C		 125 °C
RF OUTPUT
fOUT RF output frequency 45 22600 MHz
POUT Single-ended output power(12) OUTx_PWR=7 fOUT = 22 GHz 3 dBm
fOUT = 11 GHz 5
fOUT ≤ 5.5 GHz 6
H1/2 1/2 harmonic(13) fOUT = 2 x fVCO = 22 GHz  −45 dBc
H3/2 3/2 harmonic fOUT = 2 x fVCO = 11.3 GHz to 22.6 GHz −65
H2 Second harmonic fVCO = fOUT = 11 GHz −20
fVCO = 11 GHz; fOUT = 5.5 GHz −35
fOUT = 2 x fVCO = 11.3 GHz to 22.6 GHz −25
H3 Third harmonic fVCO = fOUT = 11 GHz −20
fVCO = 11 GHz; fOUT = 5.5 GHz −10
PMUTE Single-ended output power when output is muted(12) fOUT = 22 GHz −32 dBm
fOUT = 11 GHz −32
fOUT = 5.5 GHz −53
tMUTE Mute enable time fOUT = 11 GHz 200 ns
tunMUTE Mute disable time fOUT = 11 GHz 200
isoCH Channel to channel isolation fOUTA = 11 GHz; fOUTB = 5.5 GHz;
OUTx_PWR=7		 –40 dBc
PHASE SYNCHRONIZATION
fOSCinSYNC OSCin input frequency with SYNC Category 3 5 200 MHz
DIGITAL INTERFACE (CE, SCK, SDI, CS#, PSYNC, MUTE)
VIH High-level input voltage 1.2 VCC V
VIL Low-level input voltage 0.6
IIH High-level input current CS#, MUTE, CE 25 µA
SCK, SDI, PSYNC 70
IIL Low-level input current −1
VOH High-level output voltage MUXout, LD Load current = –3 mA VCC–0.5 V
VOL Low-level output voltage Load current = 3 mA 0.4
(1) fOSCin = fPD = 100 MHz; fVCO = fOUT = 11 GHz; POUT = 0 dBm; OSC_2X = 0; MULT = 1.
(2) fOSCin = fPD = 100 MHz; fVCO = 11 GHz; fOUT = 5.5 GHz; POUT = 0 dBm; OSC_2X = 0; MULT = 1.
(3) fOSCin = fPD = 100 MHz; fVCO = 11 GHz; fOUT = 22 GHz; POUT = 0 dBm; OSC_2X = 1; MULT = 1.
(4) fOSCin = fPD = 100 MHz; fRFin = 11 GHz; fOUT = 11 GHz (from external VCO); OSC_2X = 0; MULT = 1.
(5) fOSCin = fPD = 100 MHz; fPFDin = 2 GHz; fOUT = 11 GHz (from external VCO); OSC_2X = 0; MULT = 1.
(6) See applications section for definition of OSCin input voltage.
(7) For lower VCO frequencies, the N-divider minimum value can limit the phase detector frequency.
(8) Measured with a clean OSCin signal with a high slew rate using a wide loop bandwidth. The noise metrics model the PLL noise for an infinite loop bandwidth as: PLL_Total = 10∙log[10(PLL_Flat/10)+10(PLL_Flicker/10)]; PLL_Flat = PN1 Hz + 20∙log(N) + 10*log(fPD); PLL_Flicker = PN10 kHz - 10∙log(Offset/10 kHz) + 20∙log(fOUT/1 GHz).
(9) fOSCin = 100 MHz,  fPD = 200 MHz; fVCO = fOUT = 11 GHz.
(10) fOSCin = fPD = 100 MHz; fVCO = fOUT = 10.999 GHz; Fractional denominator = 1000.
(11) Not tested in production. Ensured by characterization. Allowable temperature drift refers to programming the device at an initial temperature and allowing this temperature to drift WITHOUT reprogramming the device, and still have the device stay at lock. This change could be up or down in temperature and the specification does not apply to temperatures that go outside the recommended operating temperatures of the device.
(12) Measured with one of the RF output differential pair pins, the unused pin is 50-Ω terminated. See applications section for details.
(13) One RF output is active. Measured differentially with JSO-51-471/6S balun.  Consult typical performance plots to see how this varies over conditions.