SLVS582K April   2006  – December 2024 LP2950 , LP2951

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics (Both Legacy and New Chip)
    6. 5.6 Timing Requirements (New Chip only)
    7. 5.7 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable
      2. 6.3.2 Dropout Voltage
      3. 6.3.3 Current Limit
      4. 6.3.4 Undervoltage Lockout (UVLO)
      5. 6.3.5 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Shutdown Mode
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Reverse Current
      2. 7.1.2 Input and Output Capacitor Requirements
      3. 7.1.3 Estimating Junction Temperature
      4. 7.1.4 Power Dissipation (PD)
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
        1. 7.2.1.1 Recommended Capacitor Types
          1. 7.2.1.1.1 Recommended Capacitors for the Legacy Chip
            1. 7.2.1.1.1.1 ESR Range (Legacy Chip)
          2. 7.2.1.1.2 Recommended Capacitors for the New Chip
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Feedback Resistor Selection
        2. 7.2.2.2 Feedforward Capacitor
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Device Nomenclature
    4. 8.4 Documentation Support
      1. 8.4.1 Related Documentation
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
ESR Range (Legacy Chip)

The regulator control loop relies on the ESR of the output capacitor to provide a zero to add sufficient phase margin to provide unconditional regulator stability. This condition requires the closed-loop gain to intersect the open-loop response in a region where the open-loop gain rolls off at 20dB/decade. This roll off makes sure that the phase is always less than 180° (phase margin greater than 0°) at unity gain. Thus, a minimum-maximum range for the ESR must be observed.

The upper limit of this ESR range is established by the fact that an ESR that is too high can result in the zero occurring too soon, causing the gain to roll off too slowly. This effect, in turn, allows a third pole to appear before unity gain and introduces enough phase shift to cause instability. This phase shift typically limits the maximum ESR to approximately 5Ω.

Conversely, the lower limit of the ESR range is tied to the fact that an ESR that is too low shifts the zero too far out, past unity gain, which allows the gain to roll off at 40dB/decade at unity gain, resulting in a phase shift of greater than 180°. Typically, this limits the minimum ESR to approximately 20mΩ to 30mΩ.

For specific ESR requirements, see the Section 5.7 section.