The device has an internal current
limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a brick-wall scheme. In a high-load current
fault, the brick-wall scheme limits the output current to the current limit
(ICL). ICL is listed in the
LP2982 50-mA Micropower Ultra-Low-Dropout LDO in SOT-23 Package
LP2982 50-mA, Low-Noise, Low-Dropout Regulator in SOT-23 Package
LP2982 50-mA, Low-Noise, Low-Dropout Regulator in SOT-23 Package
Features
Features
Applications
Applications
Description
Description
Table of Contents
Table of Contents
Pin Configuration and Functions
Pin Configuration and Functions
Specifications
Specifications
Absolute Maximum Ratings
Absolute Maximum Ratings
ESD Ratings
ESD Ratings
Recommended Operating Conditions
Recommended Operating Conditions
Thermal Information
Thermal Information
Electrical Characteristics
Electrical Characteristics
Typical Characteristics
Typical Characteristics
Detailed Description
Detailed Description
Overview
Overview
Functional Block Diagram
Functional Block Diagram
Feature Description
Feature Description
Output Enable
Output Enable
Dropout Voltage
Dropout Voltage
Current Limit
Current Limit
Undervoltage Lockout (UVLO)
Undervoltage Lockout (UVLO)
Output Pulldown
Output Pulldown
Thermal Shutdown
Thermal Shutdown
Device Functional Modes
Device Functional Modes
Device Functional Mode Comparison
Device Functional Mode Comparison
Normal Operation
Normal Operation
Dropout Operation
Dropout Operation
Disabled
Disabled
Application and Implementation
Application and Implementation
Application Information
Application Information
Recommended Capacitor Types
Recommended Capacitor Types
Recommended Capacitors for the Legacy Chip
Recommended Capacitors for the Legacy Chip
Recommended Capacitors for the New Chip
Recommended Capacitors for the New Chip
Input and Output Capacitor Requirements
Input and Output Capacitor Requirements
Noise Bypass Capacitor (CBYPASS)
Noise Bypass Capacitor (CBYPASS)
Reverse Current
Reverse Current
Power Dissipation (PD)
Power Dissipation (PD)
Estimating Junction Temperature
Estimating Junction Temperature
Typical Application
Typical Application
Design Requirements
Design Requirements
Detailed Design Procedure
Detailed Design Procedure
ON/ OFF Input Operation
ON/ OFF Input Operation
Application Curves
Application Curves
Power Supply Recommendations
Power Supply Recommendations
Layout
Layout
Layout Guidelines
Layout Guidelines
Layout Example
Layout Example
Device and Documentation Support
Device and Documentation Support
Device Nomenclature
Device Nomenclature
Third-Party Products Disclaimer
Third-Party Products Disclaimer
Documentation Support
Documentation Support
Related Documentation
Related Documentation
Receiving Notification of Documentation Updates
Receiving Notification of Documentation Updates
Support Resources
Support Resources
Trademarks
Trademarks
Electrostatic Discharge Caution
Electrostatic Discharge Caution
Glossary
Glossary
Revision History
Revision History
Revision History
Revision History
Mechanical, Packaging, and Orderable Information
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE AND DISCLAIMER
IMPORTANT NOTICE AND DISCLAIMER
LP2982 50-mA, Low-Noise, Low-Dropout Regulator in SOT-23 Package
LP2982 50-mA, Low-Noise, Low-Dropout Regulator in SOT-23 Package
Features
L
Updated the numbering format for tables, figures, and
cross-references throughout the document
yes
L
Changed entire document to align with current family
format
yes
L
Added M3 devices to document
yes
VIN range (new chip):
2.5 V to 16 V
VOUT range (new chip):
1.2 V to 5.0 V
VOUT accuracy:
±1% for A-grade legacy
chip
±1.5% for standard-grade
legacy chip
±0.5% for new chip
only
±1% output accuracy over load, and temperature for new chip
Output current: Up to 50 mA
Low IQ (new chip): 69 μA at ILOAD = 0
mA
Low IQ (new chip): 380
μA at ILOAD = 50 mA
Shutdown current:
1 μA for legacy chip
2.25 μA for new chip
Low noise: 30 μVRMS
with 10-nF bypass capacitor
Output current limiting and thermal protection
Stable with 2.2-µF ceramic capacitors (new chip)
High PSRR: 70 dB at 1 kHz, 40 dB
at 1 MHz
Operating junction temperature:
–40°C to +125°C
Package: 5-pin SOT-23 (DBV)
Features
L
Updated the numbering format for tables, figures, and
cross-references throughout the document
yes
L
Changed entire document to align with current family
format
yes
L
Added M3 devices to document
yes
L
Updated the numbering format for tables, figures, and
cross-references throughout the document
yes
L
Changed entire document to align with current family
format
yes
L
Added M3 devices to document
yes
L
Updated the numbering format for tables, figures, and
cross-references throughout the document
yes
LUpdated the numbering format for tables, figures, and
cross-references throughout the documentyes
L
Changed entire document to align with current family
format
yes
LChanged entire document to align with current family
formatyes
L
Added M3 devices to document
yes
LAdded M3 devices to documentyes
VIN range (new chip):
2.5 V to 16 V
VOUT range (new chip):
1.2 V to 5.0 V
VOUT accuracy:
±1% for A-grade legacy
chip
±1.5% for standard-grade
legacy chip
±0.5% for new chip
only
±1% output accuracy over load, and temperature for new chip
Output current: Up to 50 mA
Low IQ (new chip): 69 μA at ILOAD = 0
mA
Low IQ (new chip): 380
μA at ILOAD = 50 mA
Shutdown current:
1 μA for legacy chip
2.25 μA for new chip
Low noise: 30 μVRMS
with 10-nF bypass capacitor
Output current limiting and thermal protection
Stable with 2.2-µF ceramic capacitors (new chip)
High PSRR: 70 dB at 1 kHz, 40 dB
at 1 MHz
Operating junction temperature:
–40°C to +125°C
Package: 5-pin SOT-23 (DBV)
VIN range (new chip):
2.5 V to 16 V
VOUT range (new chip):
1.2 V to 5.0 V
VOUT accuracy:
±1% for A-grade legacy
chip
±1.5% for standard-grade
legacy chip
±0.5% for new chip
only
±1% output accuracy over load, and temperature for new chip
Output current: Up to 50 mA
Low IQ (new chip): 69 μA at ILOAD = 0
mA
Low IQ (new chip): 380
μA at ILOAD = 50 mA
Shutdown current:
1 μA for legacy chip
2.25 μA for new chip
Low noise: 30 μVRMS
with 10-nF bypass capacitor
Output current limiting and thermal protection
Stable with 2.2-µF ceramic capacitors (new chip)
High PSRR: 70 dB at 1 kHz, 40 dB
at 1 MHz
Operating junction temperature:
–40°C to +125°C
Package: 5-pin SOT-23 (DBV)
VIN range (new chip):
2.5 V to 16 V
VOUT range (new chip):
1.2 V to 5.0 V
VOUT accuracy:
±1% for A-grade legacy
chip
±1.5% for standard-grade
legacy chip
±0.5% for new chip
only
±1% output accuracy over load, and temperature for new chip
Output current: Up to 50 mA
Low IQ (new chip): 69 μA at ILOAD = 0
mA
Low IQ (new chip): 380
μA at ILOAD = 50 mA
Shutdown current:
1 μA for legacy chip
2.25 μA for new chip
Low noise: 30 μVRMS
with 10-nF bypass capacitor
Output current limiting and thermal protection
Stable with 2.2-µF ceramic capacitors (new chip)
High PSRR: 70 dB at 1 kHz, 40 dB
at 1 MHz
Operating junction temperature:
–40°C to +125°C
Package: 5-pin SOT-23 (DBV)
VIN range (new chip):
2.5 V to 16 VINVOUT range (new chip):
1.2 V to 5.0 VOUTVOUT accuracy:
±1% for A-grade legacy
chip
±1.5% for standard-grade
legacy chip
±0.5% for new chip
only
OUT
±1% for A-grade legacy
chip
±1.5% for standard-grade
legacy chip
±0.5% for new chip
only
±1% for A-grade legacy
chip±1.5% for standard-grade
legacy chip±0.5% for new chip
only±1% output accuracy over load, and temperature for new chipOutput current: Up to 50 mALow IQ (new chip): 69 μA at ILOAD = 0
mAQLOADLow IQ (new chip): 380
μA at ILOAD = 50 mAQLOADShutdown current:
1 μA for legacy chip
2.25 μA for new chip
1 μA for legacy chip
2.25 μA for new chip
1 μA for legacy chip2.25 μA for new chipLow noise: 30 μVRMS
with 10-nF bypass capacitorRMSOutput current limiting and thermal protectionStable with 2.2-µF ceramic capacitors (new chip)High PSRR: 70 dB at 1 kHz, 40 dB
at 1 MHzOperating junction temperature:
–40°C to +125°CPackage: 5-pin SOT-23 (DBV)
Applications
Factory automation & control
Industrial transport (non-car & non-light
truck)
Grid infrastructure
Medical
Applications
Factory automation & control
Industrial transport (non-car & non-light
truck)
Grid infrastructure
Medical
Factory automation & control
Industrial transport (non-car & non-light
truck)
Grid infrastructure
Medical
Factory automation & control
Industrial transport (non-car & non-light
truck)
Grid infrastructure
Medical
Factory automation & control
Factory automation & control
Industrial transport (non-car & non-light
truck)
Industrial transport (non-car & non-light
truck)
Grid infrastructure
Grid infrastructure
Medical
Medical
Description
K
Deleted TM symbol from VIP - no longer trademarked; changed word in title from "Regulator" to "LDO"
yes
K
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section
yes
K
Changed update typical application drawing and change pin names from Vin, Vout to IN and OUT; remove last paragraph of Description beginning "Four output voltage versions..."
yes
The LP2982 is a fixed-output,
wide-input, low-noise, low-dropout voltage regulator supporting an input voltage
range from 2.5 V to 16 V (for new chip) and up to 50 mA of load current. The LP2982
supports an output range of 1.2 V to 5.0 V (for new chip).
Additionally, the LP2982 (new chip)
has a 1% output accuracy across load, and temperature that can meet the needs of
low-voltage microcontrollers (MCUs) and processors.
Low output noise of 30
µVRMS (with 10-nF bypass capacitors) and wide bandwidth PSRR
performance of greater than 70 dB at 1 kHz and 40 dB at 1 MHz help attenuate the
switching frequency of an upstream DC/DC converter and minimize post regulator
filtering.
The internal soft-start time and
current limit protection reduce inrush current during start up, thus minimizing
input capacitance. Standard protection features, such as overcurrent and
overtemperature protection, are included.
The LP2982 is available in a 5-pin
2.9-mm × 2.8-mm SOT-23 (DBV) package.
Device
Information
PART NUMBER
PACKAGE#GUID-BE15E34C-8CEC-4AB2-AE98-5E2F77F52C1B/DEVINFONOTE
BODY SIZE (NOM)#GUID-BE15E34C-8CEC-4AB2-AE98-5E2F77F52C1B/DEVINFONOTEE
LP2982
SOT-23 (5)
2.90 mm × 2.80 mm
For all available packages, see the orderable addendum at the end of the data sheet.
The package size (length × width) is a nominal value and
includes pins, where applicable.
Simplified Schematic
Dropout Voltage versus Temperature (New
Chip)
Description
K
Deleted TM symbol from VIP - no longer trademarked; changed word in title from "Regulator" to "LDO"
yes
K
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section
yes
K
Changed update typical application drawing and change pin names from Vin, Vout to IN and OUT; remove last paragraph of Description beginning "Four output voltage versions..."
yes
K
Deleted TM symbol from VIP - no longer trademarked; changed word in title from "Regulator" to "LDO"
yes
K
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section
yes
K
Changed update typical application drawing and change pin names from Vin, Vout to IN and OUT; remove last paragraph of Description beginning "Four output voltage versions..."
yes
K
Deleted TM symbol from VIP - no longer trademarked; changed word in title from "Regulator" to "LDO"
yes
KDeleted TM symbol from VIP - no longer trademarked; changed word in title from "Regulator" to "LDO" yes
K
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section
yes
KAdded Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Pin Configuration and FunctionsESD RatingsFeature DescriptionDevice Functional ModesApplication and ImplementationPower Supply RecommendationsLayoutDevice and Documentation SupportMechanical, Packaging, and Orderable Informationyes
K
Changed update typical application drawing and change pin names from Vin, Vout to IN and OUT; remove last paragraph of Description beginning "Four output voltage versions..."
yes
KChanged update typical application drawing and change pin names from Vin, Vout to IN and OUT; remove last paragraph of Description beginning "Four output voltage versions..."Descriptionyes
The LP2982 is a fixed-output,
wide-input, low-noise, low-dropout voltage regulator supporting an input voltage
range from 2.5 V to 16 V (for new chip) and up to 50 mA of load current. The LP2982
supports an output range of 1.2 V to 5.0 V (for new chip).
Additionally, the LP2982 (new chip)
has a 1% output accuracy across load, and temperature that can meet the needs of
low-voltage microcontrollers (MCUs) and processors.
Low output noise of 30
µVRMS (with 10-nF bypass capacitors) and wide bandwidth PSRR
performance of greater than 70 dB at 1 kHz and 40 dB at 1 MHz help attenuate the
switching frequency of an upstream DC/DC converter and minimize post regulator
filtering.
The internal soft-start time and
current limit protection reduce inrush current during start up, thus minimizing
input capacitance. Standard protection features, such as overcurrent and
overtemperature protection, are included.
The LP2982 is available in a 5-pin
2.9-mm × 2.8-mm SOT-23 (DBV) package.
Device
Information
PART NUMBER
PACKAGE#GUID-BE15E34C-8CEC-4AB2-AE98-5E2F77F52C1B/DEVINFONOTE
BODY SIZE (NOM)#GUID-BE15E34C-8CEC-4AB2-AE98-5E2F77F52C1B/DEVINFONOTEE
LP2982
SOT-23 (5)
2.90 mm × 2.80 mm
For all available packages, see the orderable addendum at the end of the data sheet.
The package size (length × width) is a nominal value and
includes pins, where applicable.
Simplified Schematic
Dropout Voltage versus Temperature (New
Chip)
The LP2982 is a fixed-output,
wide-input, low-noise, low-dropout voltage regulator supporting an input voltage
range from 2.5 V to 16 V (for new chip) and up to 50 mA of load current. The LP2982
supports an output range of 1.2 V to 5.0 V (for new chip).
Additionally, the LP2982 (new chip)
has a 1% output accuracy across load, and temperature that can meet the needs of
low-voltage microcontrollers (MCUs) and processors.
Low output noise of 30
µVRMS (with 10-nF bypass capacitors) and wide bandwidth PSRR
performance of greater than 70 dB at 1 kHz and 40 dB at 1 MHz help attenuate the
switching frequency of an upstream DC/DC converter and minimize post regulator
filtering.
The internal soft-start time and
current limit protection reduce inrush current during start up, thus minimizing
input capacitance. Standard protection features, such as overcurrent and
overtemperature protection, are included.
The LP2982 is available in a 5-pin
2.9-mm × 2.8-mm SOT-23 (DBV) package.
Device
Information
PART NUMBER
PACKAGE#GUID-BE15E34C-8CEC-4AB2-AE98-5E2F77F52C1B/DEVINFONOTE
BODY SIZE (NOM)#GUID-BE15E34C-8CEC-4AB2-AE98-5E2F77F52C1B/DEVINFONOTEE
LP2982
SOT-23 (5)
2.90 mm × 2.80 mm
For all available packages, see the orderable addendum at the end of the data sheet.
The package size (length × width) is a nominal value and
includes pins, where applicable.
The LP2982 is a fixed-output,
wide-input, low-noise, low-dropout voltage regulator supporting an input voltage
range from 2.5 V to 16 V (for new chip) and up to 50 mA of load current. The LP2982
supports an output range of 1.2 V to 5.0 V (for new chip).Additionally, the LP2982 (new chip)
has a 1% output accuracy across load, and temperature that can meet the needs of
low-voltage microcontrollers (MCUs) and processors.Low output noise of 30
µVRMS (with 10-nF bypass capacitors) and wide bandwidth PSRR
performance of greater than 70 dB at 1 kHz and 40 dB at 1 MHz help attenuate the
switching frequency of an upstream DC/DC converter and minimize post regulator
filtering. RMSThe internal soft-start time and
current limit protection reduce inrush current during start up, thus minimizing
input capacitance. Standard protection features, such as overcurrent and
overtemperature protection, are included.The LP2982 is available in a 5-pin
2.9-mm × 2.8-mm SOT-23 (DBV) package.
Device
Information
PART NUMBER
PACKAGE#GUID-BE15E34C-8CEC-4AB2-AE98-5E2F77F52C1B/DEVINFONOTE
BODY SIZE (NOM)#GUID-BE15E34C-8CEC-4AB2-AE98-5E2F77F52C1B/DEVINFONOTEE
LP2982
SOT-23 (5)
2.90 mm × 2.80 mm
Device
Information
PART NUMBER
PACKAGE#GUID-BE15E34C-8CEC-4AB2-AE98-5E2F77F52C1B/DEVINFONOTE
BODY SIZE (NOM)#GUID-BE15E34C-8CEC-4AB2-AE98-5E2F77F52C1B/DEVINFONOTEE
LP2982
SOT-23 (5)
2.90 mm × 2.80 mm
PART NUMBER
PACKAGE#GUID-BE15E34C-8CEC-4AB2-AE98-5E2F77F52C1B/DEVINFONOTE
BODY SIZE (NOM)#GUID-BE15E34C-8CEC-4AB2-AE98-5E2F77F52C1B/DEVINFONOTEE
PART NUMBER
PACKAGE#GUID-BE15E34C-8CEC-4AB2-AE98-5E2F77F52C1B/DEVINFONOTE
BODY SIZE (NOM)#GUID-BE15E34C-8CEC-4AB2-AE98-5E2F77F52C1B/DEVINFONOTEE
PART NUMBERPACKAGE#GUID-BE15E34C-8CEC-4AB2-AE98-5E2F77F52C1B/DEVINFONOTE
#GUID-BE15E34C-8CEC-4AB2-AE98-5E2F77F52C1B/DEVINFONOTEBODY SIZE (NOM)#GUID-BE15E34C-8CEC-4AB2-AE98-5E2F77F52C1B/DEVINFONOTEE
#GUID-BE15E34C-8CEC-4AB2-AE98-5E2F77F52C1B/DEVINFONOTEE
LP2982
SOT-23 (5)
2.90 mm × 2.80 mm
LP2982
SOT-23 (5)
2.90 mm × 2.80 mm
LP2982SOT-23 (5)2.90 mm × 2.80 mm
For all available packages, see the orderable addendum at the end of the data sheet.
The package size (length × width) is a nominal value and
includes pins, where applicable.
For all available packages, see the orderable addendum at the end of the data sheet.The package size (length × width) is a nominal value and
includes pins, where applicable.
Simplified Schematic
Dropout Voltage versus Temperature (New
Chip)
Simplified Schematic
Dropout Voltage versus Temperature (New
Chip)
Simplified Schematic
Simplified Schematic
Dropout Voltage versus Temperature (New
Chip)
Dropout Voltage versus Temperature (New
Chip)
Table of Contents
yes
Table of Contents
yes
yes
yes
Pin Configuration and Functions
DBV Package,
5-Pin SOT-23
(Top View)
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
BYPASS
4
I/O
BYPASS pin to
achieve low noise performance. Connecting an external capacitor
between BYPASS pin and ground reduces reference voltage noise. See
the
section for more information.
GND
2
—
Ground
ON/OFF
3
I
Enable pin for
the LDO. Driving the ON/OFF pin high enables
the device. Driving this pin low disables the device. High and low
thresholds are listed in the
table. Tie this pin to VIN if unused.
VIN
1
I
Input supply
pin. Use a capacitor with a value of 1 µF or larger from this pin to
ground. See the
section for more information.
VOUT
5
O
Output of the
regulator. Use a capacitor with a value of 2.2 µF or larger from
this pin to ground. See the
section for more information.
Pin Configuration and Functions
DBV Package,
5-Pin SOT-23
(Top View)
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
BYPASS
4
I/O
BYPASS pin to
achieve low noise performance. Connecting an external capacitor
between BYPASS pin and ground reduces reference voltage noise. See
the
section for more information.
GND
2
—
Ground
ON/OFF
3
I
Enable pin for
the LDO. Driving the ON/OFF pin high enables
the device. Driving this pin low disables the device. High and low
thresholds are listed in the
table. Tie this pin to VIN if unused.
VIN
1
I
Input supply
pin. Use a capacitor with a value of 1 µF or larger from this pin to
ground. See the
section for more information.
VOUT
5
O
Output of the
regulator. Use a capacitor with a value of 2.2 µF or larger from
this pin to ground. See the
section for more information.
DBV Package,
5-Pin SOT-23
(Top View)
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
BYPASS
4
I/O
BYPASS pin to
achieve low noise performance. Connecting an external capacitor
between BYPASS pin and ground reduces reference voltage noise. See
the
section for more information.
GND
2
—
Ground
ON/OFF
3
I
Enable pin for
the LDO. Driving the ON/OFF pin high enables
the device. Driving this pin low disables the device. High and low
thresholds are listed in the
table. Tie this pin to VIN if unused.
VIN
1
I
Input supply
pin. Use a capacitor with a value of 1 µF or larger from this pin to
ground. See the
section for more information.
VOUT
5
O
Output of the
regulator. Use a capacitor with a value of 2.2 µF or larger from
this pin to ground. See the
section for more information.
DBV Package,
5-Pin SOT-23
(Top View)
DBV Package,
5-Pin SOT-23
(Top View)
DBV Package,5-Pin SOT-23(Top View)
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
BYPASS
4
I/O
BYPASS pin to
achieve low noise performance. Connecting an external capacitor
between BYPASS pin and ground reduces reference voltage noise. See
the
section for more information.
GND
2
—
Ground
ON/OFF
3
I
Enable pin for
the LDO. Driving the ON/OFF pin high enables
the device. Driving this pin low disables the device. High and low
thresholds are listed in the
table. Tie this pin to VIN if unused.
VIN
1
I
Input supply
pin. Use a capacitor with a value of 1 µF or larger from this pin to
ground. See the
section for more information.
VOUT
5
O
Output of the
regulator. Use a capacitor with a value of 2.2 µF or larger from
this pin to ground. See the
section for more information.
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
BYPASS
4
I/O
BYPASS pin to
achieve low noise performance. Connecting an external capacitor
between BYPASS pin and ground reduces reference voltage noise. See
the
section for more information.
GND
2
—
Ground
ON/OFF
3
I
Enable pin for
the LDO. Driving the ON/OFF pin high enables
the device. Driving this pin low disables the device. High and low
thresholds are listed in the
table. Tie this pin to VIN if unused.
VIN
1
I
Input supply
pin. Use a capacitor with a value of 1 µF or larger from this pin to
ground. See the
section for more information.
VOUT
5
O
Output of the
regulator. Use a capacitor with a value of 2.2 µF or larger from
this pin to ground. See the
section for more information.
PIN
TYPE
DESCRIPTION
NAME
NO.
PIN
TYPE
DESCRIPTION
PINTYPEDESCRIPTION
NAME
NO.
NAMENO.
BYPASS
4
I/O
BYPASS pin to
achieve low noise performance. Connecting an external capacitor
between BYPASS pin and ground reduces reference voltage noise. See
the
section for more information.
GND
2
—
Ground
ON/OFF
3
I
Enable pin for
the LDO. Driving the ON/OFF pin high enables
the device. Driving this pin low disables the device. High and low
thresholds are listed in the
table. Tie this pin to VIN if unused.
VIN
1
I
Input supply
pin. Use a capacitor with a value of 1 µF or larger from this pin to
ground. See the
section for more information.
VOUT
5
O
Output of the
regulator. Use a capacitor with a value of 2.2 µF or larger from
this pin to ground. See the
section for more information.
BYPASS
4
I/O
BYPASS pin to
achieve low noise performance. Connecting an external capacitor
between BYPASS pin and ground reduces reference voltage noise. See
the
section for more information.
BYPASS4I/OBYPASS pin to
achieve low noise performance. Connecting an external capacitor
between BYPASS pin and ground reduces reference voltage noise. See
the
section for more information.
GND
2
—
Ground
GND2—Ground
ON/OFF
3
I
Enable pin for
the LDO. Driving the ON/OFF pin high enables
the device. Driving this pin low disables the device. High and low
thresholds are listed in the
table. Tie this pin to VIN if unused.
ON/OFF
OFF3IEnable pin for
the LDO. Driving the ON/OFF pin high enables
the device. Driving this pin low disables the device. High and low
thresholds are listed in the
table. Tie this pin to VIN if unused.OFF
IN
VIN
1
I
Input supply
pin. Use a capacitor with a value of 1 µF or larger from this pin to
ground. See the
section for more information.
VIN
IN1IInput supply
pin. Use a capacitor with a value of 1 µF or larger from this pin to
ground. See the
section for more information.
VOUT
5
O
Output of the
regulator. Use a capacitor with a value of 2.2 µF or larger from
this pin to ground. See the
section for more information.
VOUT
OUT5OOutput of the
regulator. Use a capacitor with a value of 2.2 µF or larger from
this pin to ground. See the
section for more information.
Specifications
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377649/A_3C032305_5BB2_4444_9252_7F358B2CF63C_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER1_SF1
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377649/A_3C032305_5BB2_4444_9252_7F358B2CF63C_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER2_SF1
MIN
MAX
UNIT
VIN
Continuous input voltage range (for legacy chip)
–0.3
16
V
Continuous input voltage range (for new chip)
–0.3
18
VOUT
Output voltage range (for legacy chip)
–0.3
9
Output voltage range (for new chip)
–0.3
VIN + 0.3 or 9 (whichever is smaller)
VON/OFF
ON/OFF pin voltage range (for legacy chip)
–0.3
16
ON/OFF pin voltage range (for new chip)
–0.3
18
VIN – VOUT
Input-output voltage (for legacy chip)
–0.3
16
Input-output voltage (for new chip)
–0.3
18
Current
Maximum output current
Internally limited
mA
Temperature
Operating junction, TJ
–55
150
°C
Storage, Tstg
–65
150
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
All voltages with respect to GND.
ESD Ratings
VALUE (Legacy Chip)
VALUE (New Chip)
UNIT
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 1,2 and 5) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1
±2000
±3000
V
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 3 and 4) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1
±1000
Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/CDM_COMM_SF2_SF1
N/A
±1000
JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.
Recommended Operating Conditions
MIN
NOM
MAX
UNIT
VIN
Supply input voltage (for legacy chip)
2.1
16
V
Supply input voltage (for new chip)
2.5
16
VIN – VOUT
Input-output differential (for legacy chip)
0.7
11
Input-output differential (for new chip)
0
16
VOUT
Output voltage (for new chip)
1.2
5
VON/OFF
Enable voltage (for legacy chip)
0
VIN
Enable voltage (for new chip)
0
16
IOUT
Output current
0
50
mA
CIN
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1
Input capacitor
1
µF
COUT
Output capacitor (for legacy chip)
2.2
4.7
Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1
1
2.2
200
TJ
Operating junction temperature
–40
125
°C
All capacitor values are assumed to derate to 50% of the nominal capacitor value. Maintain an effective output capacitance of 1 µF minimum for stability.
Thermal Information
THERMAL METRIC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378365/APPNOTE_LP2985_SF1_SF1_SF1
Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378365/THERMALFOOTER_SF1_SF1_SF1_SF1
New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378365/THERMALFOOTER_SF1_SF1_SF1_SF1
UNIT
DBV (SOT23-5)
DBV (SOT23-5)
5 PINS
5 PINS
RθJA
Junction-to-ambient thermal resistance
175.7
178.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
121.8
77.9
°C/W
RθJB
Junction-to-board thermal resistance
29.5
47.2
°C/W
ψJT
Junction-to-top characterization parameter
16.1
15.9
°C/W
ψJB
Junction-to-board characterization parameter
29.0
46.9
°C/W
For more information about traditional and new thermal metrics, see the
Semiconductor and IC Package Thermal Metrics
application note.
Thermal performance results are based on the JEDEC standard of 2s2p PCB configuration. These thermal metric parameters can be further improved by 35-55% based on thermally optimized PCB layout designs. See the analysis of the
Impact of board layout on LDO thermal performance
application report.
Electrical Characteristics
specified at TJ = 25 °C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0 µF, and COUT = 2.2 µF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
∆VOUT
Output voltage tolerance
IL = 1 mA
Legacy chip (standard grade)
–1.5
1.5
%
Legacy chip (A grade)
–1.0
1.0
New chip
–0.5
0.5
1 mA < IL < 50 mA
Legacy chip (standard grade)
–2
2
Legacy chip (A grade)
–1.5
1.5
New chip
–0.5
0.5
1 mA < IL < 50 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip (standard grade)
–3.5
3.5
Legacy chip (A grade)
–2
2
New chip
–1
1
ΔVOUT(ΔVIN)
Line regulation
VO(NOM) + 1 V < VIN < 16 V
Legacy chip
0.007
0.014
%/V
New chip
0.002
0.014
VO(NOM) + 1 V < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
0.007
0.032
New chip
0.002
0.032
ΔVOUT(ΔILOAD)
Load regulation
1 mA < IL < 50 mA, –40°C ≤ TJ ≤ 125°C, VIN = VO(NOM)+0.5 V
New chip
0.1
0.5
%/A
VDO
Dropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378397/A_5B260BA6_7C10_45AC_9F2D_6AB30CB61FCE_LP298X_LP2981_300MM_AA_ELECTRICAL_CHARACTERISTICS_ELECTRICAL_CHAR_LP2981_FOOTER1
IOUT = 0 mA
Legacy chip
1
3
mV
New chip
1
2.75
IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
5
New chip
3
IOUT = 1 mA
Legacy chip
7
10
New chip
11.5
14
IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
15
New chip
17
IOUT = 10 mA
Legacy chip
40
60
New chip
98
115
IOUT = 10 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
90
New chip
148
IOUT = 50 mA
Legacy chip
120
150
New chip
120
145
IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
225
New chip
184
IOUT = 80 mA
Legacy chip
180
225
New chip
150
165
IOUT = 80 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
325
New chip
204
IGND
GND pin current
IOUT = 0 mA
Legacy chip
65
95
µA
New chip
69
95
IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
125
New chip
123
IOUT = 1 mA
Legacy chip
80
110
New chip
78
110
IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
170
New chip
140
IOUT = 10 mA
Legacy chip
140
220
µA
New chip
175
210
IOUT = 10 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
460
New chip
250
IOUT = 50 mA
Legacy chip
375
600
µA
New chip
380
440
IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
1200
µA
New chip
650
µA
IOUT = 80 mA
Legacy chip
525
750
µA
New chip
575
720
µA
IOUT = 80 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
1400
µA
900
µA
VON/OFF < 0.3 V, VIN = 16 V
Legacy chip
0.01
0.8
µA
New chip
1.25
1.75
µA
VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
0.1
2
µA
New chip
1.12
2.75
µA
VUVLO+
Rising bias supply UVLO
VIN rising, –40°C ≤ TJ ≤ 125°C
New chip
2.2
2.4
V
VUVLO-
Falling bias supply UVLO
VIN falling, –40°C ≤ TJ ≤ 125°C
1.9
V
VUVLO(HYST)
UVLO hysteresis
–40°C ≤ TJ ≤ 125°C
0.130
V
IO(MAX)
Short Output Current
RL = 0 Ω (steady state)
Legacy chip
150
mA
New chip
150
mA
IO(PK)
Peak Output Current
VOUT ≥ VO(NOM) –5% (steady state)
Legacy chip
100
150
mA
New chip
100
150
mA
VON/OFF
ON/OFF input voltage
Low = Output OFF
Legacy chip
0.55
V
New chip
0.72
Low = Output OFF, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
0.15
New chip
0.15
High = Output ON
Legacy chip
1.4
New chip
0.85
High = Output ON, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
1.6
New chip
1.6
ION/OFF
ON/OFF input current
VON/OFF = 0 V
Legacy chip
0.01
µA
New chip
0.42
VON/OFF = 0 V, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
–2
µA
New chip
–0.9
µA
VON/OFF = 5 V
Legacy chip
5
µA
New chip
0.011
µA
VON/OFF = 5 V, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
15
µA
New chip
2.20
µA
ΔVO/ΔVIN
Ripple rejection
f = 1 kHz, CBYPASS = 10 nF, COUT = 10 µF
Legacy chip
45
dB
New chip
78
f = 100 kHz, CBYPASS = 10 nF , ILOAD = 50 mA
45
dB
Vn
Output noise voltage
Bandwidth = 300 Hz to 50 kHz, CNR/SS = 10 nF, COUT = 2.2 µF, VOUT = 1.8 V, ILOAD = 150 mA
Legacy chip
30
µVRMS
New chip
30
Bandwidth = 10 Hz to 100 kHz, CNR/SS = 10 nF, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA
50
Tsd+
Thermal shutdown threshold
Shutdown, temperature increasing
New chip
170
°C
Tsd-
Reset, temperature decreasing
150
Dropout voltage (VDO) is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured with a 1 V differential. VDO is measured with VIN = VOUT(nom) – 100 mV for fixed output devices.
Typical Characteristics
Unless otherwise specified: TA = 25°C, VIN = VO(NOM) + 1 V, COUT = 4.7 μF, CIN = 1 μF, all voltage options, ON/
OFF pin tied to VIN.
Output Voltage
versus Temperature (Legacy Chip)
Output Voltage
versus Temperature (Legacy Chip)
Output Voltage
versus Temperature (Legacy Chip)
Output Voltage
versus Temperature (New Chip)
VIN = 4.3 V, VOUT = 3.3 V
Output Voltage
versus VIN (Legacy Chip)
VOUT = 5.0
V
Output Voltage
versus VIN (Legacy Chip)
VOUT = 3.3
V
Output Voltage
versus VIN (Legacy Chip)
VOUT = 3.0
V
Output Voltage versus VIN
(New Chip)
VOUT = 3.3
V
Dropout Voltage
versus Temperature (Legacy Chip)
Dropout Voltage versus Temperature
(New Chip)
Dropout Voltage
versus Load Current (Legacy Chip)
Dropout Voltage versus Load Current
(New Chip)
Ground Pin
Current versus Temperature (Legacy Chip)
Ground Pin
Current versus Temperature (New Chip)
Ground Pin
Current versus Load Current (Legacy Chip)
Ground Pin Current versus Load
Current (New Chip)
Input Current
versus VIN (Legacy Chip)
VOUT = 5
V
Input Current
versus VIN (Legacy Chip)
VOUT = 5
V
Input Current versus Input Voltage
(New Chip)
VOUT = 3.3 V
Line Transient
Response (Legacy chip)
Line Transient
Response (Legacy chip)
Line Transient Response (New
Chip)
VOUT = 3.3 V, ΔVIN = 1 V, IOUT = 50 mA,
dV/dt = 1 V/μs
Load Transient
Response (Legacy chip)
Load Transient
Response (Legacy chip)
Load Transient
Response (Legacy chip)
Load Transient
Response (Legacy chip)
Load Transient Response (New
Chip)
dI/dt = 1 A/μs
Short-Circuit
Current versus Time (Legacy chip)
VIN = 6
V
Short-Circuit
Current versus Time (Legacy chip)
VIN = 16
V
Short-Circuit Current versus Time
(New Chip)
VIN = 6 V
Short-Circuit Current versus Time
(New Chip)
Instantaneous
Short-Circuit Current versus Temperature (Legacy chip)
Short-Circuit Current versus
Temperature (New Chip)
Instantaneous
Short Circuit Current versus Output Voltage (Legacy chip)
Output
Impedance versus Frequency (Legacy chip)
Output
Impedance versus Frequency (Legacy chip)
ON/
OFF Pin Current versus VON/OFF (Legacy chip)
ON/OFF Pin Current versus
VON/OFF
(New Chip)
VIN = 16
V
ON/OFF Pin Current versus
VON/OFF
(New Chip)
VIN = 4.3
V
ON/
OFF Threshold versus Temperature (Legacy chip)
ON/
OFF Threshold versus Temperature (New chip)
Input-to-Output
Leakage versus Temperature (Legacy chip)
Output Reverse
Leakage versus Temperature (Legacy chip)
Output Reverse
Leakage versus Temperature (New chip)
Output Noise
Density (Legacy chip)
Output Noise
Density (Legacy chip)
Output Noise
Density (Legacy chip)
Output Noise Density versus
Frequency (New Chip)
VIN = 4.3V, VOUT = 3.3V, COUT = 2.2μF
and ILOAD = 50 mA
Output Noise Density versus
Frequency for New Chip
VIN = 4.3V, VOUT = 3.3V, COUT = 2.2μF
and ILOAD = 1 mA
Ripple
Rejection (Legacy chip)
Ripple Rejection versus IOUT
(New Chip)
VOUT = 3.3 V, Cbyp = 0 nF
Ripple Rejection versus
IOUT (New Chip)
VOUT = 3.3 V, Cbyp = 10 nF
Turnon Waveform
(Legacy chip)
Turnon Waveform
(Legacy chip)
Turnon Waveform
(Legacy chip)
Turnon Waveform (New chip)
Cbyp = 0 nF
Turnon Waveform (New chip)
Cbyp = 0.1 nF
Turnon Waveform (New chip)
Cbyp = 1 nF
Specifications
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377649/A_3C032305_5BB2_4444_9252_7F358B2CF63C_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER1_SF1
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377649/A_3C032305_5BB2_4444_9252_7F358B2CF63C_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER2_SF1
MIN
MAX
UNIT
VIN
Continuous input voltage range (for legacy chip)
–0.3
16
V
Continuous input voltage range (for new chip)
–0.3
18
VOUT
Output voltage range (for legacy chip)
–0.3
9
Output voltage range (for new chip)
–0.3
VIN + 0.3 or 9 (whichever is smaller)
VON/OFF
ON/OFF pin voltage range (for legacy chip)
–0.3
16
ON/OFF pin voltage range (for new chip)
–0.3
18
VIN – VOUT
Input-output voltage (for legacy chip)
–0.3
16
Input-output voltage (for new chip)
–0.3
18
Current
Maximum output current
Internally limited
mA
Temperature
Operating junction, TJ
–55
150
°C
Storage, Tstg
–65
150
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
All voltages with respect to GND.
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377649/A_3C032305_5BB2_4444_9252_7F358B2CF63C_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER1_SF1
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377649/A_3C032305_5BB2_4444_9252_7F358B2CF63C_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER2_SF1
MIN
MAX
UNIT
VIN
Continuous input voltage range (for legacy chip)
–0.3
16
V
Continuous input voltage range (for new chip)
–0.3
18
VOUT
Output voltage range (for legacy chip)
–0.3
9
Output voltage range (for new chip)
–0.3
VIN + 0.3 or 9 (whichever is smaller)
VON/OFF
ON/OFF pin voltage range (for legacy chip)
–0.3
16
ON/OFF pin voltage range (for new chip)
–0.3
18
VIN – VOUT
Input-output voltage (for legacy chip)
–0.3
16
Input-output voltage (for new chip)
–0.3
18
Current
Maximum output current
Internally limited
mA
Temperature
Operating junction, TJ
–55
150
°C
Storage, Tstg
–65
150
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
All voltages with respect to GND.
over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377649/A_3C032305_5BB2_4444_9252_7F358B2CF63C_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER1_SF1
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377649/A_3C032305_5BB2_4444_9252_7F358B2CF63C_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER2_SF1
MIN
MAX
UNIT
VIN
Continuous input voltage range (for legacy chip)
–0.3
16
V
Continuous input voltage range (for new chip)
–0.3
18
VOUT
Output voltage range (for legacy chip)
–0.3
9
Output voltage range (for new chip)
–0.3
VIN + 0.3 or 9 (whichever is smaller)
VON/OFF
ON/OFF pin voltage range (for legacy chip)
–0.3
16
ON/OFF pin voltage range (for new chip)
–0.3
18
VIN – VOUT
Input-output voltage (for legacy chip)
–0.3
16
Input-output voltage (for new chip)
–0.3
18
Current
Maximum output current
Internally limited
mA
Temperature
Operating junction, TJ
–55
150
°C
Storage, Tstg
–65
150
over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377649/A_3C032305_5BB2_4444_9252_7F358B2CF63C_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER1_SF1
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377649/A_3C032305_5BB2_4444_9252_7F358B2CF63C_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER2_SF1
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377649/A_3C032305_5BB2_4444_9252_7F358B2CF63C_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER1_SF1#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000377649/A_3C032305_5BB2_4444_9252_7F358B2CF63C_LP298X_LP2992_300MM_AA_ABSOLUTE_MAXIMUM_RATINGS_ABSOLUTE_MAXIMUM_RATINGS_1_FOOTER2_SF1
MIN
MAX
UNIT
VIN
Continuous input voltage range (for legacy chip)
–0.3
16
V
Continuous input voltage range (for new chip)
–0.3
18
VOUT
Output voltage range (for legacy chip)
–0.3
9
Output voltage range (for new chip)
–0.3
VIN + 0.3 or 9 (whichever is smaller)
VON/OFF
ON/OFF pin voltage range (for legacy chip)
–0.3
16
ON/OFF pin voltage range (for new chip)
–0.3
18
VIN – VOUT
Input-output voltage (for legacy chip)
–0.3
16
Input-output voltage (for new chip)
–0.3
18
Current
Maximum output current
Internally limited
mA
Temperature
Operating junction, TJ
–55
150
°C
Storage, Tstg
–65
150
MIN
MAX
UNIT
MIN
MAX
UNIT
MINMAXUNIT
VIN
Continuous input voltage range (for legacy chip)
–0.3
16
V
Continuous input voltage range (for new chip)
–0.3
18
VOUT
Output voltage range (for legacy chip)
–0.3
9
Output voltage range (for new chip)
–0.3
VIN + 0.3 or 9 (whichever is smaller)
VON/OFF
ON/OFF pin voltage range (for legacy chip)
–0.3
16
ON/OFF pin voltage range (for new chip)
–0.3
18
VIN – VOUT
Input-output voltage (for legacy chip)
–0.3
16
Input-output voltage (for new chip)
–0.3
18
Current
Maximum output current
Internally limited
mA
Temperature
Operating junction, TJ
–55
150
°C
Storage, Tstg
–65
150
VIN
Continuous input voltage range (for legacy chip)
–0.3
16
V
VIN
IN Continuous input voltage range (for legacy chip)–0.316V
Continuous input voltage range (for new chip)
–0.3
18
Continuous input voltage range (for new chip) –0.318
VOUT
Output voltage range (for legacy chip)
–0.3
9
VOUT
OUTOutput voltage range (for legacy chip)–0.39
Output voltage range (for new chip)
–0.3
VIN + 0.3 or 9 (whichever is smaller)
Output voltage range (for new chip) –0.3VIN + 0.3 or 9 (whichever is smaller)IN
VON/OFF
ON/OFF pin voltage range (for legacy chip)
–0.3
16
VON/OFF
ON/OFF
OFFON/OFF pin voltage range (for legacy chip)OFF–0.316
ON/OFF pin voltage range (for new chip)
–0.3
18
ON/OFF pin voltage range (for new chip)OFF–0.318
VIN – VOUT
Input-output voltage (for legacy chip)
–0.3
16
VIN – VOUT
INOUTInput-output voltage (for legacy chip)–0.316
Input-output voltage (for new chip)
–0.3
18
Input-output voltage (for new chip)–0.318
Current
Maximum output current
Internally limited
mA
CurrentMaximum output currentInternally limitedmA
Temperature
Operating junction, TJ
–55
150
°C
TemperatureOperating junction, TJ
J–55150°C
Storage, Tstg
–65
150
Storage, Tstg
stg–65150
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
All voltages with respect to GND.
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.Absolute Maximum RatingsAbsolute Maximum RatingsRecommended Operating ConditionsRecommended Operating ConditionsAbsolute Maximum RatingsAll voltages with respect to GND.
ESD Ratings
VALUE (Legacy Chip)
VALUE (New Chip)
UNIT
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 1,2 and 5) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1
±2000
±3000
V
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 3 and 4) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1
±1000
Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/CDM_COMM_SF2_SF1
N/A
±1000
JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.
ESD Ratings
VALUE (Legacy Chip)
VALUE (New Chip)
UNIT
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 1,2 and 5) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1
±2000
±3000
V
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 3 and 4) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1
±1000
Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/CDM_COMM_SF2_SF1
N/A
±1000
JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.
VALUE (Legacy Chip)
VALUE (New Chip)
UNIT
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 1,2 and 5) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1
±2000
±3000
V
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 3 and 4) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1
±1000
Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/CDM_COMM_SF2_SF1
N/A
±1000
VALUE (Legacy Chip)
VALUE (New Chip)
UNIT
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 1,2 and 5) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1
±2000
±3000
V
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 3 and 4) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1
±1000
Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/CDM_COMM_SF2_SF1
N/A
±1000
VALUE (Legacy Chip)
VALUE (New Chip)
UNIT
VALUE (Legacy Chip)
VALUE (New Chip)
UNIT
VALUE (Legacy Chip)VALUE (New Chip)UNIT
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 1,2 and 5) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1
±2000
±3000
V
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 3 and 4) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1
±1000
Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/CDM_COMM_SF2_SF1
N/A
±1000
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 1,2 and 5) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1
±2000
±3000
V
V(ESD)
(ESD)Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 1,2 and 5) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1±2000±3000V
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 3 and 4) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1
±1000
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Pin 3 and 4) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/HBM_COMM_SF2_SF1±1000
Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/CDM_COMM_SF2_SF1
N/A
±1000
Charged device model (CDM), per JEDEC specification JESD22-C101#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/CDM_COMM_SF2_SF1
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378363/CDM_COMM_SF2_SF1N/A±1000
JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process.JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.
Recommended Operating Conditions
MIN
NOM
MAX
UNIT
VIN
Supply input voltage (for legacy chip)
2.1
16
V
Supply input voltage (for new chip)
2.5
16
VIN – VOUT
Input-output differential (for legacy chip)
0.7
11
Input-output differential (for new chip)
0
16
VOUT
Output voltage (for new chip)
1.2
5
VON/OFF
Enable voltage (for legacy chip)
0
VIN
Enable voltage (for new chip)
0
16
IOUT
Output current
0
50
mA
CIN
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1
Input capacitor
1
µF
COUT
Output capacitor (for legacy chip)
2.2
4.7
Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1
1
2.2
200
TJ
Operating junction temperature
–40
125
°C
All capacitor values are assumed to derate to 50% of the nominal capacitor value. Maintain an effective output capacitance of 1 µF minimum for stability.
Recommended Operating Conditions
MIN
NOM
MAX
UNIT
VIN
Supply input voltage (for legacy chip)
2.1
16
V
Supply input voltage (for new chip)
2.5
16
VIN – VOUT
Input-output differential (for legacy chip)
0.7
11
Input-output differential (for new chip)
0
16
VOUT
Output voltage (for new chip)
1.2
5
VON/OFF
Enable voltage (for legacy chip)
0
VIN
Enable voltage (for new chip)
0
16
IOUT
Output current
0
50
mA
CIN
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1
Input capacitor
1
µF
COUT
Output capacitor (for legacy chip)
2.2
4.7
Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1
1
2.2
200
TJ
Operating junction temperature
–40
125
°C
All capacitor values are assumed to derate to 50% of the nominal capacitor value. Maintain an effective output capacitance of 1 µF minimum for stability.
MIN
NOM
MAX
UNIT
VIN
Supply input voltage (for legacy chip)
2.1
16
V
Supply input voltage (for new chip)
2.5
16
VIN – VOUT
Input-output differential (for legacy chip)
0.7
11
Input-output differential (for new chip)
0
16
VOUT
Output voltage (for new chip)
1.2
5
VON/OFF
Enable voltage (for legacy chip)
0
VIN
Enable voltage (for new chip)
0
16
IOUT
Output current
0
50
mA
CIN
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1
Input capacitor
1
µF
COUT
Output capacitor (for legacy chip)
2.2
4.7
Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1
1
2.2
200
TJ
Operating junction temperature
–40
125
°C
MIN
NOM
MAX
UNIT
VIN
Supply input voltage (for legacy chip)
2.1
16
V
Supply input voltage (for new chip)
2.5
16
VIN – VOUT
Input-output differential (for legacy chip)
0.7
11
Input-output differential (for new chip)
0
16
VOUT
Output voltage (for new chip)
1.2
5
VON/OFF
Enable voltage (for legacy chip)
0
VIN
Enable voltage (for new chip)
0
16
IOUT
Output current
0
50
mA
CIN
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1
Input capacitor
1
µF
COUT
Output capacitor (for legacy chip)
2.2
4.7
Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1
1
2.2
200
TJ
Operating junction temperature
–40
125
°C
MIN
NOM
MAX
UNIT
MIN
NOM
MAX
UNIT
MINNOMMAXUNIT
VIN
Supply input voltage (for legacy chip)
2.1
16
V
Supply input voltage (for new chip)
2.5
16
VIN – VOUT
Input-output differential (for legacy chip)
0.7
11
Input-output differential (for new chip)
0
16
VOUT
Output voltage (for new chip)
1.2
5
VON/OFF
Enable voltage (for legacy chip)
0
VIN
Enable voltage (for new chip)
0
16
IOUT
Output current
0
50
mA
CIN
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1
Input capacitor
1
µF
COUT
Output capacitor (for legacy chip)
2.2
4.7
Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1
1
2.2
200
TJ
Operating junction temperature
–40
125
°C
VIN
Supply input voltage (for legacy chip)
2.1
16
V
VIN
INSupply input voltage (for legacy chip)2.116V
Supply input voltage (for new chip)
2.5
16
Supply input voltage (for new chip)2.516
VIN – VOUT
Input-output differential (for legacy chip)
0.7
11
VIN – VOUT
INOUTInput-output differential (for legacy chip)0.711
Input-output differential (for new chip)
0
16
Input-output differential (for new chip)016
VOUT
Output voltage (for new chip)
1.2
5
VOUT
OUTOutput voltage (for new chip)1.25
VON/OFF
Enable voltage (for legacy chip)
0
VIN
VON/OFF
ON/OFF
OFFEnable voltage (for legacy chip)0VIN
IN
Enable voltage (for new chip)
0
16
Enable voltage (for new chip)016
IOUT
Output current
0
50
mA
IOUT
OUTOutput current050mA
CIN
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1
Input capacitor
1
µF
CIN
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1
IN#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1Input capacitor1µF
COUT
Output capacitor (for legacy chip)
2.2
4.7
COUT
OUTOutput capacitor (for legacy chip) 2.24.7
Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1
1
2.2
200
Output capacitance (for new chip) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF1
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378364/A_1A02712A_5439_4519_B668_3AF373CCFC83_LP298X_LP2992_300MM_AA_RECOMMENDED_OPERATING_CONDITIONS_RECOMMENDED_OPERATING_CONDI_1_FOOTER1_SF1_SF112.2200
TJ
Operating junction temperature
–40
125
°C
TJ
JOperating junction temperature–40125°C
All capacitor values are assumed to derate to 50% of the nominal capacitor value. Maintain an effective output capacitance of 1 µF minimum for stability.
All capacitor values are assumed to derate to 50% of the nominal capacitor value. Maintain an effective output capacitance of 1 µF minimum for stability.
Thermal Information
THERMAL METRIC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378365/APPNOTE_LP2985_SF1_SF1_SF1
Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378365/THERMALFOOTER_SF1_SF1_SF1_SF1
New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378365/THERMALFOOTER_SF1_SF1_SF1_SF1
UNIT
DBV (SOT23-5)
DBV (SOT23-5)
5 PINS
5 PINS
RθJA
Junction-to-ambient thermal resistance
175.7
178.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
121.8
77.9
°C/W
RθJB
Junction-to-board thermal resistance
29.5
47.2
°C/W
ψJT
Junction-to-top characterization parameter
16.1
15.9
°C/W
ψJB
Junction-to-board characterization parameter
29.0
46.9
°C/W
For more information about traditional and new thermal metrics, see the
Semiconductor and IC Package Thermal Metrics
application note.
Thermal performance results are based on the JEDEC standard of 2s2p PCB configuration. These thermal metric parameters can be further improved by 35-55% based on thermally optimized PCB layout designs. See the analysis of the
Impact of board layout on LDO thermal performance
application report.
Thermal Information
THERMAL METRIC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378365/APPNOTE_LP2985_SF1_SF1_SF1
Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378365/THERMALFOOTER_SF1_SF1_SF1_SF1
New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378365/THERMALFOOTER_SF1_SF1_SF1_SF1
UNIT
DBV (SOT23-5)
DBV (SOT23-5)
5 PINS
5 PINS
RθJA
Junction-to-ambient thermal resistance
175.7
178.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
121.8
77.9
°C/W
RθJB
Junction-to-board thermal resistance
29.5
47.2
°C/W
ψJT
Junction-to-top characterization parameter
16.1
15.9
°C/W
ψJB
Junction-to-board characterization parameter
29.0
46.9
°C/W
For more information about traditional and new thermal metrics, see the
Semiconductor and IC Package Thermal Metrics
application note.
Thermal performance results are based on the JEDEC standard of 2s2p PCB configuration. These thermal metric parameters can be further improved by 35-55% based on thermally optimized PCB layout designs. See the analysis of the
Impact of board layout on LDO thermal performance
application report.
THERMAL METRIC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378365/APPNOTE_LP2985_SF1_SF1_SF1
Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378365/THERMALFOOTER_SF1_SF1_SF1_SF1
New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378365/THERMALFOOTER_SF1_SF1_SF1_SF1
UNIT
DBV (SOT23-5)
DBV (SOT23-5)
5 PINS
5 PINS
RθJA
Junction-to-ambient thermal resistance
175.7
178.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
121.8
77.9
°C/W
RθJB
Junction-to-board thermal resistance
29.5
47.2
°C/W
ψJT
Junction-to-top characterization parameter
16.1
15.9
°C/W
ψJB
Junction-to-board characterization parameter
29.0
46.9
°C/W
THERMAL METRIC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378365/APPNOTE_LP2985_SF1_SF1_SF1
Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378365/THERMALFOOTER_SF1_SF1_SF1_SF1
New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378365/THERMALFOOTER_SF1_SF1_SF1_SF1
UNIT
DBV (SOT23-5)
DBV (SOT23-5)
5 PINS
5 PINS
RθJA
Junction-to-ambient thermal resistance
175.7
178.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
121.8
77.9
°C/W
RθJB
Junction-to-board thermal resistance
29.5
47.2
°C/W
ψJT
Junction-to-top characterization parameter
16.1
15.9
°C/W
ψJB
Junction-to-board characterization parameter
29.0
46.9
°C/W
THERMAL METRIC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378365/APPNOTE_LP2985_SF1_SF1_SF1
Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378365/THERMALFOOTER_SF1_SF1_SF1_SF1
New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378365/THERMALFOOTER_SF1_SF1_SF1_SF1
UNIT
DBV (SOT23-5)
DBV (SOT23-5)
5 PINS
5 PINS
THERMAL METRIC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378365/APPNOTE_LP2985_SF1_SF1_SF1
Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378365/THERMALFOOTER_SF1_SF1_SF1_SF1
New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378365/THERMALFOOTER_SF1_SF1_SF1_SF1
UNIT
THERMAL METRIC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378365/APPNOTE_LP2985_SF1_SF1_SF1
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378365/APPNOTE_LP2985_SF1_SF1_SF1Legacy Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378365/THERMALFOOTER_SF1_SF1_SF1_SF1
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378365/THERMALFOOTER_SF1_SF1_SF1_SF1New Chip #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378365/THERMALFOOTER_SF1_SF1_SF1_SF1
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378365/THERMALFOOTER_SF1_SF1_SF1_SF1UNIT
DBV (SOT23-5)
DBV (SOT23-5)
DBV (SOT23-5)DBV (SOT23-5)
5 PINS
5 PINS
5 PINS5 PINS
RθJA
Junction-to-ambient thermal resistance
175.7
178.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
121.8
77.9
°C/W
RθJB
Junction-to-board thermal resistance
29.5
47.2
°C/W
ψJT
Junction-to-top characterization parameter
16.1
15.9
°C/W
ψJB
Junction-to-board characterization parameter
29.0
46.9
°C/W
RθJA
Junction-to-ambient thermal resistance
175.7
178.6
°C/W
RθJA
θJAJunction-to-ambient thermal resistance175.7178.6°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
121.8
77.9
°C/W
RθJC(top)
θJC(top)Junction-to-case (top) thermal resistance121.877.9°C/W
RθJB
Junction-to-board thermal resistance
29.5
47.2
°C/W
RθJB
θJBJunction-to-board thermal resistance29.547.2°C/W
ψJT
Junction-to-top characterization parameter
16.1
15.9
°C/W
ψJT
JTJunction-to-top characterization parameter16.115.9°C/W
ψJB
Junction-to-board characterization parameter
29.0
46.9
°C/W
ψJB
JBJunction-to-board characterization parameter29.046.9°C/W
For more information about traditional and new thermal metrics, see the
Semiconductor and IC Package Thermal Metrics
application note.
Thermal performance results are based on the JEDEC standard of 2s2p PCB configuration. These thermal metric parameters can be further improved by 35-55% based on thermally optimized PCB layout designs. See the analysis of the
Impact of board layout on LDO thermal performance
application report.
For more information about traditional and new thermal metrics, see the
Semiconductor and IC Package Thermal Metrics
application note.
Semiconductor and IC Package Thermal Metrics
Semiconductor and IC Package Thermal MetricsThermal performance results are based on the JEDEC standard of 2s2p PCB configuration. These thermal metric parameters can be further improved by 35-55% based on thermally optimized PCB layout designs. See the analysis of the
Impact of board layout on LDO thermal performance
application report.
Impact of board layout on LDO thermal performance
Impact of board layout on LDO thermal performance
Electrical Characteristics
specified at TJ = 25 °C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0 µF, and COUT = 2.2 µF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
∆VOUT
Output voltage tolerance
IL = 1 mA
Legacy chip (standard grade)
–1.5
1.5
%
Legacy chip (A grade)
–1.0
1.0
New chip
–0.5
0.5
1 mA < IL < 50 mA
Legacy chip (standard grade)
–2
2
Legacy chip (A grade)
–1.5
1.5
New chip
–0.5
0.5
1 mA < IL < 50 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip (standard grade)
–3.5
3.5
Legacy chip (A grade)
–2
2
New chip
–1
1
ΔVOUT(ΔVIN)
Line regulation
VO(NOM) + 1 V < VIN < 16 V
Legacy chip
0.007
0.014
%/V
New chip
0.002
0.014
VO(NOM) + 1 V < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
0.007
0.032
New chip
0.002
0.032
ΔVOUT(ΔILOAD)
Load regulation
1 mA < IL < 50 mA, –40°C ≤ TJ ≤ 125°C, VIN = VO(NOM)+0.5 V
New chip
0.1
0.5
%/A
VDO
Dropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378397/A_5B260BA6_7C10_45AC_9F2D_6AB30CB61FCE_LP298X_LP2981_300MM_AA_ELECTRICAL_CHARACTERISTICS_ELECTRICAL_CHAR_LP2981_FOOTER1
IOUT = 0 mA
Legacy chip
1
3
mV
New chip
1
2.75
IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
5
New chip
3
IOUT = 1 mA
Legacy chip
7
10
New chip
11.5
14
IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
15
New chip
17
IOUT = 10 mA
Legacy chip
40
60
New chip
98
115
IOUT = 10 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
90
New chip
148
IOUT = 50 mA
Legacy chip
120
150
New chip
120
145
IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
225
New chip
184
IOUT = 80 mA
Legacy chip
180
225
New chip
150
165
IOUT = 80 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
325
New chip
204
IGND
GND pin current
IOUT = 0 mA
Legacy chip
65
95
µA
New chip
69
95
IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
125
New chip
123
IOUT = 1 mA
Legacy chip
80
110
New chip
78
110
IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
170
New chip
140
IOUT = 10 mA
Legacy chip
140
220
µA
New chip
175
210
IOUT = 10 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
460
New chip
250
IOUT = 50 mA
Legacy chip
375
600
µA
New chip
380
440
IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
1200
µA
New chip
650
µA
IOUT = 80 mA
Legacy chip
525
750
µA
New chip
575
720
µA
IOUT = 80 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
1400
µA
900
µA
VON/OFF < 0.3 V, VIN = 16 V
Legacy chip
0.01
0.8
µA
New chip
1.25
1.75
µA
VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
0.1
2
µA
New chip
1.12
2.75
µA
VUVLO+
Rising bias supply UVLO
VIN rising, –40°C ≤ TJ ≤ 125°C
New chip
2.2
2.4
V
VUVLO-
Falling bias supply UVLO
VIN falling, –40°C ≤ TJ ≤ 125°C
1.9
V
VUVLO(HYST)
UVLO hysteresis
–40°C ≤ TJ ≤ 125°C
0.130
V
IO(MAX)
Short Output Current
RL = 0 Ω (steady state)
Legacy chip
150
mA
New chip
150
mA
IO(PK)
Peak Output Current
VOUT ≥ VO(NOM) –5% (steady state)
Legacy chip
100
150
mA
New chip
100
150
mA
VON/OFF
ON/OFF input voltage
Low = Output OFF
Legacy chip
0.55
V
New chip
0.72
Low = Output OFF, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
0.15
New chip
0.15
High = Output ON
Legacy chip
1.4
New chip
0.85
High = Output ON, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
1.6
New chip
1.6
ION/OFF
ON/OFF input current
VON/OFF = 0 V
Legacy chip
0.01
µA
New chip
0.42
VON/OFF = 0 V, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
–2
µA
New chip
–0.9
µA
VON/OFF = 5 V
Legacy chip
5
µA
New chip
0.011
µA
VON/OFF = 5 V, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
15
µA
New chip
2.20
µA
ΔVO/ΔVIN
Ripple rejection
f = 1 kHz, CBYPASS = 10 nF, COUT = 10 µF
Legacy chip
45
dB
New chip
78
f = 100 kHz, CBYPASS = 10 nF , ILOAD = 50 mA
45
dB
Vn
Output noise voltage
Bandwidth = 300 Hz to 50 kHz, CNR/SS = 10 nF, COUT = 2.2 µF, VOUT = 1.8 V, ILOAD = 150 mA
Legacy chip
30
µVRMS
New chip
30
Bandwidth = 10 Hz to 100 kHz, CNR/SS = 10 nF, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA
50
Tsd+
Thermal shutdown threshold
Shutdown, temperature increasing
New chip
170
°C
Tsd-
Reset, temperature decreasing
150
Dropout voltage (VDO) is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured with a 1 V differential. VDO is measured with VIN = VOUT(nom) – 100 mV for fixed output devices.
Electrical Characteristics
specified at TJ = 25 °C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0 µF, and COUT = 2.2 µF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
∆VOUT
Output voltage tolerance
IL = 1 mA
Legacy chip (standard grade)
–1.5
1.5
%
Legacy chip (A grade)
–1.0
1.0
New chip
–0.5
0.5
1 mA < IL < 50 mA
Legacy chip (standard grade)
–2
2
Legacy chip (A grade)
–1.5
1.5
New chip
–0.5
0.5
1 mA < IL < 50 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip (standard grade)
–3.5
3.5
Legacy chip (A grade)
–2
2
New chip
–1
1
ΔVOUT(ΔVIN)
Line regulation
VO(NOM) + 1 V < VIN < 16 V
Legacy chip
0.007
0.014
%/V
New chip
0.002
0.014
VO(NOM) + 1 V < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
0.007
0.032
New chip
0.002
0.032
ΔVOUT(ΔILOAD)
Load regulation
1 mA < IL < 50 mA, –40°C ≤ TJ ≤ 125°C, VIN = VO(NOM)+0.5 V
New chip
0.1
0.5
%/A
VDO
Dropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378397/A_5B260BA6_7C10_45AC_9F2D_6AB30CB61FCE_LP298X_LP2981_300MM_AA_ELECTRICAL_CHARACTERISTICS_ELECTRICAL_CHAR_LP2981_FOOTER1
IOUT = 0 mA
Legacy chip
1
3
mV
New chip
1
2.75
IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
5
New chip
3
IOUT = 1 mA
Legacy chip
7
10
New chip
11.5
14
IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
15
New chip
17
IOUT = 10 mA
Legacy chip
40
60
New chip
98
115
IOUT = 10 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
90
New chip
148
IOUT = 50 mA
Legacy chip
120
150
New chip
120
145
IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
225
New chip
184
IOUT = 80 mA
Legacy chip
180
225
New chip
150
165
IOUT = 80 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
325
New chip
204
IGND
GND pin current
IOUT = 0 mA
Legacy chip
65
95
µA
New chip
69
95
IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
125
New chip
123
IOUT = 1 mA
Legacy chip
80
110
New chip
78
110
IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
170
New chip
140
IOUT = 10 mA
Legacy chip
140
220
µA
New chip
175
210
IOUT = 10 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
460
New chip
250
IOUT = 50 mA
Legacy chip
375
600
µA
New chip
380
440
IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
1200
µA
New chip
650
µA
IOUT = 80 mA
Legacy chip
525
750
µA
New chip
575
720
µA
IOUT = 80 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
1400
µA
900
µA
VON/OFF < 0.3 V, VIN = 16 V
Legacy chip
0.01
0.8
µA
New chip
1.25
1.75
µA
VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
0.1
2
µA
New chip
1.12
2.75
µA
VUVLO+
Rising bias supply UVLO
VIN rising, –40°C ≤ TJ ≤ 125°C
New chip
2.2
2.4
V
VUVLO-
Falling bias supply UVLO
VIN falling, –40°C ≤ TJ ≤ 125°C
1.9
V
VUVLO(HYST)
UVLO hysteresis
–40°C ≤ TJ ≤ 125°C
0.130
V
IO(MAX)
Short Output Current
RL = 0 Ω (steady state)
Legacy chip
150
mA
New chip
150
mA
IO(PK)
Peak Output Current
VOUT ≥ VO(NOM) –5% (steady state)
Legacy chip
100
150
mA
New chip
100
150
mA
VON/OFF
ON/OFF input voltage
Low = Output OFF
Legacy chip
0.55
V
New chip
0.72
Low = Output OFF, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
0.15
New chip
0.15
High = Output ON
Legacy chip
1.4
New chip
0.85
High = Output ON, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
1.6
New chip
1.6
ION/OFF
ON/OFF input current
VON/OFF = 0 V
Legacy chip
0.01
µA
New chip
0.42
VON/OFF = 0 V, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
–2
µA
New chip
–0.9
µA
VON/OFF = 5 V
Legacy chip
5
µA
New chip
0.011
µA
VON/OFF = 5 V, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
15
µA
New chip
2.20
µA
ΔVO/ΔVIN
Ripple rejection
f = 1 kHz, CBYPASS = 10 nF, COUT = 10 µF
Legacy chip
45
dB
New chip
78
f = 100 kHz, CBYPASS = 10 nF , ILOAD = 50 mA
45
dB
Vn
Output noise voltage
Bandwidth = 300 Hz to 50 kHz, CNR/SS = 10 nF, COUT = 2.2 µF, VOUT = 1.8 V, ILOAD = 150 mA
Legacy chip
30
µVRMS
New chip
30
Bandwidth = 10 Hz to 100 kHz, CNR/SS = 10 nF, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA
50
Tsd+
Thermal shutdown threshold
Shutdown, temperature increasing
New chip
170
°C
Tsd-
Reset, temperature decreasing
150
Dropout voltage (VDO) is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured with a 1 V differential. VDO is measured with VIN = VOUT(nom) – 100 mV for fixed output devices.
specified at TJ = 25 °C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0 µF, and COUT = 2.2 µF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
∆VOUT
Output voltage tolerance
IL = 1 mA
Legacy chip (standard grade)
–1.5
1.5
%
Legacy chip (A grade)
–1.0
1.0
New chip
–0.5
0.5
1 mA < IL < 50 mA
Legacy chip (standard grade)
–2
2
Legacy chip (A grade)
–1.5
1.5
New chip
–0.5
0.5
1 mA < IL < 50 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip (standard grade)
–3.5
3.5
Legacy chip (A grade)
–2
2
New chip
–1
1
ΔVOUT(ΔVIN)
Line regulation
VO(NOM) + 1 V < VIN < 16 V
Legacy chip
0.007
0.014
%/V
New chip
0.002
0.014
VO(NOM) + 1 V < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
0.007
0.032
New chip
0.002
0.032
ΔVOUT(ΔILOAD)
Load regulation
1 mA < IL < 50 mA, –40°C ≤ TJ ≤ 125°C, VIN = VO(NOM)+0.5 V
New chip
0.1
0.5
%/A
VDO
Dropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378397/A_5B260BA6_7C10_45AC_9F2D_6AB30CB61FCE_LP298X_LP2981_300MM_AA_ELECTRICAL_CHARACTERISTICS_ELECTRICAL_CHAR_LP2981_FOOTER1
IOUT = 0 mA
Legacy chip
1
3
mV
New chip
1
2.75
IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
5
New chip
3
IOUT = 1 mA
Legacy chip
7
10
New chip
11.5
14
IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
15
New chip
17
IOUT = 10 mA
Legacy chip
40
60
New chip
98
115
IOUT = 10 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
90
New chip
148
IOUT = 50 mA
Legacy chip
120
150
New chip
120
145
IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
225
New chip
184
IOUT = 80 mA
Legacy chip
180
225
New chip
150
165
IOUT = 80 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
325
New chip
204
IGND
GND pin current
IOUT = 0 mA
Legacy chip
65
95
µA
New chip
69
95
IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
125
New chip
123
IOUT = 1 mA
Legacy chip
80
110
New chip
78
110
IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
170
New chip
140
IOUT = 10 mA
Legacy chip
140
220
µA
New chip
175
210
IOUT = 10 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
460
New chip
250
IOUT = 50 mA
Legacy chip
375
600
µA
New chip
380
440
IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
1200
µA
New chip
650
µA
IOUT = 80 mA
Legacy chip
525
750
µA
New chip
575
720
µA
IOUT = 80 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
1400
µA
900
µA
VON/OFF < 0.3 V, VIN = 16 V
Legacy chip
0.01
0.8
µA
New chip
1.25
1.75
µA
VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
0.1
2
µA
New chip
1.12
2.75
µA
VUVLO+
Rising bias supply UVLO
VIN rising, –40°C ≤ TJ ≤ 125°C
New chip
2.2
2.4
V
VUVLO-
Falling bias supply UVLO
VIN falling, –40°C ≤ TJ ≤ 125°C
1.9
V
VUVLO(HYST)
UVLO hysteresis
–40°C ≤ TJ ≤ 125°C
0.130
V
IO(MAX)
Short Output Current
RL = 0 Ω (steady state)
Legacy chip
150
mA
New chip
150
mA
IO(PK)
Peak Output Current
VOUT ≥ VO(NOM) –5% (steady state)
Legacy chip
100
150
mA
New chip
100
150
mA
VON/OFF
ON/OFF input voltage
Low = Output OFF
Legacy chip
0.55
V
New chip
0.72
Low = Output OFF, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
0.15
New chip
0.15
High = Output ON
Legacy chip
1.4
New chip
0.85
High = Output ON, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
1.6
New chip
1.6
ION/OFF
ON/OFF input current
VON/OFF = 0 V
Legacy chip
0.01
µA
New chip
0.42
VON/OFF = 0 V, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
–2
µA
New chip
–0.9
µA
VON/OFF = 5 V
Legacy chip
5
µA
New chip
0.011
µA
VON/OFF = 5 V, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
15
µA
New chip
2.20
µA
ΔVO/ΔVIN
Ripple rejection
f = 1 kHz, CBYPASS = 10 nF, COUT = 10 µF
Legacy chip
45
dB
New chip
78
f = 100 kHz, CBYPASS = 10 nF , ILOAD = 50 mA
45
dB
Vn
Output noise voltage
Bandwidth = 300 Hz to 50 kHz, CNR/SS = 10 nF, COUT = 2.2 µF, VOUT = 1.8 V, ILOAD = 150 mA
Legacy chip
30
µVRMS
New chip
30
Bandwidth = 10 Hz to 100 kHz, CNR/SS = 10 nF, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA
50
Tsd+
Thermal shutdown threshold
Shutdown, temperature increasing
New chip
170
°C
Tsd-
Reset, temperature decreasing
150
specified at TJ = 25 °C, VIN = VOUT(nom) + 1.0 V or VIN = 2.5 V (whichever is greater), IOUT = 1 mA, VON/OFF = 2 V, CIN = 1.0 µF, and COUT = 2.2 µF (unless otherwise noted)JINOUT(nom)OUTON/OFFINOUT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
∆VOUT
Output voltage tolerance
IL = 1 mA
Legacy chip (standard grade)
–1.5
1.5
%
Legacy chip (A grade)
–1.0
1.0
New chip
–0.5
0.5
1 mA < IL < 50 mA
Legacy chip (standard grade)
–2
2
Legacy chip (A grade)
–1.5
1.5
New chip
–0.5
0.5
1 mA < IL < 50 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip (standard grade)
–3.5
3.5
Legacy chip (A grade)
–2
2
New chip
–1
1
ΔVOUT(ΔVIN)
Line regulation
VO(NOM) + 1 V < VIN < 16 V
Legacy chip
0.007
0.014
%/V
New chip
0.002
0.014
VO(NOM) + 1 V < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
0.007
0.032
New chip
0.002
0.032
ΔVOUT(ΔILOAD)
Load regulation
1 mA < IL < 50 mA, –40°C ≤ TJ ≤ 125°C, VIN = VO(NOM)+0.5 V
New chip
0.1
0.5
%/A
VDO
Dropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378397/A_5B260BA6_7C10_45AC_9F2D_6AB30CB61FCE_LP298X_LP2981_300MM_AA_ELECTRICAL_CHARACTERISTICS_ELECTRICAL_CHAR_LP2981_FOOTER1
IOUT = 0 mA
Legacy chip
1
3
mV
New chip
1
2.75
IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
5
New chip
3
IOUT = 1 mA
Legacy chip
7
10
New chip
11.5
14
IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
15
New chip
17
IOUT = 10 mA
Legacy chip
40
60
New chip
98
115
IOUT = 10 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
90
New chip
148
IOUT = 50 mA
Legacy chip
120
150
New chip
120
145
IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
225
New chip
184
IOUT = 80 mA
Legacy chip
180
225
New chip
150
165
IOUT = 80 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
325
New chip
204
IGND
GND pin current
IOUT = 0 mA
Legacy chip
65
95
µA
New chip
69
95
IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
125
New chip
123
IOUT = 1 mA
Legacy chip
80
110
New chip
78
110
IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
170
New chip
140
IOUT = 10 mA
Legacy chip
140
220
µA
New chip
175
210
IOUT = 10 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
460
New chip
250
IOUT = 50 mA
Legacy chip
375
600
µA
New chip
380
440
IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
1200
µA
New chip
650
µA
IOUT = 80 mA
Legacy chip
525
750
µA
New chip
575
720
µA
IOUT = 80 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
1400
µA
900
µA
VON/OFF < 0.3 V, VIN = 16 V
Legacy chip
0.01
0.8
µA
New chip
1.25
1.75
µA
VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
0.1
2
µA
New chip
1.12
2.75
µA
VUVLO+
Rising bias supply UVLO
VIN rising, –40°C ≤ TJ ≤ 125°C
New chip
2.2
2.4
V
VUVLO-
Falling bias supply UVLO
VIN falling, –40°C ≤ TJ ≤ 125°C
1.9
V
VUVLO(HYST)
UVLO hysteresis
–40°C ≤ TJ ≤ 125°C
0.130
V
IO(MAX)
Short Output Current
RL = 0 Ω (steady state)
Legacy chip
150
mA
New chip
150
mA
IO(PK)
Peak Output Current
VOUT ≥ VO(NOM) –5% (steady state)
Legacy chip
100
150
mA
New chip
100
150
mA
VON/OFF
ON/OFF input voltage
Low = Output OFF
Legacy chip
0.55
V
New chip
0.72
Low = Output OFF, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
0.15
New chip
0.15
High = Output ON
Legacy chip
1.4
New chip
0.85
High = Output ON, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
1.6
New chip
1.6
ION/OFF
ON/OFF input current
VON/OFF = 0 V
Legacy chip
0.01
µA
New chip
0.42
VON/OFF = 0 V, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
–2
µA
New chip
–0.9
µA
VON/OFF = 5 V
Legacy chip
5
µA
New chip
0.011
µA
VON/OFF = 5 V, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
15
µA
New chip
2.20
µA
ΔVO/ΔVIN
Ripple rejection
f = 1 kHz, CBYPASS = 10 nF, COUT = 10 µF
Legacy chip
45
dB
New chip
78
f = 100 kHz, CBYPASS = 10 nF , ILOAD = 50 mA
45
dB
Vn
Output noise voltage
Bandwidth = 300 Hz to 50 kHz, CNR/SS = 10 nF, COUT = 2.2 µF, VOUT = 1.8 V, ILOAD = 150 mA
Legacy chip
30
µVRMS
New chip
30
Bandwidth = 10 Hz to 100 kHz, CNR/SS = 10 nF, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA
50
Tsd+
Thermal shutdown threshold
Shutdown, temperature increasing
New chip
170
°C
Tsd-
Reset, temperature decreasing
150
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
∆VOUT
Output voltage tolerance
IL = 1 mA
Legacy chip (standard grade)
–1.5
1.5
%
Legacy chip (A grade)
–1.0
1.0
New chip
–0.5
0.5
1 mA < IL < 50 mA
Legacy chip (standard grade)
–2
2
Legacy chip (A grade)
–1.5
1.5
New chip
–0.5
0.5
1 mA < IL < 50 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip (standard grade)
–3.5
3.5
Legacy chip (A grade)
–2
2
New chip
–1
1
ΔVOUT(ΔVIN)
Line regulation
VO(NOM) + 1 V < VIN < 16 V
Legacy chip
0.007
0.014
%/V
New chip
0.002
0.014
VO(NOM) + 1 V < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
0.007
0.032
New chip
0.002
0.032
ΔVOUT(ΔILOAD)
Load regulation
1 mA < IL < 50 mA, –40°C ≤ TJ ≤ 125°C, VIN = VO(NOM)+0.5 V
New chip
0.1
0.5
%/A
VDO
Dropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378397/A_5B260BA6_7C10_45AC_9F2D_6AB30CB61FCE_LP298X_LP2981_300MM_AA_ELECTRICAL_CHARACTERISTICS_ELECTRICAL_CHAR_LP2981_FOOTER1
IOUT = 0 mA
Legacy chip
1
3
mV
New chip
1
2.75
IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
5
New chip
3
IOUT = 1 mA
Legacy chip
7
10
New chip
11.5
14
IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
15
New chip
17
IOUT = 10 mA
Legacy chip
40
60
New chip
98
115
IOUT = 10 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
90
New chip
148
IOUT = 50 mA
Legacy chip
120
150
New chip
120
145
IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
225
New chip
184
IOUT = 80 mA
Legacy chip
180
225
New chip
150
165
IOUT = 80 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
325
New chip
204
IGND
GND pin current
IOUT = 0 mA
Legacy chip
65
95
µA
New chip
69
95
IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
125
New chip
123
IOUT = 1 mA
Legacy chip
80
110
New chip
78
110
IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
170
New chip
140
IOUT = 10 mA
Legacy chip
140
220
µA
New chip
175
210
IOUT = 10 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
460
New chip
250
IOUT = 50 mA
Legacy chip
375
600
µA
New chip
380
440
IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
1200
µA
New chip
650
µA
IOUT = 80 mA
Legacy chip
525
750
µA
New chip
575
720
µA
IOUT = 80 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
1400
µA
900
µA
VON/OFF < 0.3 V, VIN = 16 V
Legacy chip
0.01
0.8
µA
New chip
1.25
1.75
µA
VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
0.1
2
µA
New chip
1.12
2.75
µA
VUVLO+
Rising bias supply UVLO
VIN rising, –40°C ≤ TJ ≤ 125°C
New chip
2.2
2.4
V
VUVLO-
Falling bias supply UVLO
VIN falling, –40°C ≤ TJ ≤ 125°C
1.9
V
VUVLO(HYST)
UVLO hysteresis
–40°C ≤ TJ ≤ 125°C
0.130
V
IO(MAX)
Short Output Current
RL = 0 Ω (steady state)
Legacy chip
150
mA
New chip
150
mA
IO(PK)
Peak Output Current
VOUT ≥ VO(NOM) –5% (steady state)
Legacy chip
100
150
mA
New chip
100
150
mA
VON/OFF
ON/OFF input voltage
Low = Output OFF
Legacy chip
0.55
V
New chip
0.72
Low = Output OFF, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
0.15
New chip
0.15
High = Output ON
Legacy chip
1.4
New chip
0.85
High = Output ON, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
1.6
New chip
1.6
ION/OFF
ON/OFF input current
VON/OFF = 0 V
Legacy chip
0.01
µA
New chip
0.42
VON/OFF = 0 V, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
–2
µA
New chip
–0.9
µA
VON/OFF = 5 V
Legacy chip
5
µA
New chip
0.011
µA
VON/OFF = 5 V, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
15
µA
New chip
2.20
µA
ΔVO/ΔVIN
Ripple rejection
f = 1 kHz, CBYPASS = 10 nF, COUT = 10 µF
Legacy chip
45
dB
New chip
78
f = 100 kHz, CBYPASS = 10 nF , ILOAD = 50 mA
45
dB
Vn
Output noise voltage
Bandwidth = 300 Hz to 50 kHz, CNR/SS = 10 nF, COUT = 2.2 µF, VOUT = 1.8 V, ILOAD = 150 mA
Legacy chip
30
µVRMS
New chip
30
Bandwidth = 10 Hz to 100 kHz, CNR/SS = 10 nF, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA
50
Tsd+
Thermal shutdown threshold
Shutdown, temperature increasing
New chip
170
°C
Tsd-
Reset, temperature decreasing
150
∆VOUT
Output voltage tolerance
IL = 1 mA
Legacy chip (standard grade)
–1.5
1.5
%
∆VOUT
OUTOutput voltage toleranceIL = 1 mALLegacy chip (standard grade)–1.51.5%
Legacy chip (A grade)
–1.0
1.0
Legacy chip (A grade)–1.01.0
New chip
–0.5
0.5
New chip–0.50.5
1 mA < IL < 50 mA
Legacy chip (standard grade)
–2
2
1 mA < IL < 50 mALLegacy chip (standard grade)–22
Legacy chip (A grade)
–1.5
1.5
Legacy chip (A grade)–1.51.5
New chip
–0.5
0.5
New chip–0.50.5
1 mA < IL < 50 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip (standard grade)
–3.5
3.5
1 mA < IL < 50 mA, –40°C ≤ TJ ≤ 125°CLJ Legacy chip (standard grade)–3.53.5
Legacy chip (A grade)
–2
2
Legacy chip (A grade)–22
New chip
–1
1
New chip–11
ΔVOUT(ΔVIN)
Line regulation
VO(NOM) + 1 V < VIN < 16 V
Legacy chip
0.007
0.014
%/V
ΔVOUT(ΔVIN)
OUT(ΔVIN)Line regulationVO(NOM) + 1 V < VIN < 16 VO(NOM)INLegacy chip0.0070.014%/V
New chip
0.002
0.014
New chip0.0020.014
VO(NOM) + 1 V < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
0.007
0.032
VO(NOM) + 1 V < VIN < 16 V, –40°C ≤ TJ ≤ 125°CO(NOM)INJ Legacy chip0.0070.032
New chip
0.002
0.032
New chip0.0020.032
ΔVOUT(ΔILOAD)
Load regulation
1 mA < IL < 50 mA, –40°C ≤ TJ ≤ 125°C, VIN = VO(NOM)+0.5 V
New chip
0.1
0.5
%/A
ΔVOUT(ΔILOAD)
OUT(ΔILOAD)Load regulation1 mA < IL < 50 mA, –40°C ≤ TJ ≤ 125°C, VIN = VO(NOM)+0.5 VLJ INO(NOM)New chip0.10.5%/A
VDO
Dropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378397/A_5B260BA6_7C10_45AC_9F2D_6AB30CB61FCE_LP298X_LP2981_300MM_AA_ELECTRICAL_CHARACTERISTICS_ELECTRICAL_CHAR_LP2981_FOOTER1
IOUT = 0 mA
Legacy chip
1
3
mV
VDO
DODropout voltage#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378397/A_5B260BA6_7C10_45AC_9F2D_6AB30CB61FCE_LP298X_LP2981_300MM_AA_ELECTRICAL_CHARACTERISTICS_ELECTRICAL_CHAR_LP2981_FOOTER1
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000378397/A_5B260BA6_7C10_45AC_9F2D_6AB30CB61FCE_LP298X_LP2981_300MM_AA_ELECTRICAL_CHARACTERISTICS_ELECTRICAL_CHAR_LP2981_FOOTER1IOUT = 0 mAOUTLegacy chip13mV
New chip
1
2.75
New chip12.75
IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
5
IOUT = 0 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip5
New chip
3
New chip3
IOUT = 1 mA
Legacy chip
7
10
IOUT = 1 mAOUTLegacy chip710
New chip
11.5
14
New chip11.514
IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
15
IOUT = 1 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip15
New chip
17
New chip17
IOUT = 10 mA
Legacy chip
40
60
IOUT = 10 mAOUTLegacy chip4060
New chip
98
115
New chip98115
IOUT = 10 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
90
IOUT = 10 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip90
New chip
148
New chip148
IOUT = 50 mA
Legacy chip
120
150
IOUT = 50 mAOUTLegacy chip120150
New chip
120
145
New chip120145
IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
225
IOUT = 50 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip225
New chip
184
New chip184
IOUT = 80 mA
Legacy chip
180
225
IOUT = 80 mAOUTLegacy chip180225
New chip
150
165
New chip150165
IOUT = 80 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
325
IOUT = 80 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip325
New chip
204
New chip204
IGND
GND pin current
IOUT = 0 mA
Legacy chip
65
95
µA
IGND
GND GND pin currentIOUT = 0 mAOUTLegacy chip6595µA
New chip
69
95
New chip6995
IOUT = 0 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
125
IOUT = 0 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip125
New chip
123
New chip123
IOUT = 1 mA
Legacy chip
80
110
IOUT = 1 mAOUTLegacy chip80110
New chip
78
110
New chip78110
IOUT = 1 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
170
IOUT = 1 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip170
New chip
140
New chip140
IOUT = 10 mA
Legacy chip
140
220
µA
IOUT = 10 mAOUTLegacy chip140220µA
New chip
175
210
New chip175210
IOUT = 10 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
460
IOUT = 10 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip460
New chip
250
New chip250
IOUT = 50 mA
Legacy chip
375
600
µA
IOUT = 50 mAOUTLegacy chip375600µA
New chip
380
440
New chip380440
IOUT = 50 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
1200
µA
IOUT = 50 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip1200µA
New chip
650
µA
New chip650µA
IOUT = 80 mA
Legacy chip
525
750
µA
IOUT = 80 mAOUTLegacy chip525750µA
New chip
575
720
µA
New chip575720µA
IOUT = 80 mA, –40°C ≤ TJ ≤ 125°C
Legacy chip
1400
µA
IOUT = 80 mA, –40°C ≤ TJ ≤ 125°COUTJ Legacy chip1400µA
900
µA
900µA
VON/OFF < 0.3 V, VIN = 16 V
Legacy chip
0.01
0.8
µA
VON/OFF < 0.3 V, VIN = 16 VON/OFFINLegacy chip0.010.8µA
New chip
1.25
1.75
µA
New chip1.251.75µA
VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
0.1
2
µA
VON/OFF < 0.15 V, VIN = 16 V, –40°C ≤ TJ ≤ 125°CON/OFFINJ Legacy chip0.12µA
New chip
1.12
2.75
µA
New chip1.122.75µA
VUVLO+
Rising bias supply UVLO
VIN rising, –40°C ≤ TJ ≤ 125°C
New chip
2.2
2.4
V
VUVLO+
UVLO+Rising bias supply UVLOVIN rising, –40°C ≤ TJ ≤ 125°CINJ New chip2.22.4V
VUVLO-
Falling bias supply UVLO
VIN falling, –40°C ≤ TJ ≤ 125°C
1.9
V
VUVLO-
UVLO-Falling bias supply UVLOVIN falling, –40°C ≤ TJ ≤ 125°CINJ 1.9V
VUVLO(HYST)
UVLO hysteresis
–40°C ≤ TJ ≤ 125°C
0.130
V
VUVLO(HYST)
UVLO(HYST)UVLO hysteresis–40°C ≤ TJ ≤ 125°CJ 0.130V
IO(MAX)
Short Output Current
RL = 0 Ω (steady state)
Legacy chip
150
mA
IO(MAX)
O(MAX)Short Output CurrentRL = 0 Ω (steady state)LLegacy chip150mA
New chip
150
mA
New chip150mA
IO(PK)
Peak Output Current
VOUT ≥ VO(NOM) –5% (steady state)
Legacy chip
100
150
mA
IO(PK)
O(PK)Peak Output CurrentVOUT ≥ VO(NOM) –5% (steady state)OUTO(NOM)Legacy chip100150mA
New chip
100
150
mA
New chip100150mA
VON/OFF
ON/OFF input voltage
Low = Output OFF
Legacy chip
0.55
V
VON/OFF
ON/OFF
OFFON/OFF input voltageOFFLow = Output OFFLegacy chip0.55V
New chip
0.72
New chip0.72
Low = Output OFF, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
0.15
Low = Output OFF, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°COUTINJ Legacy chip0.15
New chip
0.15
New chip0.15
High = Output ON
Legacy chip
1.4
High = Output ONLegacy chip1.4
New chip
0.85
New chip0.85
High = Output ON, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
1.6
High = Output ON, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°COUTINJ Legacy chip1.6
New chip
1.6
New chip1.6
ION/OFF
ON/OFF input current
VON/OFF = 0 V
Legacy chip
0.01
µA
ION/OFF
ON/OFF
OFFON/OFF input currentVON/OFF = 0 VON/OFFLegacy chip0.01µA
New chip
0.42
New chip0.42
VON/OFF = 0 V, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
–2
µA
VON/OFF = 0 V, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°CON/OFFOUTINJ Legacy chip–2µA
New chip
–0.9
µA
New chip–0.9µA
VON/OFF = 5 V
Legacy chip
5
µA
VON/OFF = 5 VON/OFFLegacy chip5µA
New chip
0.011
µA
New chip0.011µA
VON/OFF = 5 V, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°C
Legacy chip
15
µA
VON/OFF = 5 V, VOUT + 1 < VIN < 16 V, –40°C ≤ TJ ≤ 125°CON/OFFOUTINJ Legacy chip15µA
New chip
2.20
µA
New chip2.20µA
ΔVO/ΔVIN
Ripple rejection
f = 1 kHz, CBYPASS = 10 nF, COUT = 10 µF
Legacy chip
45
dB
ΔVO/ΔVIN
OINRipple rejectionf = 1 kHz, CBYPASS = 10 nF, COUT = 10 µFBYPASSOUTLegacy chip45dB
New chip
78
New chip78
f = 100 kHz, CBYPASS = 10 nF , ILOAD = 50 mA
45
dB
f = 100 kHz, CBYPASS = 10 nF , ILOAD = 50 mABYPASS LOAD 45dB
Vn
Output noise voltage
Bandwidth = 300 Hz to 50 kHz, CNR/SS = 10 nF, COUT = 2.2 µF, VOUT = 1.8 V, ILOAD = 150 mA
Legacy chip
30
µVRMS
Vn
nOutput noise voltageBandwidth = 300 Hz to 50 kHz, CNR/SS = 10 nF, COUT = 2.2 µF, VOUT = 1.8 V, ILOAD = 150 mANR/SSOUT OUTLOADLegacy chip30µVRMS
VRMS
New chip
30
New chip30
Bandwidth = 10 Hz to 100 kHz, CNR/SS = 10 nF, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mA
50
Bandwidth = 10 Hz to 100 kHz, CNR/SS = 10 nF, COUT = 2.2 µF, VOUT = 3.3 V, ILOAD = 150 mANR/SSOUT OUTLOAD50
Tsd+
Thermal shutdown threshold
Shutdown, temperature increasing
New chip
170
°C
Tsd+
sd+Thermal shutdown thresholdShutdown, temperature increasingNew chip170°C
Tsd-
Reset, temperature decreasing
150
Tsd-
sd-Reset, temperature decreasing150
Dropout voltage (VDO) is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured with a 1 V differential. VDO is measured with VIN = VOUT(nom) – 100 mV for fixed output devices.
Dropout voltage (VDO) is defined as the input-to-output differential at which the output voltage drops 100 mV below the value measured with a 1 V differential. VDO is measured with VIN = VOUT(nom) – 100 mV for fixed output devices.DODOINOUT(nom)
Typical Characteristics
Unless otherwise specified: TA = 25°C, VIN = VO(NOM) + 1 V, COUT = 4.7 μF, CIN = 1 μF, all voltage options, ON/
OFF pin tied to VIN.
Output Voltage
versus Temperature (Legacy Chip)
Output Voltage
versus Temperature (Legacy Chip)
Output Voltage
versus Temperature (Legacy Chip)
Output Voltage
versus Temperature (New Chip)
VIN = 4.3 V, VOUT = 3.3 V
Output Voltage
versus VIN (Legacy Chip)
VOUT = 5.0
V
Output Voltage
versus VIN (Legacy Chip)
VOUT = 3.3
V
Output Voltage
versus VIN (Legacy Chip)
VOUT = 3.0
V
Output Voltage versus VIN
(New Chip)
VOUT = 3.3
V
Dropout Voltage
versus Temperature (Legacy Chip)
Dropout Voltage versus Temperature
(New Chip)
Dropout Voltage
versus Load Current (Legacy Chip)
Dropout Voltage versus Load Current
(New Chip)
Ground Pin
Current versus Temperature (Legacy Chip)
Ground Pin
Current versus Temperature (New Chip)
Ground Pin
Current versus Load Current (Legacy Chip)
Ground Pin Current versus Load
Current (New Chip)
Input Current
versus VIN (Legacy Chip)
VOUT = 5
V
Input Current
versus VIN (Legacy Chip)
VOUT = 5
V
Input Current versus Input Voltage
(New Chip)
VOUT = 3.3 V
Line Transient
Response (Legacy chip)
Line Transient
Response (Legacy chip)
Line Transient Response (New
Chip)
VOUT = 3.3 V, ΔVIN = 1 V, IOUT = 50 mA,
dV/dt = 1 V/μs
Load Transient
Response (Legacy chip)
Load Transient
Response (Legacy chip)
Load Transient
Response (Legacy chip)
Load Transient
Response (Legacy chip)
Load Transient Response (New
Chip)
dI/dt = 1 A/μs
Short-Circuit
Current versus Time (Legacy chip)
VIN = 6
V
Short-Circuit
Current versus Time (Legacy chip)
VIN = 16
V
Short-Circuit Current versus Time
(New Chip)
VIN = 6 V
Short-Circuit Current versus Time
(New Chip)
Instantaneous
Short-Circuit Current versus Temperature (Legacy chip)
Short-Circuit Current versus
Temperature (New Chip)
Instantaneous
Short Circuit Current versus Output Voltage (Legacy chip)
Output
Impedance versus Frequency (Legacy chip)
Output
Impedance versus Frequency (Legacy chip)
ON/
OFF Pin Current versus VON/OFF (Legacy chip)
ON/OFF Pin Current versus
VON/OFF
(New Chip)
VIN = 16
V
ON/OFF Pin Current versus
VON/OFF
(New Chip)
VIN = 4.3
V
ON/
OFF Threshold versus Temperature (Legacy chip)
ON/
OFF Threshold versus Temperature (New chip)
Input-to-Output
Leakage versus Temperature (Legacy chip)
Output Reverse
Leakage versus Temperature (Legacy chip)
Output Reverse
Leakage versus Temperature (New chip)
Output Noise
Density (Legacy chip)
Output Noise
Density (Legacy chip)
Output Noise
Density (Legacy chip)
Output Noise Density versus
Frequency (New Chip)
VIN = 4.3V, VOUT = 3.3V, COUT = 2.2μF
and ILOAD = 50 mA
Output Noise Density versus
Frequency for New Chip
VIN = 4.3V, VOUT = 3.3V, COUT = 2.2μF
and ILOAD = 1 mA
Ripple
Rejection (Legacy chip)
Ripple Rejection versus IOUT
(New Chip)
VOUT = 3.3 V, Cbyp = 0 nF
Ripple Rejection versus
IOUT (New Chip)
VOUT = 3.3 V, Cbyp = 10 nF
Turnon Waveform
(Legacy chip)
Turnon Waveform
(Legacy chip)
Turnon Waveform
(Legacy chip)
Turnon Waveform (New chip)
Cbyp = 0 nF
Turnon Waveform (New chip)
Cbyp = 0.1 nF
Turnon Waveform (New chip)
Cbyp = 1 nF
Typical Characteristics
Unless otherwise specified: TA = 25°C, VIN = VO(NOM) + 1 V, COUT = 4.7 μF, CIN = 1 μF, all voltage options, ON/
OFF pin tied to VIN.
Output Voltage
versus Temperature (Legacy Chip)
Output Voltage
versus Temperature (Legacy Chip)
Output Voltage
versus Temperature (Legacy Chip)
Output Voltage
versus Temperature (New Chip)
VIN = 4.3 V, VOUT = 3.3 V
Output Voltage
versus VIN (Legacy Chip)
VOUT = 5.0
V
Output Voltage
versus VIN (Legacy Chip)
VOUT = 3.3
V
Output Voltage
versus VIN (Legacy Chip)
VOUT = 3.0
V
Output Voltage versus VIN
(New Chip)
VOUT = 3.3
V
Dropout Voltage
versus Temperature (Legacy Chip)
Dropout Voltage versus Temperature
(New Chip)
Dropout Voltage
versus Load Current (Legacy Chip)
Dropout Voltage versus Load Current
(New Chip)
Ground Pin
Current versus Temperature (Legacy Chip)
Ground Pin
Current versus Temperature (New Chip)
Ground Pin
Current versus Load Current (Legacy Chip)
Ground Pin Current versus Load
Current (New Chip)
Input Current
versus VIN (Legacy Chip)
VOUT = 5
V
Input Current
versus VIN (Legacy Chip)
VOUT = 5
V
Input Current versus Input Voltage
(New Chip)
VOUT = 3.3 V
Line Transient
Response (Legacy chip)
Line Transient
Response (Legacy chip)
Line Transient Response (New
Chip)
VOUT = 3.3 V, ΔVIN = 1 V, IOUT = 50 mA,
dV/dt = 1 V/μs
Load Transient
Response (Legacy chip)
Load Transient
Response (Legacy chip)
Load Transient
Response (Legacy chip)
Load Transient
Response (Legacy chip)
Load Transient Response (New
Chip)
dI/dt = 1 A/μs
Short-Circuit
Current versus Time (Legacy chip)
VIN = 6
V
Short-Circuit
Current versus Time (Legacy chip)
VIN = 16
V
Short-Circuit Current versus Time
(New Chip)
VIN = 6 V
Short-Circuit Current versus Time
(New Chip)
Instantaneous
Short-Circuit Current versus Temperature (Legacy chip)
Short-Circuit Current versus
Temperature (New Chip)
Instantaneous
Short Circuit Current versus Output Voltage (Legacy chip)
Output
Impedance versus Frequency (Legacy chip)
Output
Impedance versus Frequency (Legacy chip)
ON/
OFF Pin Current versus VON/OFF (Legacy chip)
ON/OFF Pin Current versus
VON/OFF
(New Chip)
VIN = 16
V
ON/OFF Pin Current versus
VON/OFF
(New Chip)
VIN = 4.3
V
ON/
OFF Threshold versus Temperature (Legacy chip)
ON/
OFF Threshold versus Temperature (New chip)
Input-to-Output
Leakage versus Temperature (Legacy chip)
Output Reverse
Leakage versus Temperature (Legacy chip)
Output Reverse
Leakage versus Temperature (New chip)
Output Noise
Density (Legacy chip)
Output Noise
Density (Legacy chip)
Output Noise
Density (Legacy chip)
Output Noise Density versus
Frequency (New Chip)
VIN = 4.3V, VOUT = 3.3V, COUT = 2.2μF
and ILOAD = 50 mA
Output Noise Density versus
Frequency for New Chip
VIN = 4.3V, VOUT = 3.3V, COUT = 2.2μF
and ILOAD = 1 mA
Ripple
Rejection (Legacy chip)
Ripple Rejection versus IOUT
(New Chip)
VOUT = 3.3 V, Cbyp = 0 nF
Ripple Rejection versus
IOUT (New Chip)
VOUT = 3.3 V, Cbyp = 10 nF
Turnon Waveform
(Legacy chip)
Turnon Waveform
(Legacy chip)
Turnon Waveform
(Legacy chip)
Turnon Waveform (New chip)
Cbyp = 0 nF
Turnon Waveform (New chip)
Cbyp = 0.1 nF
Turnon Waveform (New chip)
Cbyp = 1 nF
Unless otherwise specified: TA = 25°C, VIN = VO(NOM) + 1 V, COUT = 4.7 μF, CIN = 1 μF, all voltage options, ON/
OFF pin tied to VIN.
Output Voltage
versus Temperature (Legacy Chip)
Output Voltage
versus Temperature (Legacy Chip)
Output Voltage
versus Temperature (Legacy Chip)
Output Voltage
versus Temperature (New Chip)
VIN = 4.3 V, VOUT = 3.3 V
Output Voltage
versus VIN (Legacy Chip)
VOUT = 5.0
V
Output Voltage
versus VIN (Legacy Chip)
VOUT = 3.3
V
Output Voltage
versus VIN (Legacy Chip)
VOUT = 3.0
V
Output Voltage versus VIN
(New Chip)
VOUT = 3.3
V
Dropout Voltage
versus Temperature (Legacy Chip)
Dropout Voltage versus Temperature
(New Chip)
Dropout Voltage
versus Load Current (Legacy Chip)
Dropout Voltage versus Load Current
(New Chip)
Ground Pin
Current versus Temperature (Legacy Chip)
Ground Pin
Current versus Temperature (New Chip)
Ground Pin
Current versus Load Current (Legacy Chip)
Ground Pin Current versus Load
Current (New Chip)
Input Current
versus VIN (Legacy Chip)
VOUT = 5
V
Input Current
versus VIN (Legacy Chip)
VOUT = 5
V
Input Current versus Input Voltage
(New Chip)
VOUT = 3.3 V
Line Transient
Response (Legacy chip)
Line Transient
Response (Legacy chip)
Line Transient Response (New
Chip)
VOUT = 3.3 V, ΔVIN = 1 V, IOUT = 50 mA,
dV/dt = 1 V/μs
Load Transient
Response (Legacy chip)
Load Transient
Response (Legacy chip)
Load Transient
Response (Legacy chip)
Load Transient
Response (Legacy chip)
Load Transient Response (New
Chip)
dI/dt = 1 A/μs
Short-Circuit
Current versus Time (Legacy chip)
VIN = 6
V
Short-Circuit
Current versus Time (Legacy chip)
VIN = 16
V
Short-Circuit Current versus Time
(New Chip)
VIN = 6 V
Short-Circuit Current versus Time
(New Chip)
Instantaneous
Short-Circuit Current versus Temperature (Legacy chip)
Short-Circuit Current versus
Temperature (New Chip)
Instantaneous
Short Circuit Current versus Output Voltage (Legacy chip)
Output
Impedance versus Frequency (Legacy chip)
Output
Impedance versus Frequency (Legacy chip)
ON/
OFF Pin Current versus VON/OFF (Legacy chip)
ON/OFF Pin Current versus
VON/OFF
(New Chip)
VIN = 16
V
ON/OFF Pin Current versus
VON/OFF
(New Chip)
VIN = 4.3
V
ON/
OFF Threshold versus Temperature (Legacy chip)
ON/
OFF Threshold versus Temperature (New chip)
Input-to-Output
Leakage versus Temperature (Legacy chip)
Output Reverse
Leakage versus Temperature (Legacy chip)
Output Reverse
Leakage versus Temperature (New chip)
Output Noise
Density (Legacy chip)
Output Noise
Density (Legacy chip)
Output Noise
Density (Legacy chip)
Output Noise Density versus
Frequency (New Chip)
VIN = 4.3V, VOUT = 3.3V, COUT = 2.2μF
and ILOAD = 50 mA
Output Noise Density versus
Frequency for New Chip
VIN = 4.3V, VOUT = 3.3V, COUT = 2.2μF
and ILOAD = 1 mA
Ripple
Rejection (Legacy chip)
Ripple Rejection versus IOUT
(New Chip)
VOUT = 3.3 V, Cbyp = 0 nF
Ripple Rejection versus
IOUT (New Chip)
VOUT = 3.3 V, Cbyp = 10 nF
Turnon Waveform
(Legacy chip)
Turnon Waveform
(Legacy chip)
Turnon Waveform
(Legacy chip)
Turnon Waveform (New chip)
Cbyp = 0 nF
Turnon Waveform (New chip)
Cbyp = 0.1 nF
Turnon Waveform (New chip)
Cbyp = 1 nF
Unless otherwise specified: TA = 25°C, VIN = VO(NOM) + 1 V, COUT = 4.7 μF, CIN = 1 μF, all voltage options, ON/
OFF pin tied to VIN.AINO(NOM)OUTINOFFIN
Output Voltage
versus Temperature (Legacy Chip)
Output Voltage
versus Temperature (Legacy Chip)
Output Voltage
versus Temperature (Legacy Chip)
Output Voltage
versus Temperature (New Chip)
VIN = 4.3 V, VOUT = 3.3 V
Output Voltage
versus VIN (Legacy Chip)
VOUT = 5.0
V
Output Voltage
versus VIN (Legacy Chip)
VOUT = 3.3
V
Output Voltage
versus VIN (Legacy Chip)
VOUT = 3.0
V
Output Voltage versus VIN
(New Chip)
VOUT = 3.3
V
Dropout Voltage
versus Temperature (Legacy Chip)
Dropout Voltage versus Temperature
(New Chip)
Dropout Voltage
versus Load Current (Legacy Chip)
Dropout Voltage versus Load Current
(New Chip)
Ground Pin
Current versus Temperature (Legacy Chip)
Ground Pin
Current versus Temperature (New Chip)
Ground Pin
Current versus Load Current (Legacy Chip)
Ground Pin Current versus Load
Current (New Chip)
Input Current
versus VIN (Legacy Chip)
VOUT = 5
V
Input Current
versus VIN (Legacy Chip)
VOUT = 5
V
Input Current versus Input Voltage
(New Chip)
VOUT = 3.3 V
Line Transient
Response (Legacy chip)
Line Transient
Response (Legacy chip)
Line Transient Response (New
Chip)
VOUT = 3.3 V, ΔVIN = 1 V, IOUT = 50 mA,
dV/dt = 1 V/μs
Load Transient
Response (Legacy chip)
Load Transient
Response (Legacy chip)
Load Transient
Response (Legacy chip)
Load Transient
Response (Legacy chip)
Load Transient Response (New
Chip)
dI/dt = 1 A/μs
Short-Circuit
Current versus Time (Legacy chip)
VIN = 6
V
Short-Circuit
Current versus Time (Legacy chip)
VIN = 16
V
Short-Circuit Current versus Time
(New Chip)
VIN = 6 V
Short-Circuit Current versus Time
(New Chip)
Instantaneous
Short-Circuit Current versus Temperature (Legacy chip)
Short-Circuit Current versus
Temperature (New Chip)
Instantaneous
Short Circuit Current versus Output Voltage (Legacy chip)
Output
Impedance versus Frequency (Legacy chip)
Output
Impedance versus Frequency (Legacy chip)
ON/
OFF Pin Current versus VON/OFF (Legacy chip)
ON/OFF Pin Current versus
VON/OFF
(New Chip)
VIN = 16
V
ON/OFF Pin Current versus
VON/OFF
(New Chip)
VIN = 4.3
V
ON/
OFF Threshold versus Temperature (Legacy chip)
ON/
OFF Threshold versus Temperature (New chip)
Input-to-Output
Leakage versus Temperature (Legacy chip)
Output Reverse
Leakage versus Temperature (Legacy chip)
Output Reverse
Leakage versus Temperature (New chip)
Output Noise
Density (Legacy chip)
Output Noise
Density (Legacy chip)
Output Noise
Density (Legacy chip)
Output Noise Density versus
Frequency (New Chip)
VIN = 4.3V, VOUT = 3.3V, COUT = 2.2μF
and ILOAD = 50 mA
Output Noise Density versus
Frequency for New Chip
VIN = 4.3V, VOUT = 3.3V, COUT = 2.2μF
and ILOAD = 1 mA
Ripple
Rejection (Legacy chip)
Ripple Rejection versus IOUT
(New Chip)
VOUT = 3.3 V, Cbyp = 0 nF
Ripple Rejection versus
IOUT (New Chip)
VOUT = 3.3 V, Cbyp = 10 nF
Turnon Waveform
(Legacy chip)
Turnon Waveform
(Legacy chip)
Turnon Waveform
(Legacy chip)
Turnon Waveform (New chip)
Cbyp = 0 nF
Turnon Waveform (New chip)
Cbyp = 0.1 nF
Turnon Waveform (New chip)
Cbyp = 1 nF
Output Voltage
versus Temperature (Legacy Chip)
Output Voltage
versus Temperature (Legacy Chip)
Output Voltage
versus Temperature (Legacy Chip)
Output Voltage
versus Temperature (Legacy Chip)
Output Voltage
versus Temperature (Legacy Chip)
Output Voltage
versus Temperature (Legacy Chip)
Output Voltage
versus Temperature (New Chip)
VIN = 4.3 V, VOUT = 3.3 V
Output Voltage
versus Temperature (New Chip)
VIN = 4.3 V, VOUT = 3.3 V
VIN = 4.3 V, VOUT = 3.3 V
VIN = 4.3 V, VOUT = 3.3 V
VIN = 4.3 V, VOUT = 3.3 V
VIN = 4.3 V, VOUT = 3.3 V
VIN = 4.3 V, VOUT = 3.3 VINOUT
Output Voltage
versus VIN (Legacy Chip)
VOUT = 5.0
V
Output Voltage
versus VIN (Legacy Chip)IN
VOUT = 5.0
V
VOUT = 5.0
V
VOUT = 5.0
V
VOUT = 5.0
V
VOUT = 5.0
V
VOUT = 5.0
VOUT
Output Voltage
versus VIN (Legacy Chip)
VOUT = 3.3
V
Output Voltage
versus VIN (Legacy Chip)IN
VOUT = 3.3
V
VOUT = 3.3
V
VOUT = 3.3
V
VOUT = 3.3
V
VOUT = 3.3
V
VOUT = 3.3
VOUT
Output Voltage
versus VIN (Legacy Chip)
VOUT = 3.0
V
Output Voltage
versus VIN (Legacy Chip)IN
VOUT = 3.0
V
VOUT = 3.0
V
VOUT = 3.0
V
VOUT = 3.0
V
VOUT = 3.0
V
VOUT = 3.0
VOUT
Output Voltage versus VIN
(New Chip)
VOUT = 3.3
V
Output Voltage versus VIN
(New Chip)IN
VOUT = 3.3
V
VOUT = 3.3
V
VOUT = 3.3
V
VOUT = 3.3
V
VOUT = 3.3
V
VOUT = 3.3
V OUT
Dropout Voltage
versus Temperature (Legacy Chip)
Dropout Voltage
versus Temperature (Legacy Chip)
Dropout Voltage versus Temperature
(New Chip)
Dropout Voltage versus Temperature
(New Chip)
Dropout Voltage
versus Load Current (Legacy Chip)
Dropout Voltage
versus Load Current (Legacy Chip)
Dropout Voltage versus Load Current
(New Chip)
Dropout Voltage versus Load Current
(New Chip)
Ground Pin
Current versus Temperature (Legacy Chip)
Ground Pin
Current versus Temperature (Legacy Chip)
Ground Pin
Current versus Temperature (New Chip)
Ground Pin
Current versus Temperature (New Chip)
Ground Pin
Current versus Load Current (Legacy Chip)
Ground Pin
Current versus Load Current (Legacy Chip)
Ground Pin Current versus Load
Current (New Chip)
Ground Pin Current versus Load
Current (New Chip)
Input Current
versus VIN (Legacy Chip)
VOUT = 5
V
Input Current
versus VIN (Legacy Chip)IN
VOUT = 5
V
VOUT = 5
V
VOUT = 5
V
VOUT = 5
V
VOUT = 5
V
VOUT = 5
VOUT
Input Current
versus VIN (Legacy Chip)
VOUT = 5
V
Input Current
versus VIN (Legacy Chip)IN
VOUT = 5
V
VOUT = 5
V
VOUT = 5
V
VOUT = 5
V
VOUT = 5
V
VOUT = 5
VOUT
Input Current versus Input Voltage
(New Chip)
VOUT = 3.3 V
Input Current versus Input Voltage
(New Chip)
VOUT = 3.3 V
VOUT = 3.3 V
VOUT = 3.3 V
VOUT = 3.3 V
VOUT = 3.3 V
VOUT = 3.3 VOUT
Line Transient
Response (Legacy chip)
Line Transient
Response (Legacy chip)
Line Transient
Response (Legacy chip)
Line Transient
Response (Legacy chip)
Line Transient Response (New
Chip)
VOUT = 3.3 V, ΔVIN = 1 V, IOUT = 50 mA,
dV/dt = 1 V/μs
Line Transient Response (New
Chip)
VOUT = 3.3 V, ΔVIN = 1 V, IOUT = 50 mA,
dV/dt = 1 V/μs
VOUT = 3.3 V, ΔVIN = 1 V, IOUT = 50 mA,
dV/dt = 1 V/μs
VOUT = 3.3 V, ΔVIN = 1 V, IOUT = 50 mA,
dV/dt = 1 V/μs
VOUT = 3.3 V, ΔVIN = 1 V, IOUT = 50 mA,
dV/dt = 1 V/μs
VOUT = 3.3 V, ΔVIN = 1 V, IOUT = 50 mA,
dV/dt = 1 V/μs
VOUT = 3.3 V, ΔVIN = 1 V, IOUT = 50 mA,
dV/dt = 1 V/μsOUTINOUT
Load Transient
Response (Legacy chip)
Load Transient
Response (Legacy chip)
Load Transient
Response (Legacy chip)
Load Transient
Response (Legacy chip)
Load Transient
Response (Legacy chip)
Load Transient
Response (Legacy chip)
Load Transient
Response (Legacy chip)
Load Transient
Response (Legacy chip)
Load Transient Response (New
Chip)
dI/dt = 1 A/μs
Load Transient Response (New
Chip)
dI/dt = 1 A/μs
dI/dt = 1 A/μs
dI/dt = 1 A/μs
dI/dt = 1 A/μs
dI/dt = 1 A/μs
dI/dt = 1 A/μs
Short-Circuit
Current versus Time (Legacy chip)
VIN = 6
V
Short-Circuit
Current versus Time (Legacy chip)
VIN = 6
V
VIN = 6
V
VIN = 6
V
VIN = 6
V
VIN = 6
V
VIN = 6
VIN
Short-Circuit
Current versus Time (Legacy chip)
VIN = 16
V
Short-Circuit
Current versus Time (Legacy chip)
VIN = 16
V
VIN = 16
V
VIN = 16
V
VIN = 16
V
VIN = 16
V
VIN = 16
VIN
Short-Circuit Current versus Time
(New Chip)
VIN = 6 V
Short-Circuit Current versus Time
(New Chip)
VIN = 6 V
VIN = 6 V
VIN = 6 V
VIN = 6 V
VIN = 6 V
VIN = 6 VIN
Short-Circuit Current versus Time
(New Chip)
Short-Circuit Current versus Time
(New Chip)
Instantaneous
Short-Circuit Current versus Temperature (Legacy chip)
Instantaneous
Short-Circuit Current versus Temperature (Legacy chip)
Short-Circuit Current versus
Temperature (New Chip)
Short-Circuit Current versus
Temperature (New Chip)
Instantaneous
Short Circuit Current versus Output Voltage (Legacy chip)
Instantaneous
Short Circuit Current versus Output Voltage (Legacy chip)
Output
Impedance versus Frequency (Legacy chip)
Output
Impedance versus Frequency (Legacy chip)
Output
Impedance versus Frequency (Legacy chip)
Output
Impedance versus Frequency (Legacy chip)
ON/
OFF Pin Current versus VON/OFF (Legacy chip)
ON/
OFF Pin Current versus VON/OFF (Legacy chip)OFFON/OFF
ON/OFF Pin Current versus
VON/OFF
(New Chip)
VIN = 16
V
ON/OFF Pin Current versus
VON/OFF
(New Chip)OFFON/OFF
OFF
VIN = 16
V
VIN = 16
V
VIN = 16
V
VIN = 16
V
VIN = 16
V
VIN = 16
VIN
ON/OFF Pin Current versus
VON/OFF
(New Chip)
VIN = 4.3
V
ON/OFF Pin Current versus
VON/OFF
(New Chip)OFFON/OFF
OFF
VIN = 4.3
V
VIN = 4.3
V
VIN = 4.3
V
VIN = 4.3
V
VIN = 4.3
V
VIN = 4.3
VIN
ON/
OFF Threshold versus Temperature (Legacy chip)
ON/
OFF Threshold versus Temperature (Legacy chip)OFF
ON/
OFF Threshold versus Temperature (New chip)
ON/
OFF Threshold versus Temperature (New chip)OFF
Input-to-Output
Leakage versus Temperature (Legacy chip)
Input-to-Output
Leakage versus Temperature (Legacy chip)
Output Reverse
Leakage versus Temperature (Legacy chip)
Output Reverse
Leakage versus Temperature (Legacy chip)
Output Reverse
Leakage versus Temperature (New chip)
Output Reverse
Leakage versus Temperature (New chip)
Output Noise
Density (Legacy chip)
Output Noise
Density (Legacy chip)
Output Noise
Density (Legacy chip)
Output Noise
Density (Legacy chip)
Output Noise
Density (Legacy chip)
Output Noise
Density (Legacy chip)
Output Noise Density versus
Frequency (New Chip)
VIN = 4.3V, VOUT = 3.3V, COUT = 2.2μF
and ILOAD = 50 mA
Output Noise Density versus
Frequency (New Chip)
VIN = 4.3V, VOUT = 3.3V, COUT = 2.2μF
and ILOAD = 50 mA
VIN = 4.3V, VOUT = 3.3V, COUT = 2.2μF
and ILOAD = 50 mA
VIN = 4.3V, VOUT = 3.3V, COUT = 2.2μF
and ILOAD = 50 mA
VIN = 4.3V, VOUT = 3.3V, COUT = 2.2μF
and ILOAD = 50 mA
VIN = 4.3V, VOUT = 3.3V, COUT = 2.2μF
and ILOAD = 50 mA
VIN = 4.3V, VOUT = 3.3V, COUT = 2.2μF
and ILOAD = 50 mAINOUTOUTLOAD
Output Noise Density versus
Frequency for New Chip
VIN = 4.3V, VOUT = 3.3V, COUT = 2.2μF
and ILOAD = 1 mA
Output Noise Density versus
Frequency for New Chip
VIN = 4.3V, VOUT = 3.3V, COUT = 2.2μF
and ILOAD = 1 mA
VIN = 4.3V, VOUT = 3.3V, COUT = 2.2μF
and ILOAD = 1 mA
VIN = 4.3V, VOUT = 3.3V, COUT = 2.2μF
and ILOAD = 1 mA
VIN = 4.3V, VOUT = 3.3V, COUT = 2.2μF
and ILOAD = 1 mA
VIN = 4.3V, VOUT = 3.3V, COUT = 2.2μF
and ILOAD = 1 mA
VIN = 4.3V, VOUT = 3.3V, COUT = 2.2μF
and ILOAD = 1 mAINOUTOUTLOAD
Ripple
Rejection (Legacy chip)
Ripple
Rejection (Legacy chip)
Ripple Rejection versus IOUT
(New Chip)
VOUT = 3.3 V, Cbyp = 0 nF
Ripple Rejection versus IOUT
(New Chip)OUT
VOUT = 3.3 V, Cbyp = 0 nF
VOUT = 3.3 V, Cbyp = 0 nF
VOUT = 3.3 V, Cbyp = 0 nF
VOUT = 3.3 V, Cbyp = 0 nF
VOUT = 3.3 V, Cbyp = 0 nF
VOUT = 3.3 V, Cbyp = 0 nFOUTbyp
Ripple Rejection versus
IOUT (New Chip)
VOUT = 3.3 V, Cbyp = 10 nF
Ripple Rejection versus
IOUT (New Chip)OUT
VOUT = 3.3 V, Cbyp = 10 nF
VOUT = 3.3 V, Cbyp = 10 nF
VOUT = 3.3 V, Cbyp = 10 nF
VOUT = 3.3 V, Cbyp = 10 nF
VOUT = 3.3 V, Cbyp = 10 nF
VOUT = 3.3 V, Cbyp = 10 nFOUTbyp
Turnon Waveform
(Legacy chip)
Turnon Waveform
(Legacy chip)
Turnon Waveform
(Legacy chip)
Turnon Waveform
(Legacy chip)
Turnon Waveform
(Legacy chip)
Turnon Waveform
(Legacy chip)
Turnon Waveform (New chip)
Cbyp = 0 nF
Turnon Waveform (New chip)
Cbyp = 0 nF
Cbyp = 0 nF
Cbyp = 0 nF
Cbyp = 0 nF
Cbyp = 0 nF
Cbyp = 0 nFbyp
Turnon Waveform (New chip)
Cbyp = 0.1 nF
Turnon Waveform (New chip)
Cbyp = 0.1 nF
Cbyp = 0.1 nF
Cbyp = 0.1 nF
Cbyp = 0.1 nF
Cbyp = 0.1 nF
Cbyp = 0.1 nFbyp
Turnon Waveform (New chip)
Cbyp = 1 nF
Turnon Waveform (New chip)
Cbyp = 1 nF
Cbyp = 1 nF
Cbyp = 1 nF
Cbyp = 1 nF
Cbyp = 1 nF
Cbyp = 1 nFbyp
Detailed Description
Overview
The LP2982 is a fixed-output, low-noise,
high PSRR, low-dropout regulator that offers exceptional, cost-effective performance for
both portable and nonportable applications. The LP2982 has an output tolerance of 1% across
line, load, and temperature variation (for the new chip) and is capable of delivering 50 mA
of continuous load current.
This device features integrated overcurrent
protection, thermal shutdown, output enable, and internal output pulldown and has a built-in
soft-start mechanism for controlled inrush current. This device delivers excellent line and
load transient performance. The operating ambient temperature range of the device is –40°C
to +125°C.
Functional Block Diagram
Feature Description
Output Enable
The ON/OFF
pin for the device is an active-high pin. The output voltage is enabled when
the voltage of the ON/OFF pin is greater than the
high-level input voltage of the ON/OFF pin and disabled
with the ON/OFF pin voltage is less than the low-level
input voltage of the ON/OFF pin. If independent control
of the output voltage is not needed, connect the ON/OFF
pin to the input of the device.
The device has an internal
pulldown circuit that activates when the device is disabled by pulling the
ON/OFF pin voltage lower than the low-level input
voltage of the ON/OFF pin, to actively discharge the
output voltage.
Dropout Voltage
Dropout voltage (VDO)
is defined as the input voltage minus the output voltage (VIN –
VOUT) at the rated output current (IRATED),
where the pass transistor is fully on. IRATED is the maximum
IOUT listed in the
table.
The pass transistor is in the ohmic or triode region of operation, and acts
as a switch. The dropout voltage indirectly specifies a minimum input
voltage greater than the nominal programmed output voltage at which the
output voltage is expected to stay in regulation. If the input voltage falls
to less than the nominal output regulation, then the output voltage falls as
well.
For a
CMOS regulator, the dropout voltage is determined by the drain-source
on-state resistance (RDS(ON)) of the pass transistor. Therefore,
if the linear regulator operates at less than the rated current, the dropout
voltage for that current scales accordingly. The following equation
calculates the RDS(ON) of the device.
Current Limit
The device has an internal current
limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a brick-wall scheme. In a high-load current
fault, the brick-wall scheme limits the output current to the current limit
(ICL). ICL is listed in the
table.
The output voltage is not regulated
when the device is in current limit. When a current limit event occurs, the device
begins to heat up because of the increase in power dissipation. When the device is
in brick-wall current limit, the pass transistor dissipates power [(VIN –
VOUT) × ICL]. If thermal shutdown is triggered, the device
turns off. After the device cools down, the internal thermal shutdown circuit turns
the device back on. If the output current fault condition continues, the device
cycles between current limit and thermal shutdown. For more information on current
limits, see the
Know Your Limits application note.
shows a diagram
of the current limit.
Current
Limit
Undervoltage Lockout (UVLO)
The device has
an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing
a controlled and consistent turn on and off of the output voltage. To prevent the device
from turning off if the input drops during turn on, the UVLO has hysteresis as specified in
the
table.
Output Pulldown
Q
Added Output Pulldown section
yes
The new chip has an output
pulldown circuit. The output pulldown activates in the following
conditions:
When the device is disabled
(VON/OFF
<
VON/OFF(LOW))
If 1.0 V < VIN < VUVLO
Do not rely on the output
pulldown circuit for discharging a large amount of output capacitance after
the input supply has collapsed because reverse current can flow from the
output to the input. This reverse current flow can cause damage to the
device. See the
section for more details.
Thermal Shutdown
The device contains a thermal
shutdown protection circuit to disable the device when the junction
temperature (TJ) of the pass transistor rises to
TSD(shutdown) (typical). Thermal shutdown hysteresis
enables the device to reset (turns on) when the temperature falls to
TSD(reset) (typical). Thermal shutdown circuit limits are
defined in
section.
The thermal time-constant of the
semiconductor die is fairly short, thus the device can cycle on and off when
thermal shutdown is reached until power dissipation is reduced. Power
dissipation during start up can be high from large VIN –
VOUT voltage drops across the device or from high inrush
currents charging large output capacitors. Under some conditions, the
thermal shutdown protection disables the device before start up
completes.
For reliable operation, limit
the junction temperature to the maximum listed in the
table.
Operation above this maximum temperature causes the device to exceed
operational specifications. Although the internal protection circuitry of
the device is designed to protect against thermal overall conditions, this
circuitry is not intended to replace proper heat sinking. Continuously
running the device into thermal shutdown or above the maximum recommended
junction temperature reduces long-term reliability.
Device Functional Modes
Device Functional Mode Comparison
Device Functional Mode
Comparison
shows the conditions that lead to the different modes of
operation. See the
table for parameter values.
Device Functional Mode
Comparison
OPERATING MODE
PARAMETER
VIN
VON/OFF
IOUT
TJ
Normal operation
VIN >
VOUT(nom) + VDO and
VIN > VIN(min)
VON/OFF
>
VON/OFF(HI)
IOUT <
IOUT(max)
TJ <
TSD(shutdown)
Dropout operation
VIN(min) <
VIN < VOUT(nom) +
VDO
VON/OFF
>
VON/OFF(HI)
IOUT <
IOUT(max)
TJ <
TSD(shutdown)
Disabled
(any true condition disables the device)
VIN <
VUVLO
VON/OFF
<
VON/OFF(LOW)
Not applicable
TJ >
TSD(shutdown)
Normal Operation
The device regulates to the
nominal output voltage when the following conditions are met:
The input voltage is
greater than the nominal output voltage plus the dropout voltage
(VOUT(nom) + VDO)
The output current is
less than the current limit (IOUT < ICL)
The device junction
temperature is less than the thermal shutdown temperature
(TJ < TSD)
The
ON/OFF voltage has previously exceeded the
ON/OFF rising threshold voltage and has not
yet decreased to less than the enable falling threshold
Dropout Operation
If the input voltage is lower
than the nominal output voltage plus the specified dropout voltage, but all
other conditions are met for normal operation, the device operates in
dropout mode. In this mode, the output voltage tracks the input voltage.
During this mode, the transient performance of the device becomes
significantly degraded because the pass transistor is in the ohmic or triode
region, and acts as a switch. Line or load transients in dropout can result
in large output-voltage deviations.
When the device is in a steady
dropout state (defined as when the device is in dropout, VIN <
VOUT(NOM) + VDO, directly after being in a
normal regulation state, but not during start up), the pass
transistor is driven into the ohmic or triode region. When the input voltage
returns to a value greater than or equal to the nominal output voltage plus
the dropout voltage (VOUT(NOM) + VDO), the output
voltage can overshoot for a short period of time while the device pulls the
pass transistor back into the linear region.
Disabled
The output of
the device can be shutdown by forcing the voltage of the ON/OFF pin to
less than the maximum ON/OFF pin low-level input voltage (see the
table). When disabled,
the pass transistor is turned off, internal circuits are shutdown, and the output voltage is
actively discharged to ground by an internal discharge circuit from the output to
ground.
Detailed Description
Overview
The LP2982 is a fixed-output, low-noise,
high PSRR, low-dropout regulator that offers exceptional, cost-effective performance for
both portable and nonportable applications. The LP2982 has an output tolerance of 1% across
line, load, and temperature variation (for the new chip) and is capable of delivering 50 mA
of continuous load current.
This device features integrated overcurrent
protection, thermal shutdown, output enable, and internal output pulldown and has a built-in
soft-start mechanism for controlled inrush current. This device delivers excellent line and
load transient performance. The operating ambient temperature range of the device is –40°C
to +125°C.
Overview
The LP2982 is a fixed-output, low-noise,
high PSRR, low-dropout regulator that offers exceptional, cost-effective performance for
both portable and nonportable applications. The LP2982 has an output tolerance of 1% across
line, load, and temperature variation (for the new chip) and is capable of delivering 50 mA
of continuous load current.
This device features integrated overcurrent
protection, thermal shutdown, output enable, and internal output pulldown and has a built-in
soft-start mechanism for controlled inrush current. This device delivers excellent line and
load transient performance. The operating ambient temperature range of the device is –40°C
to +125°C.
The LP2982 is a fixed-output, low-noise,
high PSRR, low-dropout regulator that offers exceptional, cost-effective performance for
both portable and nonportable applications. The LP2982 has an output tolerance of 1% across
line, load, and temperature variation (for the new chip) and is capable of delivering 50 mA
of continuous load current.
This device features integrated overcurrent
protection, thermal shutdown, output enable, and internal output pulldown and has a built-in
soft-start mechanism for controlled inrush current. This device delivers excellent line and
load transient performance. The operating ambient temperature range of the device is –40°C
to +125°C.
The LP2982 is a fixed-output, low-noise,
high PSRR, low-dropout regulator that offers exceptional, cost-effective performance for
both portable and nonportable applications. The LP2982 has an output tolerance of 1% across
line, load, and temperature variation (for the new chip) and is capable of delivering 50 mA
of continuous load current.This device features integrated overcurrent
protection, thermal shutdown, output enable, and internal output pulldown and has a built-in
soft-start mechanism for controlled inrush current. This device delivers excellent line and
load transient performance. The operating ambient temperature range of the device is –40°C
to +125°C.
Functional Block Diagram
Functional Block Diagram
Feature Description
Output Enable
The ON/OFF
pin for the device is an active-high pin. The output voltage is enabled when
the voltage of the ON/OFF pin is greater than the
high-level input voltage of the ON/OFF pin and disabled
with the ON/OFF pin voltage is less than the low-level
input voltage of the ON/OFF pin. If independent control
of the output voltage is not needed, connect the ON/OFF
pin to the input of the device.
The device has an internal
pulldown circuit that activates when the device is disabled by pulling the
ON/OFF pin voltage lower than the low-level input
voltage of the ON/OFF pin, to actively discharge the
output voltage.
Dropout Voltage
Dropout voltage (VDO)
is defined as the input voltage minus the output voltage (VIN –
VOUT) at the rated output current (IRATED),
where the pass transistor is fully on. IRATED is the maximum
IOUT listed in the
table.
The pass transistor is in the ohmic or triode region of operation, and acts
as a switch. The dropout voltage indirectly specifies a minimum input
voltage greater than the nominal programmed output voltage at which the
output voltage is expected to stay in regulation. If the input voltage falls
to less than the nominal output regulation, then the output voltage falls as
well.
For a
CMOS regulator, the dropout voltage is determined by the drain-source
on-state resistance (RDS(ON)) of the pass transistor. Therefore,
if the linear regulator operates at less than the rated current, the dropout
voltage for that current scales accordingly. The following equation
calculates the RDS(ON) of the device.
Current Limit
The device has an internal current
limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a brick-wall scheme. In a high-load current
fault, the brick-wall scheme limits the output current to the current limit
(ICL). ICL is listed in the
table.
The output voltage is not regulated
when the device is in current limit. When a current limit event occurs, the device
begins to heat up because of the increase in power dissipation. When the device is
in brick-wall current limit, the pass transistor dissipates power [(VIN –
VOUT) × ICL]. If thermal shutdown is triggered, the device
turns off. After the device cools down, the internal thermal shutdown circuit turns
the device back on. If the output current fault condition continues, the device
cycles between current limit and thermal shutdown. For more information on current
limits, see the
Know Your Limits application note.
shows a diagram
of the current limit.
Current
Limit
Undervoltage Lockout (UVLO)
The device has
an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing
a controlled and consistent turn on and off of the output voltage. To prevent the device
from turning off if the input drops during turn on, the UVLO has hysteresis as specified in
the
table.
Output Pulldown
Q
Added Output Pulldown section
yes
The new chip has an output
pulldown circuit. The output pulldown activates in the following
conditions:
When the device is disabled
(VON/OFF
<
VON/OFF(LOW))
If 1.0 V < VIN < VUVLO
Do not rely on the output
pulldown circuit for discharging a large amount of output capacitance after
the input supply has collapsed because reverse current can flow from the
output to the input. This reverse current flow can cause damage to the
device. See the
section for more details.
Thermal Shutdown
The device contains a thermal
shutdown protection circuit to disable the device when the junction
temperature (TJ) of the pass transistor rises to
TSD(shutdown) (typical). Thermal shutdown hysteresis
enables the device to reset (turns on) when the temperature falls to
TSD(reset) (typical). Thermal shutdown circuit limits are
defined in
section.
The thermal time-constant of the
semiconductor die is fairly short, thus the device can cycle on and off when
thermal shutdown is reached until power dissipation is reduced. Power
dissipation during start up can be high from large VIN –
VOUT voltage drops across the device or from high inrush
currents charging large output capacitors. Under some conditions, the
thermal shutdown protection disables the device before start up
completes.
For reliable operation, limit
the junction temperature to the maximum listed in the
table.
Operation above this maximum temperature causes the device to exceed
operational specifications. Although the internal protection circuitry of
the device is designed to protect against thermal overall conditions, this
circuitry is not intended to replace proper heat sinking. Continuously
running the device into thermal shutdown or above the maximum recommended
junction temperature reduces long-term reliability.
Feature Description
Output Enable
The ON/OFF
pin for the device is an active-high pin. The output voltage is enabled when
the voltage of the ON/OFF pin is greater than the
high-level input voltage of the ON/OFF pin and disabled
with the ON/OFF pin voltage is less than the low-level
input voltage of the ON/OFF pin. If independent control
of the output voltage is not needed, connect the ON/OFF
pin to the input of the device.
The device has an internal
pulldown circuit that activates when the device is disabled by pulling the
ON/OFF pin voltage lower than the low-level input
voltage of the ON/OFF pin, to actively discharge the
output voltage.
Output Enable
The ON/OFF
pin for the device is an active-high pin. The output voltage is enabled when
the voltage of the ON/OFF pin is greater than the
high-level input voltage of the ON/OFF pin and disabled
with the ON/OFF pin voltage is less than the low-level
input voltage of the ON/OFF pin. If independent control
of the output voltage is not needed, connect the ON/OFF
pin to the input of the device.
The device has an internal
pulldown circuit that activates when the device is disabled by pulling the
ON/OFF pin voltage lower than the low-level input
voltage of the ON/OFF pin, to actively discharge the
output voltage.
The ON/OFF
pin for the device is an active-high pin. The output voltage is enabled when
the voltage of the ON/OFF pin is greater than the
high-level input voltage of the ON/OFF pin and disabled
with the ON/OFF pin voltage is less than the low-level
input voltage of the ON/OFF pin. If independent control
of the output voltage is not needed, connect the ON/OFF
pin to the input of the device.
The device has an internal
pulldown circuit that activates when the device is disabled by pulling the
ON/OFF pin voltage lower than the low-level input
voltage of the ON/OFF pin, to actively discharge the
output voltage.
The ON/OFF
pin for the device is an active-high pin. The output voltage is enabled when
the voltage of the ON/OFF pin is greater than the
high-level input voltage of the ON/OFF pin and disabled
with the ON/OFF pin voltage is less than the low-level
input voltage of the ON/OFF pin. If independent control
of the output voltage is not needed, connect the ON/OFF
pin to the input of the device.OFFOFFOFFOFFOFFOFFThe device has an internal
pulldown circuit that activates when the device is disabled by pulling the
ON/OFF pin voltage lower than the low-level input
voltage of the ON/OFF pin, to actively discharge the
output voltage.OFFOFF
Dropout Voltage
Dropout voltage (VDO)
is defined as the input voltage minus the output voltage (VIN –
VOUT) at the rated output current (IRATED),
where the pass transistor is fully on. IRATED is the maximum
IOUT listed in the
table.
The pass transistor is in the ohmic or triode region of operation, and acts
as a switch. The dropout voltage indirectly specifies a minimum input
voltage greater than the nominal programmed output voltage at which the
output voltage is expected to stay in regulation. If the input voltage falls
to less than the nominal output regulation, then the output voltage falls as
well.
For a
CMOS regulator, the dropout voltage is determined by the drain-source
on-state resistance (RDS(ON)) of the pass transistor. Therefore,
if the linear regulator operates at less than the rated current, the dropout
voltage for that current scales accordingly. The following equation
calculates the RDS(ON) of the device.
Dropout Voltage
Dropout voltage (VDO)
is defined as the input voltage minus the output voltage (VIN –
VOUT) at the rated output current (IRATED),
where the pass transistor is fully on. IRATED is the maximum
IOUT listed in the
table.
The pass transistor is in the ohmic or triode region of operation, and acts
as a switch. The dropout voltage indirectly specifies a minimum input
voltage greater than the nominal programmed output voltage at which the
output voltage is expected to stay in regulation. If the input voltage falls
to less than the nominal output regulation, then the output voltage falls as
well.
For a
CMOS regulator, the dropout voltage is determined by the drain-source
on-state resistance (RDS(ON)) of the pass transistor. Therefore,
if the linear regulator operates at less than the rated current, the dropout
voltage for that current scales accordingly. The following equation
calculates the RDS(ON) of the device.
Dropout voltage (VDO)
is defined as the input voltage minus the output voltage (VIN –
VOUT) at the rated output current (IRATED),
where the pass transistor is fully on. IRATED is the maximum
IOUT listed in the
table.
The pass transistor is in the ohmic or triode region of operation, and acts
as a switch. The dropout voltage indirectly specifies a minimum input
voltage greater than the nominal programmed output voltage at which the
output voltage is expected to stay in regulation. If the input voltage falls
to less than the nominal output regulation, then the output voltage falls as
well.
For a
CMOS regulator, the dropout voltage is determined by the drain-source
on-state resistance (RDS(ON)) of the pass transistor. Therefore,
if the linear regulator operates at less than the rated current, the dropout
voltage for that current scales accordingly. The following equation
calculates the RDS(ON) of the device.
Dropout voltage (VDO)
is defined as the input voltage minus the output voltage (VIN –
VOUT) at the rated output current (IRATED),
where the pass transistor is fully on. IRATED is the maximum
IOUT listed in the
table.
The pass transistor is in the ohmic or triode region of operation, and acts
as a switch. The dropout voltage indirectly specifies a minimum input
voltage greater than the nominal programmed output voltage at which the
output voltage is expected to stay in regulation. If the input voltage falls
to less than the nominal output regulation, then the output voltage falls as
well.DOINOUTRATEDRATEDOUT
For a
CMOS regulator, the dropout voltage is determined by the drain-source
on-state resistance (RDS(ON)) of the pass transistor. Therefore,
if the linear regulator operates at less than the rated current, the dropout
voltage for that current scales accordingly. The following equation
calculates the RDS(ON) of the device.DS(ON)DS(ON)
Current Limit
The device has an internal current
limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a brick-wall scheme. In a high-load current
fault, the brick-wall scheme limits the output current to the current limit
(ICL). ICL is listed in the
table.
The output voltage is not regulated
when the device is in current limit. When a current limit event occurs, the device
begins to heat up because of the increase in power dissipation. When the device is
in brick-wall current limit, the pass transistor dissipates power [(VIN –
VOUT) × ICL]. If thermal shutdown is triggered, the device
turns off. After the device cools down, the internal thermal shutdown circuit turns
the device back on. If the output current fault condition continues, the device
cycles between current limit and thermal shutdown. For more information on current
limits, see the
Know Your Limits application note.
shows a diagram
of the current limit.
Current
Limit
Current Limit
The device has an internal current
limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a brick-wall scheme. In a high-load current
fault, the brick-wall scheme limits the output current to the current limit
(ICL). ICL is listed in the
table.
The output voltage is not regulated
when the device is in current limit. When a current limit event occurs, the device
begins to heat up because of the increase in power dissipation. When the device is
in brick-wall current limit, the pass transistor dissipates power [(VIN –
VOUT) × ICL]. If thermal shutdown is triggered, the device
turns off. After the device cools down, the internal thermal shutdown circuit turns
the device back on. If the output current fault condition continues, the device
cycles between current limit and thermal shutdown. For more information on current
limits, see the
Know Your Limits application note.
shows a diagram
of the current limit.
Current
Limit
The device has an internal current
limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a brick-wall scheme. In a high-load current
fault, the brick-wall scheme limits the output current to the current limit
(ICL). ICL is listed in the
table.
The output voltage is not regulated
when the device is in current limit. When a current limit event occurs, the device
begins to heat up because of the increase in power dissipation. When the device is
in brick-wall current limit, the pass transistor dissipates power [(VIN –
VOUT) × ICL]. If thermal shutdown is triggered, the device
turns off. After the device cools down, the internal thermal shutdown circuit turns
the device back on. If the output current fault condition continues, the device
cycles between current limit and thermal shutdown. For more information on current
limits, see the
Know Your Limits application note.
shows a diagram
of the current limit.
Current
Limit
The device has an internal current
limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a brick-wall scheme. In a high-load current
fault, the brick-wall scheme limits the output current to the current limit
(ICL). ICL is listed in the
table.CLCL
The output voltage is not regulated
when the device is in current limit. When a current limit event occurs, the device
begins to heat up because of the increase in power dissipation. When the device is
in brick-wall current limit, the pass transistor dissipates power [(VIN –
VOUT) × ICL]. If thermal shutdown is triggered, the device
turns off. After the device cools down, the internal thermal shutdown circuit turns
the device back on. If the output current fault condition continues, the device
cycles between current limit and thermal shutdown. For more information on current
limits, see the
Know Your Limits application note.INOUTCL
Know Your Limits application noteKnow Your Limits
shows a diagram
of the current limit.
Current
Limit
Current
Limit
Undervoltage Lockout (UVLO)
The device has
an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing
a controlled and consistent turn on and off of the output voltage. To prevent the device
from turning off if the input drops during turn on, the UVLO has hysteresis as specified in
the
table.
Undervoltage Lockout (UVLO)
The device has
an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing
a controlled and consistent turn on and off of the output voltage. To prevent the device
from turning off if the input drops during turn on, the UVLO has hysteresis as specified in
the
table.
The device has
an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing
a controlled and consistent turn on and off of the output voltage. To prevent the device
from turning off if the input drops during turn on, the UVLO has hysteresis as specified in
the
table.
The device has
an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing
a controlled and consistent turn on and off of the output voltage. To prevent the device
from turning off if the input drops during turn on, the UVLO has hysteresis as specified in
the
table.
Output Pulldown
Q
Added Output Pulldown section
yes
The new chip has an output
pulldown circuit. The output pulldown activates in the following
conditions:
When the device is disabled
(VON/OFF
<
VON/OFF(LOW))
If 1.0 V < VIN < VUVLO
Do not rely on the output
pulldown circuit for discharging a large amount of output capacitance after
the input supply has collapsed because reverse current can flow from the
output to the input. This reverse current flow can cause damage to the
device. See the
section for more details.
Output Pulldown
Q
Added Output Pulldown section
yes
Q
Added Output Pulldown section
yes
Q
Added Output Pulldown section
yes
QAdded Output Pulldown sectionOutput Pulldownyes
The new chip has an output
pulldown circuit. The output pulldown activates in the following
conditions:
When the device is disabled
(VON/OFF
<
VON/OFF(LOW))
If 1.0 V < VIN < VUVLO
Do not rely on the output
pulldown circuit for discharging a large amount of output capacitance after
the input supply has collapsed because reverse current can flow from the
output to the input. This reverse current flow can cause damage to the
device. See the
section for more details.
The new chip has an output
pulldown circuit. The output pulldown activates in the following
conditions:
When the device is disabled
(VON/OFF
<
VON/OFF(LOW))
If 1.0 V < VIN < VUVLO
Do not rely on the output
pulldown circuit for discharging a large amount of output capacitance after
the input supply has collapsed because reverse current can flow from the
output to the input. This reverse current flow can cause damage to the
device. See the
section for more details.
The new chip has an output
pulldown circuit. The output pulldown activates in the following
conditions:
When the device is disabled
(VON/OFF
<
VON/OFF(LOW))
If 1.0 V < VIN < VUVLO
When the device is disabled
(VON/OFF
<
VON/OFF(LOW))ON/OFF
OFFON/OFF(LOW)OFFIf 1.0 V < VIN < VUVLO
INUVLODo not rely on the output
pulldown circuit for discharging a large amount of output capacitance after
the input supply has collapsed because reverse current can flow from the
output to the input. This reverse current flow can cause damage to the
device. See the
section for more details.
Thermal Shutdown
The device contains a thermal
shutdown protection circuit to disable the device when the junction
temperature (TJ) of the pass transistor rises to
TSD(shutdown) (typical). Thermal shutdown hysteresis
enables the device to reset (turns on) when the temperature falls to
TSD(reset) (typical). Thermal shutdown circuit limits are
defined in
section.
The thermal time-constant of the
semiconductor die is fairly short, thus the device can cycle on and off when
thermal shutdown is reached until power dissipation is reduced. Power
dissipation during start up can be high from large VIN –
VOUT voltage drops across the device or from high inrush
currents charging large output capacitors. Under some conditions, the
thermal shutdown protection disables the device before start up
completes.
For reliable operation, limit
the junction temperature to the maximum listed in the
table.
Operation above this maximum temperature causes the device to exceed
operational specifications. Although the internal protection circuitry of
the device is designed to protect against thermal overall conditions, this
circuitry is not intended to replace proper heat sinking. Continuously
running the device into thermal shutdown or above the maximum recommended
junction temperature reduces long-term reliability.
Thermal Shutdown
The device contains a thermal
shutdown protection circuit to disable the device when the junction
temperature (TJ) of the pass transistor rises to
TSD(shutdown) (typical). Thermal shutdown hysteresis
enables the device to reset (turns on) when the temperature falls to
TSD(reset) (typical). Thermal shutdown circuit limits are
defined in
section.
The thermal time-constant of the
semiconductor die is fairly short, thus the device can cycle on and off when
thermal shutdown is reached until power dissipation is reduced. Power
dissipation during start up can be high from large VIN –
VOUT voltage drops across the device or from high inrush
currents charging large output capacitors. Under some conditions, the
thermal shutdown protection disables the device before start up
completes.
For reliable operation, limit
the junction temperature to the maximum listed in the
table.
Operation above this maximum temperature causes the device to exceed
operational specifications. Although the internal protection circuitry of
the device is designed to protect against thermal overall conditions, this
circuitry is not intended to replace proper heat sinking. Continuously
running the device into thermal shutdown or above the maximum recommended
junction temperature reduces long-term reliability.
The device contains a thermal
shutdown protection circuit to disable the device when the junction
temperature (TJ) of the pass transistor rises to
TSD(shutdown) (typical). Thermal shutdown hysteresis
enables the device to reset (turns on) when the temperature falls to
TSD(reset) (typical). Thermal shutdown circuit limits are
defined in
section.
The thermal time-constant of the
semiconductor die is fairly short, thus the device can cycle on and off when
thermal shutdown is reached until power dissipation is reduced. Power
dissipation during start up can be high from large VIN –
VOUT voltage drops across the device or from high inrush
currents charging large output capacitors. Under some conditions, the
thermal shutdown protection disables the device before start up
completes.
For reliable operation, limit
the junction temperature to the maximum listed in the
table.
Operation above this maximum temperature causes the device to exceed
operational specifications. Although the internal protection circuitry of
the device is designed to protect against thermal overall conditions, this
circuitry is not intended to replace proper heat sinking. Continuously
running the device into thermal shutdown or above the maximum recommended
junction temperature reduces long-term reliability.
The device contains a thermal
shutdown protection circuit to disable the device when the junction
temperature (TJ) of the pass transistor rises to
TSD(shutdown) (typical). Thermal shutdown hysteresis
enables the device to reset (turns on) when the temperature falls to
TSD(reset) (typical). Thermal shutdown circuit limits are
defined in
section.JSD(shutdown)SD(reset)
The thermal time-constant of the
semiconductor die is fairly short, thus the device can cycle on and off when
thermal shutdown is reached until power dissipation is reduced. Power
dissipation during start up can be high from large VIN –
VOUT voltage drops across the device or from high inrush
currents charging large output capacitors. Under some conditions, the
thermal shutdown protection disables the device before start up
completes.INOUTFor reliable operation, limit
the junction temperature to the maximum listed in the
table.
Operation above this maximum temperature causes the device to exceed
operational specifications. Although the internal protection circuitry of
the device is designed to protect against thermal overall conditions, this
circuitry is not intended to replace proper heat sinking. Continuously
running the device into thermal shutdown or above the maximum recommended
junction temperature reduces long-term reliability.
Device Functional Modes
Device Functional Mode Comparison
Device Functional Mode
Comparison
shows the conditions that lead to the different modes of
operation. See the
table for parameter values.
Device Functional Mode
Comparison
OPERATING MODE
PARAMETER
VIN
VON/OFF
IOUT
TJ
Normal operation
VIN >
VOUT(nom) + VDO and
VIN > VIN(min)
VON/OFF
>
VON/OFF(HI)
IOUT <
IOUT(max)
TJ <
TSD(shutdown)
Dropout operation
VIN(min) <
VIN < VOUT(nom) +
VDO
VON/OFF
>
VON/OFF(HI)
IOUT <
IOUT(max)
TJ <
TSD(shutdown)
Disabled
(any true condition disables the device)
VIN <
VUVLO
VON/OFF
<
VON/OFF(LOW)
Not applicable
TJ >
TSD(shutdown)
Normal Operation
The device regulates to the
nominal output voltage when the following conditions are met:
The input voltage is
greater than the nominal output voltage plus the dropout voltage
(VOUT(nom) + VDO)
The output current is
less than the current limit (IOUT < ICL)
The device junction
temperature is less than the thermal shutdown temperature
(TJ < TSD)
The
ON/OFF voltage has previously exceeded the
ON/OFF rising threshold voltage and has not
yet decreased to less than the enable falling threshold
Dropout Operation
If the input voltage is lower
than the nominal output voltage plus the specified dropout voltage, but all
other conditions are met for normal operation, the device operates in
dropout mode. In this mode, the output voltage tracks the input voltage.
During this mode, the transient performance of the device becomes
significantly degraded because the pass transistor is in the ohmic or triode
region, and acts as a switch. Line or load transients in dropout can result
in large output-voltage deviations.
When the device is in a steady
dropout state (defined as when the device is in dropout, VIN <
VOUT(NOM) + VDO, directly after being in a
normal regulation state, but not during start up), the pass
transistor is driven into the ohmic or triode region. When the input voltage
returns to a value greater than or equal to the nominal output voltage plus
the dropout voltage (VOUT(NOM) + VDO), the output
voltage can overshoot for a short period of time while the device pulls the
pass transistor back into the linear region.
Disabled
The output of
the device can be shutdown by forcing the voltage of the ON/OFF pin to
less than the maximum ON/OFF pin low-level input voltage (see the
table). When disabled,
the pass transistor is turned off, internal circuits are shutdown, and the output voltage is
actively discharged to ground by an internal discharge circuit from the output to
ground.
Device Functional Modes
Device Functional Mode Comparison
Device Functional Mode
Comparison
shows the conditions that lead to the different modes of
operation. See the
table for parameter values.
Device Functional Mode
Comparison
OPERATING MODE
PARAMETER
VIN
VON/OFF
IOUT
TJ
Normal operation
VIN >
VOUT(nom) + VDO and
VIN > VIN(min)
VON/OFF
>
VON/OFF(HI)
IOUT <
IOUT(max)
TJ <
TSD(shutdown)
Dropout operation
VIN(min) <
VIN < VOUT(nom) +
VDO
VON/OFF
>
VON/OFF(HI)
IOUT <
IOUT(max)
TJ <
TSD(shutdown)
Disabled
(any true condition disables the device)
VIN <
VUVLO
VON/OFF
<
VON/OFF(LOW)
Not applicable
TJ >
TSD(shutdown)
Device Functional Mode Comparison
Device Functional Mode
Comparison
shows the conditions that lead to the different modes of
operation. See the
table for parameter values.
Device Functional Mode
Comparison
OPERATING MODE
PARAMETER
VIN
VON/OFF
IOUT
TJ
Normal operation
VIN >
VOUT(nom) + VDO and
VIN > VIN(min)
VON/OFF
>
VON/OFF(HI)
IOUT <
IOUT(max)
TJ <
TSD(shutdown)
Dropout operation
VIN(min) <
VIN < VOUT(nom) +
VDO
VON/OFF
>
VON/OFF(HI)
IOUT <
IOUT(max)
TJ <
TSD(shutdown)
Disabled
(any true condition disables the device)
VIN <
VUVLO
VON/OFF
<
VON/OFF(LOW)
Not applicable
TJ >
TSD(shutdown)
Device Functional Mode
Comparison
shows the conditions that lead to the different modes of
operation. See the
table for parameter values.
Device Functional Mode
Comparison
OPERATING MODE
PARAMETER
VIN
VON/OFF
IOUT
TJ
Normal operation
VIN >
VOUT(nom) + VDO and
VIN > VIN(min)
VON/OFF
>
VON/OFF(HI)
IOUT <
IOUT(max)
TJ <
TSD(shutdown)
Dropout operation
VIN(min) <
VIN < VOUT(nom) +
VDO
VON/OFF
>
VON/OFF(HI)
IOUT <
IOUT(max)
TJ <
TSD(shutdown)
Disabled
(any true condition disables the device)
VIN <
VUVLO
VON/OFF
<
VON/OFF(LOW)
Not applicable
TJ >
TSD(shutdown)
Device Functional Mode
Comparison
shows the conditions that lead to the different modes of
operation. See the
table for parameter values.
Device Functional Mode
Comparison
Device Functional Mode
Comparison
Device Functional Mode
Comparison
Device Functional Mode
Comparison
OPERATING MODE
PARAMETER
VIN
VON/OFF
IOUT
TJ
Normal operation
VIN >
VOUT(nom) + VDO and
VIN > VIN(min)
VON/OFF
>
VON/OFF(HI)
IOUT <
IOUT(max)
TJ <
TSD(shutdown)
Dropout operation
VIN(min) <
VIN < VOUT(nom) +
VDO
VON/OFF
>
VON/OFF(HI)
IOUT <
IOUT(max)
TJ <
TSD(shutdown)
Disabled
(any true condition disables the device)
VIN <
VUVLO
VON/OFF
<
VON/OFF(LOW)
Not applicable
TJ >
TSD(shutdown)
Device Functional Mode
Comparison
OPERATING MODE
PARAMETER
VIN
VON/OFF
IOUT
TJ
Normal operation
VIN >
VOUT(nom) + VDO and
VIN > VIN(min)
VON/OFF
>
VON/OFF(HI)
IOUT <
IOUT(max)
TJ <
TSD(shutdown)
Dropout operation
VIN(min) <
VIN < VOUT(nom) +
VDO
VON/OFF
>
VON/OFF(HI)
IOUT <
IOUT(max)
TJ <
TSD(shutdown)
Disabled
(any true condition disables the device)
VIN <
VUVLO
VON/OFF
<
VON/OFF(LOW)
Not applicable
TJ >
TSD(shutdown)
OPERATING MODE
PARAMETER
VIN
VON/OFF
IOUT
TJ
OPERATING MODE
PARAMETER
OPERATING MODEPARAMETER
VIN
VON/OFF
IOUT
TJ
VIN
INVON/OFF
ON/OFF
OFFIOUT
OUTTJ
J
Normal operation
VIN >
VOUT(nom) + VDO and
VIN > VIN(min)
VON/OFF
>
VON/OFF(HI)
IOUT <
IOUT(max)
TJ <
TSD(shutdown)
Dropout operation
VIN(min) <
VIN < VOUT(nom) +
VDO
VON/OFF
>
VON/OFF(HI)
IOUT <
IOUT(max)
TJ <
TSD(shutdown)
Disabled
(any true condition disables the device)
VIN <
VUVLO
VON/OFF
<
VON/OFF(LOW)
Not applicable
TJ >
TSD(shutdown)
Normal operation
VIN >
VOUT(nom) + VDO and
VIN > VIN(min)
VON/OFF
>
VON/OFF(HI)
IOUT <
IOUT(max)
TJ <
TSD(shutdown)
Normal operationVIN >
VOUT(nom) + VDO and
VIN > VIN(min)
INOUT(nom)DOININ(min)VON/OFF
>
VON/OFF(HI)
ON/OFF
OFFON/OFF(HI)OFFIOUT <
IOUT(max)
OUTOUT(max)TJ <
TSD(shutdown)
JSD(shutdown)
Dropout operation
VIN(min) <
VIN < VOUT(nom) +
VDO
VON/OFF
>
VON/OFF(HI)
IOUT <
IOUT(max)
TJ <
TSD(shutdown)
Dropout operationVIN(min) <
VIN < VOUT(nom) +
VDO
IN(min)INOUT(nom)DOVON/OFF
>
VON/OFF(HI)
ON/OFF
OFFON/OFF(HI)OFFIOUT <
IOUT(max)
OUTOUT(max)TJ <
TSD(shutdown)
JSD(shutdown)
Disabled
(any true condition disables the device)
VIN <
VUVLO
VON/OFF
<
VON/OFF(LOW)
Not applicable
TJ >
TSD(shutdown)
Disabled
(any true condition disables the device)VIN <
VUVLO
INUVLOVON/OFF
<
VON/OFF(LOW)
ON/OFF
OFFON/OFF(LOW)OFFNot applicableTJ >
TSD(shutdown)
JSD(shutdown)
Normal Operation
The device regulates to the
nominal output voltage when the following conditions are met:
The input voltage is
greater than the nominal output voltage plus the dropout voltage
(VOUT(nom) + VDO)
The output current is
less than the current limit (IOUT < ICL)
The device junction
temperature is less than the thermal shutdown temperature
(TJ < TSD)
The
ON/OFF voltage has previously exceeded the
ON/OFF rising threshold voltage and has not
yet decreased to less than the enable falling threshold
Normal Operation
The device regulates to the
nominal output voltage when the following conditions are met:
The input voltage is
greater than the nominal output voltage plus the dropout voltage
(VOUT(nom) + VDO)
The output current is
less than the current limit (IOUT < ICL)
The device junction
temperature is less than the thermal shutdown temperature
(TJ < TSD)
The
ON/OFF voltage has previously exceeded the
ON/OFF rising threshold voltage and has not
yet decreased to less than the enable falling threshold
The device regulates to the
nominal output voltage when the following conditions are met:
The input voltage is
greater than the nominal output voltage plus the dropout voltage
(VOUT(nom) + VDO)
The output current is
less than the current limit (IOUT < ICL)
The device junction
temperature is less than the thermal shutdown temperature
(TJ < TSD)
The
ON/OFF voltage has previously exceeded the
ON/OFF rising threshold voltage and has not
yet decreased to less than the enable falling threshold
The device regulates to the
nominal output voltage when the following conditions are met:
The input voltage is
greater than the nominal output voltage plus the dropout voltage
(VOUT(nom) + VDO)
The output current is
less than the current limit (IOUT < ICL)
The device junction
temperature is less than the thermal shutdown temperature
(TJ < TSD)
The
ON/OFF voltage has previously exceeded the
ON/OFF rising threshold voltage and has not
yet decreased to less than the enable falling threshold
The input voltage is
greater than the nominal output voltage plus the dropout voltage
(VOUT(nom) + VDO)OUT(nom)DOThe output current is
less than the current limit (IOUT < ICL)OUTCLThe device junction
temperature is less than the thermal shutdown temperature
(TJ < TSD)JSDThe
ON/OFF voltage has previously exceeded the
ON/OFF rising threshold voltage and has not
yet decreased to less than the enable falling thresholdOFFOFF
Dropout Operation
If the input voltage is lower
than the nominal output voltage plus the specified dropout voltage, but all
other conditions are met for normal operation, the device operates in
dropout mode. In this mode, the output voltage tracks the input voltage.
During this mode, the transient performance of the device becomes
significantly degraded because the pass transistor is in the ohmic or triode
region, and acts as a switch. Line or load transients in dropout can result
in large output-voltage deviations.
When the device is in a steady
dropout state (defined as when the device is in dropout, VIN <
VOUT(NOM) + VDO, directly after being in a
normal regulation state, but not during start up), the pass
transistor is driven into the ohmic or triode region. When the input voltage
returns to a value greater than or equal to the nominal output voltage plus
the dropout voltage (VOUT(NOM) + VDO), the output
voltage can overshoot for a short period of time while the device pulls the
pass transistor back into the linear region.
Dropout Operation
If the input voltage is lower
than the nominal output voltage plus the specified dropout voltage, but all
other conditions are met for normal operation, the device operates in
dropout mode. In this mode, the output voltage tracks the input voltage.
During this mode, the transient performance of the device becomes
significantly degraded because the pass transistor is in the ohmic or triode
region, and acts as a switch. Line or load transients in dropout can result
in large output-voltage deviations.
When the device is in a steady
dropout state (defined as when the device is in dropout, VIN <
VOUT(NOM) + VDO, directly after being in a
normal regulation state, but not during start up), the pass
transistor is driven into the ohmic or triode region. When the input voltage
returns to a value greater than or equal to the nominal output voltage plus
the dropout voltage (VOUT(NOM) + VDO), the output
voltage can overshoot for a short period of time while the device pulls the
pass transistor back into the linear region.
If the input voltage is lower
than the nominal output voltage plus the specified dropout voltage, but all
other conditions are met for normal operation, the device operates in
dropout mode. In this mode, the output voltage tracks the input voltage.
During this mode, the transient performance of the device becomes
significantly degraded because the pass transistor is in the ohmic or triode
region, and acts as a switch. Line or load transients in dropout can result
in large output-voltage deviations.
When the device is in a steady
dropout state (defined as when the device is in dropout, VIN <
VOUT(NOM) + VDO, directly after being in a
normal regulation state, but not during start up), the pass
transistor is driven into the ohmic or triode region. When the input voltage
returns to a value greater than or equal to the nominal output voltage plus
the dropout voltage (VOUT(NOM) + VDO), the output
voltage can overshoot for a short period of time while the device pulls the
pass transistor back into the linear region.
If the input voltage is lower
than the nominal output voltage plus the specified dropout voltage, but all
other conditions are met for normal operation, the device operates in
dropout mode. In this mode, the output voltage tracks the input voltage.
During this mode, the transient performance of the device becomes
significantly degraded because the pass transistor is in the ohmic or triode
region, and acts as a switch. Line or load transients in dropout can result
in large output-voltage deviations.When the device is in a steady
dropout state (defined as when the device is in dropout, VIN <
VOUT(NOM) + VDO, directly after being in a
normal regulation state, but not during start up), the pass
transistor is driven into the ohmic or triode region. When the input voltage
returns to a value greater than or equal to the nominal output voltage plus
the dropout voltage (VOUT(NOM) + VDO), the output
voltage can overshoot for a short period of time while the device pulls the
pass transistor back into the linear region.INOUT(NOM)DOnotOUT(NOM)DO
Disabled
The output of
the device can be shutdown by forcing the voltage of the ON/OFF pin to
less than the maximum ON/OFF pin low-level input voltage (see the
table). When disabled,
the pass transistor is turned off, internal circuits are shutdown, and the output voltage is
actively discharged to ground by an internal discharge circuit from the output to
ground.
Disabled
The output of
the device can be shutdown by forcing the voltage of the ON/OFF pin to
less than the maximum ON/OFF pin low-level input voltage (see the
table). When disabled,
the pass transistor is turned off, internal circuits are shutdown, and the output voltage is
actively discharged to ground by an internal discharge circuit from the output to
ground.
The output of
the device can be shutdown by forcing the voltage of the ON/OFF pin to
less than the maximum ON/OFF pin low-level input voltage (see the
table). When disabled,
the pass transistor is turned off, internal circuits are shutdown, and the output voltage is
actively discharged to ground by an internal discharge circuit from the output to
ground.
The output of
the device can be shutdown by forcing the voltage of the ON/OFF pin to
less than the maximum ON/OFF pin low-level input voltage (see the
table). When disabled,
the pass transistor is turned off, internal circuits are shutdown, and the output voltage is
actively discharged to ground by an internal discharge circuit from the output to
ground.OFFOFF
Application and Implementation
Information in the following applications sections is not part of the TI
component specification, and TI does not warrant its accuracy or completeness.
TI’s customers are responsible for determining suitability of components for
their purposes, as well as validating and testing their design implementation to
confirm system functionality.
Application Information
The LP2982 is a linear voltage regulator operating from 2.5 V to 16 V (for new chip)
on the input and regulates voltages between 1.2 V to 5 V with ±1% accuracy (across
line, load and temperature) and 50-mA maximum output current.
Successfully implementing an LDO in an
application depends on the application requirements. If the requirements are simply
input voltage and output voltage, compliance specifications (such as internal power
dissipation or stability) must be verified for a solid design. If timing, start-up,
noise, power supply rejection ratio (PSRR), or any other transient specification is
required, then the design becomes more challenging.
Recommended Capacitor Types
F
Added Recommended Capacitor
Types section
no
Recommended Capacitors for the Legacy
Chip
Tantalum Capacitors: For the
legacy chip LP2981-N, tantalum capacitors are the best choice for use at the output
of the LDO. Most good quality tantalums can be used with the LP2981-N, but check the
manufacturer's data sheet to be sure the ESR is in range. At lower temperatures, as
ESR increases, a capacitor with ESR, near the upper limit for stability at room
temperature can cause instability. For very low temperature applications, output
tantalum capacitors can be used in parallel configuration to prevent the ESR from
going up too high.
Ceramic Capacitors: For the
legacy chip LP2981-N, ceramic capacitors are not recommended for use at the output
of the LDO. This is because the ESR of a ceramic can be low enough to go below the
minimum stable value for the LP2981-N. A 2.2-μF ceramic was measured and found to
have an ESR of about 15 mΩ, which is low enough to cause oscillations.If a ceramic
capacitor is used on the output, a 1-Ω resistor is required be placed in series with
the capacitor.
Aluminimum Capacitors: For the
legacy chip LP2981-N, aluminum electrolytics are not typically used with the LDO,
because of the large physical size. These aluminimum capacitors must meet the same
ESR requirements over the operating temperature range, more difficult because of
their steep increase at cold temperature. An aluminum electrolytic can exhibit an
ESR increase of as much as 50x when going from 20°C to −40°C. Also, some aluminum
electrolytics are not operational below −25°C because the electrolyte can
freeze.
Recommended Capacitors for the New
Chip
The new chip is designed to be stable
using low equivalent series resistance (ESR) ceramic capacitors at the input and
output. Multilayer ceramic capacitors have become the industry standard for these
types of applications and are recommended, but must be used with good judgment.
Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials
provide relatively good capacitive stability across temperature, whereas using
Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor
type selected, the effective capacitance varies with operating voltage and
temperature. Generally, expect the effective capacitance to decrease by as much as
50%. The input and output capacitors listed in the
table account for an
effective capacitance of approximately 50% of the nominal value.
Input and Output Capacitor Requirements
Q
Added Input and Output Capacitor
Requirements section
no
Although an
input capacitor is not required for stability, good analog design practice is to connect a
capacitor from IN to GND. This capacitor counteracts reactive input sources and improves
transient response, input ripple, and PSRR. Use an input capacitor if the source impedance
is more than 0.5 Ω. A higher value capacitor can be necessary if large, fast rise-time load
or line transients are anticipated or if the device is located several inches from the input
power source.
Dynamic
performance of the device is improved with the use of an output capacitor. Use an output
capacitor within the range specified in the
table for stability.
Noise Bypass Capacitor (CBYPASS)
Q
Added start-up behavior discussion to Noise Bypass Capacitor
(CBYPASS) section
no
The LP2982 allows for low-noise
performance with the use of a bypass capacitor that is connected to the internal
band-gap reference with the BYPASS pin. This high-impedance band-gap circuitry is
biased in the microampere range and, thus, cannot be loaded significantly,
otherwise, the output (and, correspondingly, the output of the regulator) changes.
Thus, for best output accuracy, dc leakage current through CBYPASS must
be minimized as much as possible and must never exceed 100 nA. The
CBYPASS capacitor also impacts the start-up behavior of the
regulator. Inrush current and start-up time increase with larger bypass capacitor
values.
Use a 10-nF capacitor for
CBYPASS. Ceramic and film capacitors are good choices for this
purpose.
Reverse Current
Q
Added Reverse Current
section
no
Excessive
reverse current can damage this device. Reverse
current flows through the intrinsic body diode of
the pass transistor instead of the normal conducting
channel. At high magnitudes, this current flow
degrades the long-term reliability of the
device.
Conditions
where reverse current can occur are outlined in this
section, all of which can exceed the absolute
maximum rating of VOUT ≤ VIN +
0.3 V.
If the device has a large COUT and the
input supply collapses with little or no load
current
The output is biased when the input supply is not
established
The output is biased above the input supply
If reverse
current flow is expected in the application, use external protection to protect the device.
Reverse current is not limited in the device, so external limiting is required if extended
reverse voltage operation is anticipated.
shows one approach for
protecting the device.
Example Circuit
for Reverse Current Protection Using a Schottky Diode
Power Dissipation
(PD)
Q
Added Power Dissipation
(PD) section
no
Circuit
reliability requires consideration of the device
power dissipation, location of the circuit on the
printed circuit board (PCB), and correct sizing of
the thermal plane. The PCB area around the regulator
must have few or no other heat-generating devices
that cause added thermal stress.
To first-order
approximation, power dissipation in the regulator
depends on the input-to-output voltage difference
and load conditions. The following equation
calculates power dissipation (PD).
PD = (VIN
– VOUT) ×
IOUT
Power
dissipation can be minimized, and therefore greater efficiency can be achieved, by
correct selection of the system voltage rails. For the lowest power dissipation use
the minimum input voltage required for correct output regulation.
For devices
with a thermal pad, the primary heat conduction path
for the device package is through the thermal pad to
the PCB. Solder the thermal pad to a copper pad area
under the device. This pad area must contain an
array of plated vias that conduct heat to additional
copper planes for increased heat dissipation.
The maximum
power dissipation determines the maximum allowable
ambient temperature (TA) for the device.
According to the following equation, power
dissipation and junction temperature are most often
related by the junction-to-ambient thermal
resistance (RθJA) of the combined PCB and
device package and the temperature of the ambient
air (TA).
TJ = TA
+ (RθJA × PD)
Thermal
resistance (RθJA) is highly dependent on the heat-spreading capability built into
the particular PCB design, and therefore varies according to the total copper area, copper
weight, and location of the planes. The junction-to-ambient thermal resistance listed in the
table is determined by
the JEDEC standard PCB and copper-spreading area, and is used as a relative measure of
package thermal performance.
Estimating Junction Temperature
Q
Added Estimating Junction Temperature
section
no
The JEDEC standard now
recommends the use of psi (Ψ) thermal metrics to estimate the junction
temperatures of the linear regulator when in-circuit on a typical PCB board
application. These metrics are not thermal resistance parameters and instead
offer a practical and relative way to estimate junction temperature. These
psi metrics are determined to be significantly independent of the copper
area available for heat-spreading. The
table
lists the primary thermal metrics, which are the junction-to-top
characterization parameter (ψJT) and junction-to-board
characterization parameter (ψJB). These parameters provide two
methods for calculating the junction temperature (TJ), as
described in the following equations. Use the junction-to-top
characterization parameter (ψJT) with the temperature at the
center-top of device package (TT) to calculate the junction
temperature. Use the junction-to-board characterization parameter
(ψJB) with the PCB surface temperature 1 mm from the device
package (TB) to calculate the junction temperature.
TJ = TT +
ψJT × PD
where:
PD is the
dissipated power
TT is the
temperature at the center-top of the device package
TJ = TB +
ψJB × PD
where:
TB is the PCB
surface temperature measured 1 mm from the device package and centered
on the package edge
For detailed information on the
thermal metrics and how to use them, see the
Semiconductor
and IC Package Thermal Metrics application note.
Typical Application
LP2982
Typical Application
ON/
OFF input must be actively terminated. Tie to
VIN if this function is not to be used. Minimum output
capacitance is shown to insure stability over full load current range. More
capacitance provides better dynamic performance and additional stability margin
(see
).
Design Requirements
PARAMETER
DESIGN REQUIREMENT
Input voltage
12 V ±10%
Output voltage
3.3 V ±1.5%
Output current
50 mA
Ambient temperature
85°C
Detailed Design Procedure
ON/
OFF Input Operation
J
Changed layout of National Semiconductor Data Sheet to TI format
yes
The LP2982 is shut off by pulling the ON/
OFF input low, and turned on by driving the input high. If this
feature is not to be used, the ON/OFF input required to be tied to VIN to keep
the regulator on at all times (the ON/ OFF input must not be
left floating).
For proper operation of the LDO, the signal source
used to drive the ON/ OFF input must be able to swing above and below
the specified turnon/turnoff voltage thresholds which specify an ON or
OFF state.
The ON/ OFF signal can come
from either a totem-pole output, or an open-collector output with pullup resistor to the
LP2982 input voltage or another logic supply. The high-level voltage can exceed the LP2982
input voltage, but must remain within the absolute maximum ratings for the ON/
OFF pin.
It is also important that the turnon/turnoff voltage signals applied to the ON/
OFF input have a slew rate which is greater than 40 mV/μs.
IMPORTANT: For the legacy chip, the
regulator shutdown function does not operate correctly if a slow-moving signal
is applied to the ON/ OFF input.
Application Curves
5-V,
2.2-μF ESR Curves (Legacy chip)
VIN = 6 V
3-V, 4.7-μF ESR Curves (Legacy chip)
VIN = 4 V
Line
Transient Response (Legacy chip)
Line
Transient Response (Legacy chip)
Line Transient Response
(New Chip)
VOUT = 3.3 V, ΔVIN = 1 V,
IOUT = 50 mA, dV/dt = 1 V/μs
Load
Transient Response (Legacy chip)
Load
Transient Response (Legacy chip)
Load
Transient Response (Legacy chip)
Load
Transient Response (Legacy chip)
Load Transient Response
(New Chip)
dI/dt = 1 A/μs
Turnon Waveform (Legacy chip)
Turnon Waveform (Legacy chip)
Turnon Waveform (Legacy chip)
Turnon Waveform (New
chip)
Cbyp = 0 nF
Turnon Waveform (New
chip)
Cbyp = 0.1 nF
Turnon Waveform (New
chip)
Cbyp = 1 nF
Application and Implementation
Information in the following applications sections is not part of the TI
component specification, and TI does not warrant its accuracy or completeness.
TI’s customers are responsible for determining suitability of components for
their purposes, as well as validating and testing their design implementation to
confirm system functionality.
Information in the following applications sections is not part of the TI
component specification, and TI does not warrant its accuracy or completeness.
TI’s customers are responsible for determining suitability of components for
their purposes, as well as validating and testing their design implementation to
confirm system functionality.
Information in the following applications sections is not part of the TI
component specification, and TI does not warrant its accuracy or completeness.
TI’s customers are responsible for determining suitability of components for
their purposes, as well as validating and testing their design implementation to
confirm system functionality.
Information in the following applications sections is not part of the TI
component specification, and TI does not warrant its accuracy or completeness.
TI’s customers are responsible for determining suitability of components for
their purposes, as well as validating and testing their design implementation to
confirm system functionality.
Application Information
The LP2982 is a linear voltage regulator operating from 2.5 V to 16 V (for new chip)
on the input and regulates voltages between 1.2 V to 5 V with ±1% accuracy (across
line, load and temperature) and 50-mA maximum output current.
Successfully implementing an LDO in an
application depends on the application requirements. If the requirements are simply
input voltage and output voltage, compliance specifications (such as internal power
dissipation or stability) must be verified for a solid design. If timing, start-up,
noise, power supply rejection ratio (PSRR), or any other transient specification is
required, then the design becomes more challenging.
Recommended Capacitor Types
F
Added Recommended Capacitor
Types section
no
Recommended Capacitors for the Legacy
Chip
Tantalum Capacitors: For the
legacy chip LP2981-N, tantalum capacitors are the best choice for use at the output
of the LDO. Most good quality tantalums can be used with the LP2981-N, but check the
manufacturer's data sheet to be sure the ESR is in range. At lower temperatures, as
ESR increases, a capacitor with ESR, near the upper limit for stability at room
temperature can cause instability. For very low temperature applications, output
tantalum capacitors can be used in parallel configuration to prevent the ESR from
going up too high.
Ceramic Capacitors: For the
legacy chip LP2981-N, ceramic capacitors are not recommended for use at the output
of the LDO. This is because the ESR of a ceramic can be low enough to go below the
minimum stable value for the LP2981-N. A 2.2-μF ceramic was measured and found to
have an ESR of about 15 mΩ, which is low enough to cause oscillations.If a ceramic
capacitor is used on the output, a 1-Ω resistor is required be placed in series with
the capacitor.
Aluminimum Capacitors: For the
legacy chip LP2981-N, aluminum electrolytics are not typically used with the LDO,
because of the large physical size. These aluminimum capacitors must meet the same
ESR requirements over the operating temperature range, more difficult because of
their steep increase at cold temperature. An aluminum electrolytic can exhibit an
ESR increase of as much as 50x when going from 20°C to −40°C. Also, some aluminum
electrolytics are not operational below −25°C because the electrolyte can
freeze.
Recommended Capacitors for the New
Chip
The new chip is designed to be stable
using low equivalent series resistance (ESR) ceramic capacitors at the input and
output. Multilayer ceramic capacitors have become the industry standard for these
types of applications and are recommended, but must be used with good judgment.
Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials
provide relatively good capacitive stability across temperature, whereas using
Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor
type selected, the effective capacitance varies with operating voltage and
temperature. Generally, expect the effective capacitance to decrease by as much as
50%. The input and output capacitors listed in the
table account for an
effective capacitance of approximately 50% of the nominal value.
Input and Output Capacitor Requirements
Q
Added Input and Output Capacitor
Requirements section
no
Although an
input capacitor is not required for stability, good analog design practice is to connect a
capacitor from IN to GND. This capacitor counteracts reactive input sources and improves
transient response, input ripple, and PSRR. Use an input capacitor if the source impedance
is more than 0.5 Ω. A higher value capacitor can be necessary if large, fast rise-time load
or line transients are anticipated or if the device is located several inches from the input
power source.
Dynamic
performance of the device is improved with the use of an output capacitor. Use an output
capacitor within the range specified in the
table for stability.
Noise Bypass Capacitor (CBYPASS)
Q
Added start-up behavior discussion to Noise Bypass Capacitor
(CBYPASS) section
no
The LP2982 allows for low-noise
performance with the use of a bypass capacitor that is connected to the internal
band-gap reference with the BYPASS pin. This high-impedance band-gap circuitry is
biased in the microampere range and, thus, cannot be loaded significantly,
otherwise, the output (and, correspondingly, the output of the regulator) changes.
Thus, for best output accuracy, dc leakage current through CBYPASS must
be minimized as much as possible and must never exceed 100 nA. The
CBYPASS capacitor also impacts the start-up behavior of the
regulator. Inrush current and start-up time increase with larger bypass capacitor
values.
Use a 10-nF capacitor for
CBYPASS. Ceramic and film capacitors are good choices for this
purpose.
Reverse Current
Q
Added Reverse Current
section
no
Excessive
reverse current can damage this device. Reverse
current flows through the intrinsic body diode of
the pass transistor instead of the normal conducting
channel. At high magnitudes, this current flow
degrades the long-term reliability of the
device.
Conditions
where reverse current can occur are outlined in this
section, all of which can exceed the absolute
maximum rating of VOUT ≤ VIN +
0.3 V.
If the device has a large COUT and the
input supply collapses with little or no load
current
The output is biased when the input supply is not
established
The output is biased above the input supply
If reverse
current flow is expected in the application, use external protection to protect the device.
Reverse current is not limited in the device, so external limiting is required if extended
reverse voltage operation is anticipated.
shows one approach for
protecting the device.
Example Circuit
for Reverse Current Protection Using a Schottky Diode
Power Dissipation
(PD)
Q
Added Power Dissipation
(PD) section
no
Circuit
reliability requires consideration of the device
power dissipation, location of the circuit on the
printed circuit board (PCB), and correct sizing of
the thermal plane. The PCB area around the regulator
must have few or no other heat-generating devices
that cause added thermal stress.
To first-order
approximation, power dissipation in the regulator
depends on the input-to-output voltage difference
and load conditions. The following equation
calculates power dissipation (PD).
PD = (VIN
– VOUT) ×
IOUT
Power
dissipation can be minimized, and therefore greater efficiency can be achieved, by
correct selection of the system voltage rails. For the lowest power dissipation use
the minimum input voltage required for correct output regulation.
For devices
with a thermal pad, the primary heat conduction path
for the device package is through the thermal pad to
the PCB. Solder the thermal pad to a copper pad area
under the device. This pad area must contain an
array of plated vias that conduct heat to additional
copper planes for increased heat dissipation.
The maximum
power dissipation determines the maximum allowable
ambient temperature (TA) for the device.
According to the following equation, power
dissipation and junction temperature are most often
related by the junction-to-ambient thermal
resistance (RθJA) of the combined PCB and
device package and the temperature of the ambient
air (TA).
TJ = TA
+ (RθJA × PD)
Thermal
resistance (RθJA) is highly dependent on the heat-spreading capability built into
the particular PCB design, and therefore varies according to the total copper area, copper
weight, and location of the planes. The junction-to-ambient thermal resistance listed in the
table is determined by
the JEDEC standard PCB and copper-spreading area, and is used as a relative measure of
package thermal performance.
Estimating Junction Temperature
Q
Added Estimating Junction Temperature
section
no
The JEDEC standard now
recommends the use of psi (Ψ) thermal metrics to estimate the junction
temperatures of the linear regulator when in-circuit on a typical PCB board
application. These metrics are not thermal resistance parameters and instead
offer a practical and relative way to estimate junction temperature. These
psi metrics are determined to be significantly independent of the copper
area available for heat-spreading. The
table
lists the primary thermal metrics, which are the junction-to-top
characterization parameter (ψJT) and junction-to-board
characterization parameter (ψJB). These parameters provide two
methods for calculating the junction temperature (TJ), as
described in the following equations. Use the junction-to-top
characterization parameter (ψJT) with the temperature at the
center-top of device package (TT) to calculate the junction
temperature. Use the junction-to-board characterization parameter
(ψJB) with the PCB surface temperature 1 mm from the device
package (TB) to calculate the junction temperature.
TJ = TT +
ψJT × PD
where:
PD is the
dissipated power
TT is the
temperature at the center-top of the device package
TJ = TB +
ψJB × PD
where:
TB is the PCB
surface temperature measured 1 mm from the device package and centered
on the package edge
For detailed information on the
thermal metrics and how to use them, see the
Semiconductor
and IC Package Thermal Metrics application note.
Application Information
The LP2982 is a linear voltage regulator operating from 2.5 V to 16 V (for new chip)
on the input and regulates voltages between 1.2 V to 5 V with ±1% accuracy (across
line, load and temperature) and 50-mA maximum output current.
Successfully implementing an LDO in an
application depends on the application requirements. If the requirements are simply
input voltage and output voltage, compliance specifications (such as internal power
dissipation or stability) must be verified for a solid design. If timing, start-up,
noise, power supply rejection ratio (PSRR), or any other transient specification is
required, then the design becomes more challenging.
The LP2982 is a linear voltage regulator operating from 2.5 V to 16 V (for new chip)
on the input and regulates voltages between 1.2 V to 5 V with ±1% accuracy (across
line, load and temperature) and 50-mA maximum output current.
Successfully implementing an LDO in an
application depends on the application requirements. If the requirements are simply
input voltage and output voltage, compliance specifications (such as internal power
dissipation or stability) must be verified for a solid design. If timing, start-up,
noise, power supply rejection ratio (PSRR), or any other transient specification is
required, then the design becomes more challenging.
The LP2982 is a linear voltage regulator operating from 2.5 V to 16 V (for new chip)
on the input and regulates voltages between 1.2 V to 5 V with ±1% accuracy (across
line, load and temperature) and 50-mA maximum output current.Successfully implementing an LDO in an
application depends on the application requirements. If the requirements are simply
input voltage and output voltage, compliance specifications (such as internal power
dissipation or stability) must be verified for a solid design. If timing, start-up,
noise, power supply rejection ratio (PSRR), or any other transient specification is
required, then the design becomes more challenging.
Recommended Capacitor Types
F
Added Recommended Capacitor
Types section
no
Recommended Capacitors for the Legacy
Chip
Tantalum Capacitors: For the
legacy chip LP2981-N, tantalum capacitors are the best choice for use at the output
of the LDO. Most good quality tantalums can be used with the LP2981-N, but check the
manufacturer's data sheet to be sure the ESR is in range. At lower temperatures, as
ESR increases, a capacitor with ESR, near the upper limit for stability at room
temperature can cause instability. For very low temperature applications, output
tantalum capacitors can be used in parallel configuration to prevent the ESR from
going up too high.
Ceramic Capacitors: For the
legacy chip LP2981-N, ceramic capacitors are not recommended for use at the output
of the LDO. This is because the ESR of a ceramic can be low enough to go below the
minimum stable value for the LP2981-N. A 2.2-μF ceramic was measured and found to
have an ESR of about 15 mΩ, which is low enough to cause oscillations.If a ceramic
capacitor is used on the output, a 1-Ω resistor is required be placed in series with
the capacitor.
Aluminimum Capacitors: For the
legacy chip LP2981-N, aluminum electrolytics are not typically used with the LDO,
because of the large physical size. These aluminimum capacitors must meet the same
ESR requirements over the operating temperature range, more difficult because of
their steep increase at cold temperature. An aluminum electrolytic can exhibit an
ESR increase of as much as 50x when going from 20°C to −40°C. Also, some aluminum
electrolytics are not operational below −25°C because the electrolyte can
freeze.
Recommended Capacitors for the New
Chip
The new chip is designed to be stable
using low equivalent series resistance (ESR) ceramic capacitors at the input and
output. Multilayer ceramic capacitors have become the industry standard for these
types of applications and are recommended, but must be used with good judgment.
Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials
provide relatively good capacitive stability across temperature, whereas using
Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor
type selected, the effective capacitance varies with operating voltage and
temperature. Generally, expect the effective capacitance to decrease by as much as
50%. The input and output capacitors listed in the
table account for an
effective capacitance of approximately 50% of the nominal value.
Recommended Capacitor Types
F
Added Recommended Capacitor
Types section
no
F
Added Recommended Capacitor
Types section
no
F
Added Recommended Capacitor
Types section
no
FAdded Recommended Capacitor
Types sectionRecommended Capacitor
Typesno
Recommended Capacitors for the Legacy
Chip
Tantalum Capacitors: For the
legacy chip LP2981-N, tantalum capacitors are the best choice for use at the output
of the LDO. Most good quality tantalums can be used with the LP2981-N, but check the
manufacturer's data sheet to be sure the ESR is in range. At lower temperatures, as
ESR increases, a capacitor with ESR, near the upper limit for stability at room
temperature can cause instability. For very low temperature applications, output
tantalum capacitors can be used in parallel configuration to prevent the ESR from
going up too high.
Ceramic Capacitors: For the
legacy chip LP2981-N, ceramic capacitors are not recommended for use at the output
of the LDO. This is because the ESR of a ceramic can be low enough to go below the
minimum stable value for the LP2981-N. A 2.2-μF ceramic was measured and found to
have an ESR of about 15 mΩ, which is low enough to cause oscillations.If a ceramic
capacitor is used on the output, a 1-Ω resistor is required be placed in series with
the capacitor.
Aluminimum Capacitors: For the
legacy chip LP2981-N, aluminum electrolytics are not typically used with the LDO,
because of the large physical size. These aluminimum capacitors must meet the same
ESR requirements over the operating temperature range, more difficult because of
their steep increase at cold temperature. An aluminum electrolytic can exhibit an
ESR increase of as much as 50x when going from 20°C to −40°C. Also, some aluminum
electrolytics are not operational below −25°C because the electrolyte can
freeze.
Recommended Capacitors for the Legacy
Chip
Tantalum Capacitors: For the
legacy chip LP2981-N, tantalum capacitors are the best choice for use at the output
of the LDO. Most good quality tantalums can be used with the LP2981-N, but check the
manufacturer's data sheet to be sure the ESR is in range. At lower temperatures, as
ESR increases, a capacitor with ESR, near the upper limit for stability at room
temperature can cause instability. For very low temperature applications, output
tantalum capacitors can be used in parallel configuration to prevent the ESR from
going up too high.
Ceramic Capacitors: For the
legacy chip LP2981-N, ceramic capacitors are not recommended for use at the output
of the LDO. This is because the ESR of a ceramic can be low enough to go below the
minimum stable value for the LP2981-N. A 2.2-μF ceramic was measured and found to
have an ESR of about 15 mΩ, which is low enough to cause oscillations.If a ceramic
capacitor is used on the output, a 1-Ω resistor is required be placed in series with
the capacitor.
Aluminimum Capacitors: For the
legacy chip LP2981-N, aluminum electrolytics are not typically used with the LDO,
because of the large physical size. These aluminimum capacitors must meet the same
ESR requirements over the operating temperature range, more difficult because of
their steep increase at cold temperature. An aluminum electrolytic can exhibit an
ESR increase of as much as 50x when going from 20°C to −40°C. Also, some aluminum
electrolytics are not operational below −25°C because the electrolyte can
freeze.
Tantalum Capacitors: For the
legacy chip LP2981-N, tantalum capacitors are the best choice for use at the output
of the LDO. Most good quality tantalums can be used with the LP2981-N, but check the
manufacturer's data sheet to be sure the ESR is in range. At lower temperatures, as
ESR increases, a capacitor with ESR, near the upper limit for stability at room
temperature can cause instability. For very low temperature applications, output
tantalum capacitors can be used in parallel configuration to prevent the ESR from
going up too high.
Ceramic Capacitors: For the
legacy chip LP2981-N, ceramic capacitors are not recommended for use at the output
of the LDO. This is because the ESR of a ceramic can be low enough to go below the
minimum stable value for the LP2981-N. A 2.2-μF ceramic was measured and found to
have an ESR of about 15 mΩ, which is low enough to cause oscillations.If a ceramic
capacitor is used on the output, a 1-Ω resistor is required be placed in series with
the capacitor.
Aluminimum Capacitors: For the
legacy chip LP2981-N, aluminum electrolytics are not typically used with the LDO,
because of the large physical size. These aluminimum capacitors must meet the same
ESR requirements over the operating temperature range, more difficult because of
their steep increase at cold temperature. An aluminum electrolytic can exhibit an
ESR increase of as much as 50x when going from 20°C to −40°C. Also, some aluminum
electrolytics are not operational below −25°C because the electrolyte can
freeze.
Tantalum Capacitors: For the
legacy chip LP2981-N, tantalum capacitors are the best choice for use at the output
of the LDO. Most good quality tantalums can be used with the LP2981-N, but check the
manufacturer's data sheet to be sure the ESR is in range. At lower temperatures, as
ESR increases, a capacitor with ESR, near the upper limit for stability at room
temperature can cause instability. For very low temperature applications, output
tantalum capacitors can be used in parallel configuration to prevent the ESR from
going up too high.Tantalum Capacitors:
Ceramic Capacitors: For the
legacy chip LP2981-N, ceramic capacitors are not recommended for use at the output
of the LDO. This is because the ESR of a ceramic can be low enough to go below the
minimum stable value for the LP2981-N. A 2.2-μF ceramic was measured and found to
have an ESR of about 15 mΩ, which is low enough to cause oscillations.If a ceramic
capacitor is used on the output, a 1-Ω resistor is required be placed in series with
the capacitor.Ceramic Capacitors:
Aluminimum Capacitors: For the
legacy chip LP2981-N, aluminum electrolytics are not typically used with the LDO,
because of the large physical size. These aluminimum capacitors must meet the same
ESR requirements over the operating temperature range, more difficult because of
their steep increase at cold temperature. An aluminum electrolytic can exhibit an
ESR increase of as much as 50x when going from 20°C to −40°C. Also, some aluminum
electrolytics are not operational below −25°C because the electrolyte can
freeze.Aluminimum Capacitors:
Recommended Capacitors for the New
Chip
The new chip is designed to be stable
using low equivalent series resistance (ESR) ceramic capacitors at the input and
output. Multilayer ceramic capacitors have become the industry standard for these
types of applications and are recommended, but must be used with good judgment.
Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials
provide relatively good capacitive stability across temperature, whereas using
Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor
type selected, the effective capacitance varies with operating voltage and
temperature. Generally, expect the effective capacitance to decrease by as much as
50%. The input and output capacitors listed in the
table account for an
effective capacitance of approximately 50% of the nominal value.
Recommended Capacitors for the New
Chip
The new chip is designed to be stable
using low equivalent series resistance (ESR) ceramic capacitors at the input and
output. Multilayer ceramic capacitors have become the industry standard for these
types of applications and are recommended, but must be used with good judgment.
Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials
provide relatively good capacitive stability across temperature, whereas using
Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor
type selected, the effective capacitance varies with operating voltage and
temperature. Generally, expect the effective capacitance to decrease by as much as
50%. The input and output capacitors listed in the
table account for an
effective capacitance of approximately 50% of the nominal value.
The new chip is designed to be stable
using low equivalent series resistance (ESR) ceramic capacitors at the input and
output. Multilayer ceramic capacitors have become the industry standard for these
types of applications and are recommended, but must be used with good judgment.
Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials
provide relatively good capacitive stability across temperature, whereas using
Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor
type selected, the effective capacitance varies with operating voltage and
temperature. Generally, expect the effective capacitance to decrease by as much as
50%. The input and output capacitors listed in the
table account for an
effective capacitance of approximately 50% of the nominal value.
The new chip is designed to be stable
using low equivalent series resistance (ESR) ceramic capacitors at the input and
output. Multilayer ceramic capacitors have become the industry standard for these
types of applications and are recommended, but must be used with good judgment.
Ceramic capacitors that employ X7R-, X5R-, and C0G-rated dielectric materials
provide relatively good capacitive stability across temperature, whereas using
Y5V-rated capacitors is discouraged because of large variations in capacitance.Regardless of the ceramic capacitor
type selected, the effective capacitance varies with operating voltage and
temperature. Generally, expect the effective capacitance to decrease by as much as
50%. The input and output capacitors listed in the
table account for an
effective capacitance of approximately 50% of the nominal value.
Input and Output Capacitor Requirements
Q
Added Input and Output Capacitor
Requirements section
no
Although an
input capacitor is not required for stability, good analog design practice is to connect a
capacitor from IN to GND. This capacitor counteracts reactive input sources and improves
transient response, input ripple, and PSRR. Use an input capacitor if the source impedance
is more than 0.5 Ω. A higher value capacitor can be necessary if large, fast rise-time load
or line transients are anticipated or if the device is located several inches from the input
power source.
Dynamic
performance of the device is improved with the use of an output capacitor. Use an output
capacitor within the range specified in the
table for stability.
Input and Output Capacitor Requirements
Q
Added Input and Output Capacitor
Requirements section
no
Q
Added Input and Output Capacitor
Requirements section
no
Q
Added Input and Output Capacitor
Requirements section
no
QAdded Input and Output Capacitor
Requirements sectionInput and Output Capacitor
Requirementsno
Although an
input capacitor is not required for stability, good analog design practice is to connect a
capacitor from IN to GND. This capacitor counteracts reactive input sources and improves
transient response, input ripple, and PSRR. Use an input capacitor if the source impedance
is more than 0.5 Ω. A higher value capacitor can be necessary if large, fast rise-time load
or line transients are anticipated or if the device is located several inches from the input
power source.
Dynamic
performance of the device is improved with the use of an output capacitor. Use an output
capacitor within the range specified in the
table for stability.
Although an
input capacitor is not required for stability, good analog design practice is to connect a
capacitor from IN to GND. This capacitor counteracts reactive input sources and improves
transient response, input ripple, and PSRR. Use an input capacitor if the source impedance
is more than 0.5 Ω. A higher value capacitor can be necessary if large, fast rise-time load
or line transients are anticipated or if the device is located several inches from the input
power source.
Dynamic
performance of the device is improved with the use of an output capacitor. Use an output
capacitor within the range specified in the
table for stability.
Although an
input capacitor is not required for stability, good analog design practice is to connect a
capacitor from IN to GND. This capacitor counteracts reactive input sources and improves
transient response, input ripple, and PSRR. Use an input capacitor if the source impedance
is more than 0.5 Ω. A higher value capacitor can be necessary if large, fast rise-time load
or line transients are anticipated or if the device is located several inches from the input
power source.Dynamic
performance of the device is improved with the use of an output capacitor. Use an output
capacitor within the range specified in the
table for stability.
Noise Bypass Capacitor (CBYPASS)
Q
Added start-up behavior discussion to Noise Bypass Capacitor
(CBYPASS) section
no
The LP2982 allows for low-noise
performance with the use of a bypass capacitor that is connected to the internal
band-gap reference with the BYPASS pin. This high-impedance band-gap circuitry is
biased in the microampere range and, thus, cannot be loaded significantly,
otherwise, the output (and, correspondingly, the output of the regulator) changes.
Thus, for best output accuracy, dc leakage current through CBYPASS must
be minimized as much as possible and must never exceed 100 nA. The
CBYPASS capacitor also impacts the start-up behavior of the
regulator. Inrush current and start-up time increase with larger bypass capacitor
values.
Use a 10-nF capacitor for
CBYPASS. Ceramic and film capacitors are good choices for this
purpose.
Noise Bypass Capacitor (CBYPASS)BYPASS
Q
Added start-up behavior discussion to Noise Bypass Capacitor
(CBYPASS) section
no
Q
Added start-up behavior discussion to Noise Bypass Capacitor
(CBYPASS) section
no
Q
Added start-up behavior discussion to Noise Bypass Capacitor
(CBYPASS) section
no
QAdded start-up behavior discussion to Noise Bypass Capacitor
(CBYPASS) sectionNoise Bypass Capacitor
(CBYPASS)BYPASSno
The LP2982 allows for low-noise
performance with the use of a bypass capacitor that is connected to the internal
band-gap reference with the BYPASS pin. This high-impedance band-gap circuitry is
biased in the microampere range and, thus, cannot be loaded significantly,
otherwise, the output (and, correspondingly, the output of the regulator) changes.
Thus, for best output accuracy, dc leakage current through CBYPASS must
be minimized as much as possible and must never exceed 100 nA. The
CBYPASS capacitor also impacts the start-up behavior of the
regulator. Inrush current and start-up time increase with larger bypass capacitor
values.
Use a 10-nF capacitor for
CBYPASS. Ceramic and film capacitors are good choices for this
purpose.
The LP2982 allows for low-noise
performance with the use of a bypass capacitor that is connected to the internal
band-gap reference with the BYPASS pin. This high-impedance band-gap circuitry is
biased in the microampere range and, thus, cannot be loaded significantly,
otherwise, the output (and, correspondingly, the output of the regulator) changes.
Thus, for best output accuracy, dc leakage current through CBYPASS must
be minimized as much as possible and must never exceed 100 nA. The
CBYPASS capacitor also impacts the start-up behavior of the
regulator. Inrush current and start-up time increase with larger bypass capacitor
values.
Use a 10-nF capacitor for
CBYPASS. Ceramic and film capacitors are good choices for this
purpose.
The LP2982 allows for low-noise
performance with the use of a bypass capacitor that is connected to the internal
band-gap reference with the BYPASS pin. This high-impedance band-gap circuitry is
biased in the microampere range and, thus, cannot be loaded significantly,
otherwise, the output (and, correspondingly, the output of the regulator) changes.
Thus, for best output accuracy, dc leakage current through CBYPASS must
be minimized as much as possible and must never exceed 100 nA. The
CBYPASS capacitor also impacts the start-up behavior of the
regulator. Inrush current and start-up time increase with larger bypass capacitor
values. BYPASSBYPASSUse a 10-nF capacitor for
CBYPASS. Ceramic and film capacitors are good choices for this
purpose.BYPASS
Reverse Current
Q
Added Reverse Current
section
no
Excessive
reverse current can damage this device. Reverse
current flows through the intrinsic body diode of
the pass transistor instead of the normal conducting
channel. At high magnitudes, this current flow
degrades the long-term reliability of the
device.
Conditions
where reverse current can occur are outlined in this
section, all of which can exceed the absolute
maximum rating of VOUT ≤ VIN +
0.3 V.
If the device has a large COUT and the
input supply collapses with little or no load
current
The output is biased when the input supply is not
established
The output is biased above the input supply
If reverse
current flow is expected in the application, use external protection to protect the device.
Reverse current is not limited in the device, so external limiting is required if extended
reverse voltage operation is anticipated.
shows one approach for
protecting the device.
Example Circuit
for Reverse Current Protection Using a Schottky Diode
Reverse Current
Q
Added Reverse Current
section
no
Q
Added Reverse Current
section
no
Q
Added Reverse Current
section
no
QAdded Reverse Current
sectionReverse Currentno
Excessive
reverse current can damage this device. Reverse
current flows through the intrinsic body diode of
the pass transistor instead of the normal conducting
channel. At high magnitudes, this current flow
degrades the long-term reliability of the
device.
Conditions
where reverse current can occur are outlined in this
section, all of which can exceed the absolute
maximum rating of VOUT ≤ VIN +
0.3 V.
If the device has a large COUT and the
input supply collapses with little or no load
current
The output is biased when the input supply is not
established
The output is biased above the input supply
If reverse
current flow is expected in the application, use external protection to protect the device.
Reverse current is not limited in the device, so external limiting is required if extended
reverse voltage operation is anticipated.
shows one approach for
protecting the device.
Example Circuit
for Reverse Current Protection Using a Schottky Diode
Excessive
reverse current can damage this device. Reverse
current flows through the intrinsic body diode of
the pass transistor instead of the normal conducting
channel. At high magnitudes, this current flow
degrades the long-term reliability of the
device.
Conditions
where reverse current can occur are outlined in this
section, all of which can exceed the absolute
maximum rating of VOUT ≤ VIN +
0.3 V.
If the device has a large COUT and the
input supply collapses with little or no load
current
The output is biased when the input supply is not
established
The output is biased above the input supply
If reverse
current flow is expected in the application, use external protection to protect the device.
Reverse current is not limited in the device, so external limiting is required if extended
reverse voltage operation is anticipated.
shows one approach for
protecting the device.
Example Circuit
for Reverse Current Protection Using a Schottky Diode
Excessive
reverse current can damage this device. Reverse
current flows through the intrinsic body diode of
the pass transistor instead of the normal conducting
channel. At high magnitudes, this current flow
degrades the long-term reliability of the
device.Conditions
where reverse current can occur are outlined in this
section, all of which can exceed the absolute
maximum rating of VOUT ≤ VIN +
0.3 V.OUTIN
If the device has a large COUT and the
input supply collapses with little or no load
current
The output is biased when the input supply is not
established
The output is biased above the input supply
If the device has a large COUT and the
input supply collapses with little or no load
currentOUTThe output is biased when the input supply is not
establishedThe output is biased above the input supplyIf reverse
current flow is expected in the application, use external protection to protect the device.
Reverse current is not limited in the device, so external limiting is required if extended
reverse voltage operation is anticipated.
shows one approach for
protecting the device.
Example Circuit
for Reverse Current Protection Using a Schottky Diode
Example Circuit
for Reverse Current Protection Using a Schottky Diode
Power Dissipation
(PD)
Q
Added Power Dissipation
(PD) section
no
Circuit
reliability requires consideration of the device
power dissipation, location of the circuit on the
printed circuit board (PCB), and correct sizing of
the thermal plane. The PCB area around the regulator
must have few or no other heat-generating devices
that cause added thermal stress.
To first-order
approximation, power dissipation in the regulator
depends on the input-to-output voltage difference
and load conditions. The following equation
calculates power dissipation (PD).
PD = (VIN
– VOUT) ×
IOUT
Power
dissipation can be minimized, and therefore greater efficiency can be achieved, by
correct selection of the system voltage rails. For the lowest power dissipation use
the minimum input voltage required for correct output regulation.
For devices
with a thermal pad, the primary heat conduction path
for the device package is through the thermal pad to
the PCB. Solder the thermal pad to a copper pad area
under the device. This pad area must contain an
array of plated vias that conduct heat to additional
copper planes for increased heat dissipation.
The maximum
power dissipation determines the maximum allowable
ambient temperature (TA) for the device.
According to the following equation, power
dissipation and junction temperature are most often
related by the junction-to-ambient thermal
resistance (RθJA) of the combined PCB and
device package and the temperature of the ambient
air (TA).
TJ = TA
+ (RθJA × PD)
Thermal
resistance (RθJA) is highly dependent on the heat-spreading capability built into
the particular PCB design, and therefore varies according to the total copper area, copper
weight, and location of the planes. The junction-to-ambient thermal resistance listed in the
table is determined by
the JEDEC standard PCB and copper-spreading area, and is used as a relative measure of
package thermal performance.
Power Dissipation
(PD)D
Q
Added Power Dissipation
(PD) section
no
Q
Added Power Dissipation
(PD) section
no
Q
Added Power Dissipation
(PD) section
no
QAdded Power Dissipation
(PD) sectionPower Dissipation
(PD)Dno
Circuit
reliability requires consideration of the device
power dissipation, location of the circuit on the
printed circuit board (PCB), and correct sizing of
the thermal plane. The PCB area around the regulator
must have few or no other heat-generating devices
that cause added thermal stress.
To first-order
approximation, power dissipation in the regulator
depends on the input-to-output voltage difference
and load conditions. The following equation
calculates power dissipation (PD).
PD = (VIN
– VOUT) ×
IOUT
Power
dissipation can be minimized, and therefore greater efficiency can be achieved, by
correct selection of the system voltage rails. For the lowest power dissipation use
the minimum input voltage required for correct output regulation.
For devices
with a thermal pad, the primary heat conduction path
for the device package is through the thermal pad to
the PCB. Solder the thermal pad to a copper pad area
under the device. This pad area must contain an
array of plated vias that conduct heat to additional
copper planes for increased heat dissipation.
The maximum
power dissipation determines the maximum allowable
ambient temperature (TA) for the device.
According to the following equation, power
dissipation and junction temperature are most often
related by the junction-to-ambient thermal
resistance (RθJA) of the combined PCB and
device package and the temperature of the ambient
air (TA).
TJ = TA
+ (RθJA × PD)
Thermal
resistance (RθJA) is highly dependent on the heat-spreading capability built into
the particular PCB design, and therefore varies according to the total copper area, copper
weight, and location of the planes. The junction-to-ambient thermal resistance listed in the
table is determined by
the JEDEC standard PCB and copper-spreading area, and is used as a relative measure of
package thermal performance.
Circuit
reliability requires consideration of the device
power dissipation, location of the circuit on the
printed circuit board (PCB), and correct sizing of
the thermal plane. The PCB area around the regulator
must have few or no other heat-generating devices
that cause added thermal stress.
To first-order
approximation, power dissipation in the regulator
depends on the input-to-output voltage difference
and load conditions. The following equation
calculates power dissipation (PD).
PD = (VIN
– VOUT) ×
IOUT
Power
dissipation can be minimized, and therefore greater efficiency can be achieved, by
correct selection of the system voltage rails. For the lowest power dissipation use
the minimum input voltage required for correct output regulation.
For devices
with a thermal pad, the primary heat conduction path
for the device package is through the thermal pad to
the PCB. Solder the thermal pad to a copper pad area
under the device. This pad area must contain an
array of plated vias that conduct heat to additional
copper planes for increased heat dissipation.
The maximum
power dissipation determines the maximum allowable
ambient temperature (TA) for the device.
According to the following equation, power
dissipation and junction temperature are most often
related by the junction-to-ambient thermal
resistance (RθJA) of the combined PCB and
device package and the temperature of the ambient
air (TA).
TJ = TA
+ (RθJA × PD)
Thermal
resistance (RθJA) is highly dependent on the heat-spreading capability built into
the particular PCB design, and therefore varies according to the total copper area, copper
weight, and location of the planes. The junction-to-ambient thermal resistance listed in the
table is determined by
the JEDEC standard PCB and copper-spreading area, and is used as a relative measure of
package thermal performance.
Circuit
reliability requires consideration of the device
power dissipation, location of the circuit on the
printed circuit board (PCB), and correct sizing of
the thermal plane. The PCB area around the regulator
must have few or no other heat-generating devices
that cause added thermal stress.To first-order
approximation, power dissipation in the regulator
depends on the input-to-output voltage difference
and load conditions. The following equation
calculates power dissipation (PD).DPD = (VIN
– VOUT) ×
IOUT
DINOUTOUTPower
dissipation can be minimized, and therefore greater efficiency can be achieved, by
correct selection of the system voltage rails. For the lowest power dissipation use
the minimum input voltage required for correct output regulation.For devices
with a thermal pad, the primary heat conduction path
for the device package is through the thermal pad to
the PCB. Solder the thermal pad to a copper pad area
under the device. This pad area must contain an
array of plated vias that conduct heat to additional
copper planes for increased heat dissipation.The maximum
power dissipation determines the maximum allowable
ambient temperature (TA) for the device.
According to the following equation, power
dissipation and junction temperature are most often
related by the junction-to-ambient thermal
resistance (RθJA) of the combined PCB and
device package and the temperature of the ambient
air (TA).AθJAA TJ = TA
+ (RθJA × PD) JAθJADThermal
resistance (RθJA) is highly dependent on the heat-spreading capability built into
the particular PCB design, and therefore varies according to the total copper area, copper
weight, and location of the planes. The junction-to-ambient thermal resistance listed in the
table is determined by
the JEDEC standard PCB and copper-spreading area, and is used as a relative measure of
package thermal performance.θJA
Estimating Junction Temperature
Q
Added Estimating Junction Temperature
section
no
The JEDEC standard now
recommends the use of psi (Ψ) thermal metrics to estimate the junction
temperatures of the linear regulator when in-circuit on a typical PCB board
application. These metrics are not thermal resistance parameters and instead
offer a practical and relative way to estimate junction temperature. These
psi metrics are determined to be significantly independent of the copper
area available for heat-spreading. The
table
lists the primary thermal metrics, which are the junction-to-top
characterization parameter (ψJT) and junction-to-board
characterization parameter (ψJB). These parameters provide two
methods for calculating the junction temperature (TJ), as
described in the following equations. Use the junction-to-top
characterization parameter (ψJT) with the temperature at the
center-top of device package (TT) to calculate the junction
temperature. Use the junction-to-board characterization parameter
(ψJB) with the PCB surface temperature 1 mm from the device
package (TB) to calculate the junction temperature.
TJ = TT +
ψJT × PD
where:
PD is the
dissipated power
TT is the
temperature at the center-top of the device package
TJ = TB +
ψJB × PD
where:
TB is the PCB
surface temperature measured 1 mm from the device package and centered
on the package edge
For detailed information on the
thermal metrics and how to use them, see the
Semiconductor
and IC Package Thermal Metrics application note.
Estimating Junction Temperature
Q
Added Estimating Junction Temperature
section
no
Q
Added Estimating Junction Temperature
section
no
Q
Added Estimating Junction Temperature
section
no
QAdded Estimating Junction Temperature
sectionEstimating Junction Temperatureno
The JEDEC standard now
recommends the use of psi (Ψ) thermal metrics to estimate the junction
temperatures of the linear regulator when in-circuit on a typical PCB board
application. These metrics are not thermal resistance parameters and instead
offer a practical and relative way to estimate junction temperature. These
psi metrics are determined to be significantly independent of the copper
area available for heat-spreading. The
table
lists the primary thermal metrics, which are the junction-to-top
characterization parameter (ψJT) and junction-to-board
characterization parameter (ψJB). These parameters provide two
methods for calculating the junction temperature (TJ), as
described in the following equations. Use the junction-to-top
characterization parameter (ψJT) with the temperature at the
center-top of device package (TT) to calculate the junction
temperature. Use the junction-to-board characterization parameter
(ψJB) with the PCB surface temperature 1 mm from the device
package (TB) to calculate the junction temperature.
TJ = TT +
ψJT × PD
where:
PD is the
dissipated power
TT is the
temperature at the center-top of the device package
TJ = TB +
ψJB × PD
where:
TB is the PCB
surface temperature measured 1 mm from the device package and centered
on the package edge
For detailed information on the
thermal metrics and how to use them, see the
Semiconductor
and IC Package Thermal Metrics application note.
The JEDEC standard now
recommends the use of psi (Ψ) thermal metrics to estimate the junction
temperatures of the linear regulator when in-circuit on a typical PCB board
application. These metrics are not thermal resistance parameters and instead
offer a practical and relative way to estimate junction temperature. These
psi metrics are determined to be significantly independent of the copper
area available for heat-spreading. The
table
lists the primary thermal metrics, which are the junction-to-top
characterization parameter (ψJT) and junction-to-board
characterization parameter (ψJB). These parameters provide two
methods for calculating the junction temperature (TJ), as
described in the following equations. Use the junction-to-top
characterization parameter (ψJT) with the temperature at the
center-top of device package (TT) to calculate the junction
temperature. Use the junction-to-board characterization parameter
(ψJB) with the PCB surface temperature 1 mm from the device
package (TB) to calculate the junction temperature.
TJ = TT +
ψJT × PD
where:
PD is the
dissipated power
TT is the
temperature at the center-top of the device package
TJ = TB +
ψJB × PD
where:
TB is the PCB
surface temperature measured 1 mm from the device package and centered
on the package edge
For detailed information on the
thermal metrics and how to use them, see the
Semiconductor
and IC Package Thermal Metrics application note.
The JEDEC standard now
recommends the use of psi (Ψ) thermal metrics to estimate the junction
temperatures of the linear regulator when in-circuit on a typical PCB board
application. These metrics are not thermal resistance parameters and instead
offer a practical and relative way to estimate junction temperature. These
psi metrics are determined to be significantly independent of the copper
area available for heat-spreading. The
table
lists the primary thermal metrics, which are the junction-to-top
characterization parameter (ψJT) and junction-to-board
characterization parameter (ψJB). These parameters provide two
methods for calculating the junction temperature (TJ), as
described in the following equations. Use the junction-to-top
characterization parameter (ψJT) with the temperature at the
center-top of device package (TT) to calculate the junction
temperature. Use the junction-to-board characterization parameter
(ψJB) with the PCB surface temperature 1 mm from the device
package (TB) to calculate the junction temperature.
JTJBJJTTJBBTJ = TT +
ψJT × PD
JTJTDwhere:
PD is the
dissipated power
TT is the
temperature at the center-top of the device package
PD is the
dissipated powerDTT is the
temperature at the center-top of the device packageTTJ = TB +
ψJB × PD
JBJBDwhere:
TB is the PCB
surface temperature measured 1 mm from the device package and centered
on the package edge
TB is the PCB
surface temperature measured 1 mm from the device package and centered
on the package edgeBFor detailed information on the
thermal metrics and how to use them, see the
Semiconductor
and IC Package Thermal Metrics application note.
Semiconductor
and IC Package Thermal Metrics application noteSemiconductor
and IC Package Thermal Metrics
Typical Application
LP2982
Typical Application
ON/
OFF input must be actively terminated. Tie to
VIN if this function is not to be used. Minimum output
capacitance is shown to insure stability over full load current range. More
capacitance provides better dynamic performance and additional stability margin
(see
).
Design Requirements
PARAMETER
DESIGN REQUIREMENT
Input voltage
12 V ±10%
Output voltage
3.3 V ±1.5%
Output current
50 mA
Ambient temperature
85°C
Detailed Design Procedure
ON/
OFF Input Operation
J
Changed layout of National Semiconductor Data Sheet to TI format
yes
The LP2982 is shut off by pulling the ON/
OFF input low, and turned on by driving the input high. If this
feature is not to be used, the ON/OFF input required to be tied to VIN to keep
the regulator on at all times (the ON/ OFF input must not be
left floating).
For proper operation of the LDO, the signal source
used to drive the ON/ OFF input must be able to swing above and below
the specified turnon/turnoff voltage thresholds which specify an ON or
OFF state.
The ON/ OFF signal can come
from either a totem-pole output, or an open-collector output with pullup resistor to the
LP2982 input voltage or another logic supply. The high-level voltage can exceed the LP2982
input voltage, but must remain within the absolute maximum ratings for the ON/
OFF pin.
It is also important that the turnon/turnoff voltage signals applied to the ON/
OFF input have a slew rate which is greater than 40 mV/μs.
IMPORTANT: For the legacy chip, the
regulator shutdown function does not operate correctly if a slow-moving signal
is applied to the ON/ OFF input.
Application Curves
5-V,
2.2-μF ESR Curves (Legacy chip)
VIN = 6 V
3-V, 4.7-μF ESR Curves (Legacy chip)
VIN = 4 V
Line
Transient Response (Legacy chip)
Line
Transient Response (Legacy chip)
Line Transient Response
(New Chip)
VOUT = 3.3 V, ΔVIN = 1 V,
IOUT = 50 mA, dV/dt = 1 V/μs
Load
Transient Response (Legacy chip)
Load
Transient Response (Legacy chip)
Load
Transient Response (Legacy chip)
Load
Transient Response (Legacy chip)
Load Transient Response
(New Chip)
dI/dt = 1 A/μs
Turnon Waveform (Legacy chip)
Turnon Waveform (Legacy chip)
Turnon Waveform (Legacy chip)
Turnon Waveform (New
chip)
Cbyp = 0 nF
Turnon Waveform (New
chip)
Cbyp = 0.1 nF
Turnon Waveform (New
chip)
Cbyp = 1 nF
Typical Application
LP2982
Typical Application
ON/
OFF input must be actively terminated. Tie to
VIN if this function is not to be used. Minimum output
capacitance is shown to insure stability over full load current range. More
capacitance provides better dynamic performance and additional stability margin
(see
).
LP2982
Typical Application
ON/
OFF input must be actively terminated. Tie to
VIN if this function is not to be used. Minimum output
capacitance is shown to insure stability over full load current range. More
capacitance provides better dynamic performance and additional stability margin
(see
).
LP2982
Typical Application
ON/
OFF input must be actively terminated. Tie to
VIN if this function is not to be used. Minimum output
capacitance is shown to insure stability over full load current range. More
capacitance provides better dynamic performance and additional stability margin
(see
).
LP2982
Typical Application ON/
OFF input must be actively terminated. Tie to
VIN if this function is not to be used. Minimum output
capacitance is shown to insure stability over full load current range. More
capacitance provides better dynamic performance and additional stability margin
(see
).OFFIN
Design Requirements
PARAMETER
DESIGN REQUIREMENT
Input voltage
12 V ±10%
Output voltage
3.3 V ±1.5%
Output current
50 mA
Ambient temperature
85°C
Design Requirements
PARAMETER
DESIGN REQUIREMENT
Input voltage
12 V ±10%
Output voltage
3.3 V ±1.5%
Output current
50 mA
Ambient temperature
85°C
PARAMETER
DESIGN REQUIREMENT
Input voltage
12 V ±10%
Output voltage
3.3 V ±1.5%
Output current
50 mA
Ambient temperature
85°C
PARAMETER
DESIGN REQUIREMENT
Input voltage
12 V ±10%
Output voltage
3.3 V ±1.5%
Output current
50 mA
Ambient temperature
85°C
PARAMETER
DESIGN REQUIREMENT
Input voltage
12 V ±10%
Output voltage
3.3 V ±1.5%
Output current
50 mA
Ambient temperature
85°C
PARAMETER
DESIGN REQUIREMENT
PARAMETER
DESIGN REQUIREMENT
PARAMETERDESIGN REQUIREMENT
Input voltage
12 V ±10%
Output voltage
3.3 V ±1.5%
Output current
50 mA
Ambient temperature
85°C
Input voltage
12 V ±10%
Input voltage12 V ±10%
Output voltage
3.3 V ±1.5%
Output voltage3.3 V ±1.5%
Output current
50 mA
Output current50 mA
Ambient temperature
85°C
Ambient temperature85°C
Detailed Design Procedure
ON/
OFF Input Operation
J
Changed layout of National Semiconductor Data Sheet to TI format
yes
The LP2982 is shut off by pulling the ON/
OFF input low, and turned on by driving the input high. If this
feature is not to be used, the ON/OFF input required to be tied to VIN to keep
the regulator on at all times (the ON/ OFF input must not be
left floating).
For proper operation of the LDO, the signal source
used to drive the ON/ OFF input must be able to swing above and below
the specified turnon/turnoff voltage thresholds which specify an ON or
OFF state.
The ON/ OFF signal can come
from either a totem-pole output, or an open-collector output with pullup resistor to the
LP2982 input voltage or another logic supply. The high-level voltage can exceed the LP2982
input voltage, but must remain within the absolute maximum ratings for the ON/
OFF pin.
It is also important that the turnon/turnoff voltage signals applied to the ON/
OFF input have a slew rate which is greater than 40 mV/μs.
IMPORTANT: For the legacy chip, the
regulator shutdown function does not operate correctly if a slow-moving signal
is applied to the ON/ OFF input.
Detailed Design Procedure
ON/
OFF Input Operation
J
Changed layout of National Semiconductor Data Sheet to TI format
yes
The LP2982 is shut off by pulling the ON/
OFF input low, and turned on by driving the input high. If this
feature is not to be used, the ON/OFF input required to be tied to VIN to keep
the regulator on at all times (the ON/ OFF input must not be
left floating).
For proper operation of the LDO, the signal source
used to drive the ON/ OFF input must be able to swing above and below
the specified turnon/turnoff voltage thresholds which specify an ON or
OFF state.
The ON/ OFF signal can come
from either a totem-pole output, or an open-collector output with pullup resistor to the
LP2982 input voltage or another logic supply. The high-level voltage can exceed the LP2982
input voltage, but must remain within the absolute maximum ratings for the ON/
OFF pin.
It is also important that the turnon/turnoff voltage signals applied to the ON/
OFF input have a slew rate which is greater than 40 mV/μs.
IMPORTANT: For the legacy chip, the
regulator shutdown function does not operate correctly if a slow-moving signal
is applied to the ON/ OFF input.
ON/
OFF Input OperationOFF
J
Changed layout of National Semiconductor Data Sheet to TI format
yes
J
Changed layout of National Semiconductor Data Sheet to TI format
yes
J
Changed layout of National Semiconductor Data Sheet to TI format
yes
JChanged layout of National Semiconductor Data Sheet to TI formatyes
The LP2982 is shut off by pulling the ON/
OFF input low, and turned on by driving the input high. If this
feature is not to be used, the ON/OFF input required to be tied to VIN to keep
the regulator on at all times (the ON/ OFF input must not be
left floating).
For proper operation of the LDO, the signal source
used to drive the ON/ OFF input must be able to swing above and below
the specified turnon/turnoff voltage thresholds which specify an ON or
OFF state.
The ON/ OFF signal can come
from either a totem-pole output, or an open-collector output with pullup resistor to the
LP2982 input voltage or another logic supply. The high-level voltage can exceed the LP2982
input voltage, but must remain within the absolute maximum ratings for the ON/
OFF pin.
It is also important that the turnon/turnoff voltage signals applied to the ON/
OFF input have a slew rate which is greater than 40 mV/μs.
IMPORTANT: For the legacy chip, the
regulator shutdown function does not operate correctly if a slow-moving signal
is applied to the ON/ OFF input.
The LP2982 is shut off by pulling the ON/
OFF input low, and turned on by driving the input high. If this
feature is not to be used, the ON/OFF input required to be tied to VIN to keep
the regulator on at all times (the ON/ OFF input must not be
left floating).
For proper operation of the LDO, the signal source
used to drive the ON/ OFF input must be able to swing above and below
the specified turnon/turnoff voltage thresholds which specify an ON or
OFF state.
The ON/ OFF signal can come
from either a totem-pole output, or an open-collector output with pullup resistor to the
LP2982 input voltage or another logic supply. The high-level voltage can exceed the LP2982
input voltage, but must remain within the absolute maximum ratings for the ON/
OFF pin.
It is also important that the turnon/turnoff voltage signals applied to the ON/
OFF input have a slew rate which is greater than 40 mV/μs.
IMPORTANT: For the legacy chip, the
regulator shutdown function does not operate correctly if a slow-moving signal
is applied to the ON/ OFF input.
The LP2982 is shut off by pulling the ON/
OFF input low, and turned on by driving the input high. If this
feature is not to be used, the ON/OFF input required to be tied to VIN to keep
the regulator on at all times (the ON/ OFF input must not be
left floating).OFFINOFFnotFor proper operation of the LDO, the signal source
used to drive the ON/ OFF input must be able to swing above and below
the specified turnon/turnoff voltage thresholds which specify an ON or
OFF state.OFFOFFThe ON/ OFF signal can come
from either a totem-pole output, or an open-collector output with pullup resistor to the
LP2982 input voltage or another logic supply. The high-level voltage can exceed the LP2982
input voltage, but must remain within the absolute maximum ratings for the ON/
OFF pin.OFFOFFIt is also important that the turnon/turnoff voltage signals applied to the ON/
OFF input have a slew rate which is greater than 40 mV/μs.OFF
IMPORTANT: For the legacy chip, the
regulator shutdown function does not operate correctly if a slow-moving signal
is applied to the ON/ OFF input.
IMPORTANT: For the legacy chip, the
regulator shutdown function does not operate correctly if a slow-moving signal
is applied to the ON/ OFF input.IMPORTANTOFF
Application Curves
5-V,
2.2-μF ESR Curves (Legacy chip)
VIN = 6 V
3-V, 4.7-μF ESR Curves (Legacy chip)
VIN = 4 V
Line
Transient Response (Legacy chip)
Line
Transient Response (Legacy chip)
Line Transient Response
(New Chip)
VOUT = 3.3 V, ΔVIN = 1 V,
IOUT = 50 mA, dV/dt = 1 V/μs
Load
Transient Response (Legacy chip)
Load
Transient Response (Legacy chip)
Load
Transient Response (Legacy chip)
Load
Transient Response (Legacy chip)
Load Transient Response
(New Chip)
dI/dt = 1 A/μs
Turnon Waveform (Legacy chip)
Turnon Waveform (Legacy chip)
Turnon Waveform (Legacy chip)
Turnon Waveform (New
chip)
Cbyp = 0 nF
Turnon Waveform (New
chip)
Cbyp = 0.1 nF
Turnon Waveform (New
chip)
Cbyp = 1 nF
Application Curves
5-V,
2.2-μF ESR Curves (Legacy chip)
VIN = 6 V
3-V, 4.7-μF ESR Curves (Legacy chip)
VIN = 4 V
Line
Transient Response (Legacy chip)
Line
Transient Response (Legacy chip)
Line Transient Response
(New Chip)
VOUT = 3.3 V, ΔVIN = 1 V,
IOUT = 50 mA, dV/dt = 1 V/μs
Load
Transient Response (Legacy chip)
Load
Transient Response (Legacy chip)
Load
Transient Response (Legacy chip)
Load
Transient Response (Legacy chip)
Load Transient Response
(New Chip)
dI/dt = 1 A/μs
Turnon Waveform (Legacy chip)
Turnon Waveform (Legacy chip)
Turnon Waveform (Legacy chip)
Turnon Waveform (New
chip)
Cbyp = 0 nF
Turnon Waveform (New
chip)
Cbyp = 0.1 nF
Turnon Waveform (New
chip)
Cbyp = 1 nF
5-V,
2.2-μF ESR Curves (Legacy chip)
VIN = 6 V
3-V, 4.7-μF ESR Curves (Legacy chip)
VIN = 4 V
Line
Transient Response (Legacy chip)
Line
Transient Response (Legacy chip)
Line Transient Response
(New Chip)
VOUT = 3.3 V, ΔVIN = 1 V,
IOUT = 50 mA, dV/dt = 1 V/μs
Load
Transient Response (Legacy chip)
Load
Transient Response (Legacy chip)
Load
Transient Response (Legacy chip)
Load
Transient Response (Legacy chip)
Load Transient Response
(New Chip)
dI/dt = 1 A/μs
Turnon Waveform (Legacy chip)
Turnon Waveform (Legacy chip)
Turnon Waveform (Legacy chip)
Turnon Waveform (New
chip)
Cbyp = 0 nF
Turnon Waveform (New
chip)
Cbyp = 0.1 nF
Turnon Waveform (New
chip)
Cbyp = 1 nF
5-V,
2.2-μF ESR Curves (Legacy chip)
VIN = 6 V
3-V, 4.7-μF ESR Curves (Legacy chip)
VIN = 4 V
Line
Transient Response (Legacy chip)
Line
Transient Response (Legacy chip)
Line Transient Response
(New Chip)
VOUT = 3.3 V, ΔVIN = 1 V,
IOUT = 50 mA, dV/dt = 1 V/μs
Load
Transient Response (Legacy chip)
Load
Transient Response (Legacy chip)
Load
Transient Response (Legacy chip)
Load
Transient Response (Legacy chip)
Load Transient Response
(New Chip)
dI/dt = 1 A/μs
Turnon Waveform (Legacy chip)
Turnon Waveform (Legacy chip)
Turnon Waveform (Legacy chip)
Turnon Waveform (New
chip)
Cbyp = 0 nF
Turnon Waveform (New
chip)
Cbyp = 0.1 nF
Turnon Waveform (New
chip)
Cbyp = 1 nF
5-V,
2.2-μF ESR Curves (Legacy chip)
VIN = 6 V
5-V,
2.2-μF ESR Curves (Legacy chip)
VIN = 6 V
VIN = 6 V
VIN = 6 V
VIN = 6 V
VIN = 6 V
VIN = 6 VIN
3-V, 4.7-μF ESR Curves (Legacy chip)
VIN = 4 V
3-V, 4.7-μF ESR Curves (Legacy chip)
VIN = 4 V
VIN = 4 V
VIN = 4 V
VIN = 4 V
VIN = 4 V
VIN = 4 VIN
Line
Transient Response (Legacy chip)
Line
Transient Response (Legacy chip)
Line
Transient Response (Legacy chip)
Line
Transient Response (Legacy chip)
Line Transient Response
(New Chip)
VOUT = 3.3 V, ΔVIN = 1 V,
IOUT = 50 mA, dV/dt = 1 V/μs
Line Transient Response
(New Chip)
VOUT = 3.3 V, ΔVIN = 1 V,
IOUT = 50 mA, dV/dt = 1 V/μs
VOUT = 3.3 V, ΔVIN = 1 V,
IOUT = 50 mA, dV/dt = 1 V/μs
VOUT = 3.3 V, ΔVIN = 1 V,
IOUT = 50 mA, dV/dt = 1 V/μs
VOUT = 3.3 V, ΔVIN = 1 V,
IOUT = 50 mA, dV/dt = 1 V/μs
VOUT = 3.3 V, ΔVIN = 1 V,
IOUT = 50 mA, dV/dt = 1 V/μs
VOUT = 3.3 V, ΔVIN = 1 V,
IOUT = 50 mA, dV/dt = 1 V/μsOUTINOUT
Load
Transient Response (Legacy chip)
Load
Transient Response (Legacy chip)
Load
Transient Response (Legacy chip)
Load
Transient Response (Legacy chip)
Load
Transient Response (Legacy chip)
Load
Transient Response (Legacy chip)
Load
Transient Response (Legacy chip)
Load
Transient Response (Legacy chip)
Load Transient Response
(New Chip)
dI/dt = 1 A/μs
Load Transient Response
(New Chip)
dI/dt = 1 A/μs
dI/dt = 1 A/μs
dI/dt = 1 A/μs
dI/dt = 1 A/μs
dI/dt = 1 A/μs
dI/dt = 1 A/μs
Turnon Waveform (Legacy chip)
Turnon Waveform (Legacy chip)
Turnon Waveform (Legacy chip)
Turnon Waveform (Legacy chip)
Turnon Waveform (Legacy chip)
Turnon Waveform (Legacy chip)
Turnon Waveform (New
chip)
Cbyp = 0 nF
Turnon Waveform (New
chip)
Cbyp = 0 nF
Cbyp = 0 nF
Cbyp = 0 nF
Cbyp = 0 nF
Cbyp = 0 nF
Cbyp = 0 nFbyp
Turnon Waveform (New
chip)
Cbyp = 0.1 nF
Turnon Waveform (New
chip)
Cbyp = 0.1 nF
Cbyp = 0.1 nF
Cbyp = 0.1 nF
Cbyp = 0.1 nF
Cbyp = 0.1 nF
Cbyp = 0.1 nFbyp
Turnon Waveform (New
chip)
Cbyp = 1 nF
Turnon Waveform (New
chip)
Cbyp = 1 nF
Cbyp = 1 nF
Cbyp = 1 nF
Cbyp = 1 nF
Cbyp = 1 nF
Cbyp = 1 nFbyp
Power Supply Recommendations
The LP2982 is designed to operate
from an input voltage supply range between between VOUT(NOM) + 1 V
and 16 V. The input voltage range provides adequate headroom for the device to
have a regulated output. This input supply must be well regulated. If the input
supply is noisy, additional input capacitors with low ESR can help improve the
output noise performance.
Power Supply Recommendations
The LP2982 is designed to operate
from an input voltage supply range between between VOUT(NOM) + 1 V
and 16 V. The input voltage range provides adequate headroom for the device to
have a regulated output. This input supply must be well regulated. If the input
supply is noisy, additional input capacitors with low ESR can help improve the
output noise performance.
The LP2982 is designed to operate
from an input voltage supply range between between VOUT(NOM) + 1 V
and 16 V. The input voltage range provides adequate headroom for the device to
have a regulated output. This input supply must be well regulated. If the input
supply is noisy, additional input capacitors with low ESR can help improve the
output noise performance.
The LP2982 is designed to operate
from an input voltage supply range between between VOUT(NOM) + 1 V
and 16 V. The input voltage range provides adequate headroom for the device to
have a regulated output. This input supply must be well regulated. If the input
supply is noisy, additional input capacitors with low ESR can help improve the
output noise performance.
The LP2982 is designed to operate
from an input voltage supply range between between VOUT(NOM) + 1 V
and 16 V. The input voltage range provides adequate headroom for the device to
have a regulated output. This input supply must be well regulated. If the input
supply is noisy, additional input capacitors with low ESR can help improve the
output noise performance.OUT(NOM)
Layout
Layout Guidelines
For best overall performance, place all circuit
components on the same side of the circuit board and as near as practical to the respective
LDO pin connections. Place ground return connections to the input and output capacitors, and
to the LDO ground pin as close to each other as possible, connected by a wide,
component-side, copper surface. The use of vias and long traces to create LDO circuit
connections is strongly discouraged and negatively affects system performance. This
grounding and layout scheme minimizes inductive parasitics, and thereby reduces load-current
transients, minimizes noise, and increases circuit stability. A ground reference plane is
also recommended and is either embedded in the PCB itself or located on the bottom side of
the PCB opposite the components. This reference plane serves for better accuracy of the
output voltage, shield noise, and behaves similar to a thermal plane to spread (or sink)
heat from the LDO device. In most applications, this ground plane is necessary to meet
thermal requirements.
Layout Example
LP2982 Layout Example
Layout
Layout Guidelines
For best overall performance, place all circuit
components on the same side of the circuit board and as near as practical to the respective
LDO pin connections. Place ground return connections to the input and output capacitors, and
to the LDO ground pin as close to each other as possible, connected by a wide,
component-side, copper surface. The use of vias and long traces to create LDO circuit
connections is strongly discouraged and negatively affects system performance. This
grounding and layout scheme minimizes inductive parasitics, and thereby reduces load-current
transients, minimizes noise, and increases circuit stability. A ground reference plane is
also recommended and is either embedded in the PCB itself or located on the bottom side of
the PCB opposite the components. This reference plane serves for better accuracy of the
output voltage, shield noise, and behaves similar to a thermal plane to spread (or sink)
heat from the LDO device. In most applications, this ground plane is necessary to meet
thermal requirements.
Layout Guidelines
For best overall performance, place all circuit
components on the same side of the circuit board and as near as practical to the respective
LDO pin connections. Place ground return connections to the input and output capacitors, and
to the LDO ground pin as close to each other as possible, connected by a wide,
component-side, copper surface. The use of vias and long traces to create LDO circuit
connections is strongly discouraged and negatively affects system performance. This
grounding and layout scheme minimizes inductive parasitics, and thereby reduces load-current
transients, minimizes noise, and increases circuit stability. A ground reference plane is
also recommended and is either embedded in the PCB itself or located on the bottom side of
the PCB opposite the components. This reference plane serves for better accuracy of the
output voltage, shield noise, and behaves similar to a thermal plane to spread (or sink)
heat from the LDO device. In most applications, this ground plane is necessary to meet
thermal requirements.
For best overall performance, place all circuit
components on the same side of the circuit board and as near as practical to the respective
LDO pin connections. Place ground return connections to the input and output capacitors, and
to the LDO ground pin as close to each other as possible, connected by a wide,
component-side, copper surface. The use of vias and long traces to create LDO circuit
connections is strongly discouraged and negatively affects system performance. This
grounding and layout scheme minimizes inductive parasitics, and thereby reduces load-current
transients, minimizes noise, and increases circuit stability. A ground reference plane is
also recommended and is either embedded in the PCB itself or located on the bottom side of
the PCB opposite the components. This reference plane serves for better accuracy of the
output voltage, shield noise, and behaves similar to a thermal plane to spread (or sink)
heat from the LDO device. In most applications, this ground plane is necessary to meet
thermal requirements.
For best overall performance, place all circuit
components on the same side of the circuit board and as near as practical to the respective
LDO pin connections. Place ground return connections to the input and output capacitors, and
to the LDO ground pin as close to each other as possible, connected by a wide,
component-side, copper surface. The use of vias and long traces to create LDO circuit
connections is strongly discouraged and negatively affects system performance. This
grounding and layout scheme minimizes inductive parasitics, and thereby reduces load-current
transients, minimizes noise, and increases circuit stability. A ground reference plane is
also recommended and is either embedded in the PCB itself or located on the bottom side of
the PCB opposite the components. This reference plane serves for better accuracy of the
output voltage, shield noise, and behaves similar to a thermal plane to spread (or sink)
heat from the LDO device. In most applications, this ground plane is necessary to meet
thermal requirements.
Layout Example
LP2982 Layout Example
Layout Example
LP2982 Layout Example
LP2982 Layout Example
LP2982 Layout Example
LP2982 Layout Example
Device and Documentation Support
Device Nomenclature
O
Added Device Nomenclature section
yes
Available Options
PRODUCT
VOUT
LP2982cxxxzX-y.y/NOPBLegacy chip
c is the accuracy specification.
xxx is the
package designator.
z is the package quantity.
X is for a large-quantity reel and non-X is for a
small-quantity reel.
y.y is the nominal output
voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V).
LP2982AxxxzX-y.y/M3
New chip
A is for
higher accuracy and non-A is for standard grade.
xxx is the package designator.
z is the package quantity.
X is for a large-quantity reel and non-X is for a
small-quantity reel
y.y is the nominal output
voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V).
M3 is a suffix designator for newer chip redesigns, fabricated on the
latest TI process technology.
Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A
WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN
COMBINATION WITH ANY TI PRODUCT OR SERVICE.
Documentation Support
Related Documentation
For additional information, see the following:
TI Application Report Semiconductor and IC Package Thermal Metrics (SPRA953)
TI Application Report Using New Thermal Metrics (SBVA025)
TI Application Report Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs (SZZA017)
Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
Support Resources
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are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick
design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute
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Trademarks
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Device and Documentation Support
Device Nomenclature
O
Added Device Nomenclature section
yes
Available Options
PRODUCT
VOUT
LP2982cxxxzX-y.y/NOPBLegacy chip
c is the accuracy specification.
xxx is the
package designator.
z is the package quantity.
X is for a large-quantity reel and non-X is for a
small-quantity reel.
y.y is the nominal output
voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V).
LP2982AxxxzX-y.y/M3
New chip
A is for
higher accuracy and non-A is for standard grade.
xxx is the package designator.
z is the package quantity.
X is for a large-quantity reel and non-X is for a
small-quantity reel
y.y is the nominal output
voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V).
M3 is a suffix designator for newer chip redesigns, fabricated on the
latest TI process technology.
Device Nomenclature
O
Added Device Nomenclature section
yes
O
Added Device Nomenclature section
yes
O
Added Device Nomenclature section
yes
OAdded Device Nomenclature sectionDevice Nomenclatureyes
Available Options
PRODUCT
VOUT
LP2982cxxxzX-y.y/NOPBLegacy chip
c is the accuracy specification.
xxx is the
package designator.
z is the package quantity.
X is for a large-quantity reel and non-X is for a
small-quantity reel.
y.y is the nominal output
voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V).
LP2982AxxxzX-y.y/M3
New chip
A is for
higher accuracy and non-A is for standard grade.
xxx is the package designator.
z is the package quantity.
X is for a large-quantity reel and non-X is for a
small-quantity reel
y.y is the nominal output
voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V).
M3 is a suffix designator for newer chip redesigns, fabricated on the
latest TI process technology.
Available Options
PRODUCT
VOUT
LP2982cxxxzX-y.y/NOPBLegacy chip
c is the accuracy specification.
xxx is the
package designator.
z is the package quantity.
X is for a large-quantity reel and non-X is for a
small-quantity reel.
y.y is the nominal output
voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V).
LP2982AxxxzX-y.y/M3
New chip
A is for
higher accuracy and non-A is for standard grade.
xxx is the package designator.
z is the package quantity.
X is for a large-quantity reel and non-X is for a
small-quantity reel
y.y is the nominal output
voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V).
M3 is a suffix designator for newer chip redesigns, fabricated on the
latest TI process technology.
Available Options
PRODUCT
VOUT
LP2982cxxxzX-y.y/NOPBLegacy chip
c is the accuracy specification.
xxx is the
package designator.
z is the package quantity.
X is for a large-quantity reel and non-X is for a
small-quantity reel.
y.y is the nominal output
voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V).
LP2982AxxxzX-y.y/M3
New chip
A is for
higher accuracy and non-A is for standard grade.
xxx is the package designator.
z is the package quantity.
X is for a large-quantity reel and non-X is for a
small-quantity reel
y.y is the nominal output
voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V).
M3 is a suffix designator for newer chip redesigns, fabricated on the
latest TI process technology.
Available Options
PRODUCT
VOUT
LP2982cxxxzX-y.y/NOPBLegacy chip
c is the accuracy specification.
xxx is the
package designator.
z is the package quantity.
X is for a large-quantity reel and non-X is for a
small-quantity reel.
y.y is the nominal output
voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V).
LP2982AxxxzX-y.y/M3
New chip
A is for
higher accuracy and non-A is for standard grade.
xxx is the package designator.
z is the package quantity.
X is for a large-quantity reel and non-X is for a
small-quantity reel
y.y is the nominal output
voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V).
M3 is a suffix designator for newer chip redesigns, fabricated on the
latest TI process technology.
PRODUCT
VOUT
PRODUCT
VOUT
PRODUCTVOUT
OUT
LP2982cxxxzX-y.y/NOPBLegacy chip
c is the accuracy specification.
xxx is the
package designator.
z is the package quantity.
X is for a large-quantity reel and non-X is for a
small-quantity reel.
y.y is the nominal output
voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V).
LP2982AxxxzX-y.y/M3
New chip
A is for
higher accuracy and non-A is for standard grade.
xxx is the package designator.
z is the package quantity.
X is for a large-quantity reel and non-X is for a
small-quantity reel
y.y is the nominal output
voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V).
M3 is a suffix designator for newer chip redesigns, fabricated on the
latest TI process technology.
LP2982cxxxzX-y.y/NOPBLegacy chip
c is the accuracy specification.
xxx is the
package designator.
z is the package quantity.
X is for a large-quantity reel and non-X is for a
small-quantity reel.
y.y is the nominal output
voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V).
LP2982cxxxzX-y.y/NOPBLegacy chip
cxxxzXy.yLegacy chip
c is the accuracy specification.
xxx is the
package designator.
z is the package quantity.
X is for a large-quantity reel and non-X is for a
small-quantity reel.
y.y is the nominal output
voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V).cxxxzXy.y
LP2982AxxxzX-y.y/M3
New chip
A is for
higher accuracy and non-A is for standard grade.
xxx is the package designator.
z is the package quantity.
X is for a large-quantity reel and non-X is for a
small-quantity reel
y.y is the nominal output
voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V).
M3 is a suffix designator for newer chip redesigns, fabricated on the
latest TI process technology.
LP2982AxxxzX-y.y/M3
New chip
LP2982AxxxzX-y.y/M3
AxxxzXy.yM3New chip
A is for
higher accuracy and non-A is for standard grade.
xxx is the package designator.
z is the package quantity.
X is for a large-quantity reel and non-X is for a
small-quantity reel
y.y is the nominal output
voltage (for example, 3.3 = 3.3 V; 5.0 = 5.0 V).
M3 is a suffix designator for newer chip redesigns, fabricated on the
latest TI process technology.AxxxzXy.yM3
Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A
WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN
COMBINATION WITH ANY TI PRODUCT OR SERVICE.
Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A
WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN
COMBINATION WITH ANY TI PRODUCT OR SERVICE.
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A
WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN
COMBINATION WITH ANY TI PRODUCT OR SERVICE.
Documentation Support
Related Documentation
For additional information, see the following:
TI Application Report Semiconductor and IC Package Thermal Metrics (SPRA953)
TI Application Report Using New Thermal Metrics (SBVA025)
TI Application Report Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs (SZZA017)
Documentation Support
Related Documentation
For additional information, see the following:
TI Application Report Semiconductor and IC Package Thermal Metrics (SPRA953)
TI Application Report Using New Thermal Metrics (SBVA025)
TI Application Report Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs (SZZA017)
Related Documentation
For additional information, see the following:
TI Application Report Semiconductor and IC Package Thermal Metrics (SPRA953)
TI Application Report Using New Thermal Metrics (SBVA025)
TI Application Report Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs (SZZA017)
For additional information, see the following:
TI Application Report Semiconductor and IC Package Thermal Metrics (SPRA953)
TI Application Report Using New Thermal Metrics (SBVA025)
TI Application Report Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs (SZZA017)
For additional information, see the following:
TI Application Report Semiconductor and IC Package Thermal Metrics (SPRA953)
TI Application Report Using New Thermal Metrics (SBVA025)
TI Application Report Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs (SZZA017)
TI Application Report Semiconductor and IC Package Thermal Metrics (SPRA953)Semiconductor and IC Package Thermal MetricsSPRA953TI Application Report Using New Thermal Metrics (SBVA025)Using New Thermal MetricsSBVA025TI Application Report Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs (SZZA017)Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB DesignsSZZA017
Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
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Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
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Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
TI Glossary
TI GlossaryThis glossary lists and explains terms, acronyms, and definitions.
Revision History
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Revision History
yes
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Dec 2023
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yesJune 2016Dec 2023KL
Revision History
yes
April 2013
June 2016
J
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Revision History
yes
April 2013
June 2016
J
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yes
April 2013
June 2016
J
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yesApril 2013June 2016JK
yes
April 2013
April 2013
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yes
April 2013
April 2013
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yes
April 2013
April 2013
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yesApril 2013April 2013IJ
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The following pages include
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of this data sheet, refer to the left-hand navigation.
The following pages include
mechanical, packaging, and orderable information. This information is the most
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Mailing Address:
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Copyright © 2023, Texas Instruments Incorporated
Mailing Address:
Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated
Mailing Address:
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Copyright © 2023, Texas Instruments Incorporated table.
The output voltage is not regulated
when the device is in current limit. When a current limit event occurs, the device
begins to heat up because of the increase in power dissipation. When the device is
in brick-wall current limit, the pass transistor dissipates power [(VIN –
VOUT) × ICL]. If thermal shutdown is triggered, the device
turns off. After the device cools down, the internal thermal shutdown circuit turns
the device back on. If the output current fault condition continues, the device
cycles between current limit and thermal shutdown. For more information on current
limits, see the Know Your Limits application note.
Figure 6-1 shows a diagram
of the current limit.
Figure 6-1 Current
Limit