SNVS170D October   2001  – April 2016 LP2983

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 High-Accuracy Output Voltage
      2. 7.3.2 Low Ground Current
      3. 7.3.3 Reverse Input-Output Voltage
      4. 7.3.4 ON/OFF Input Operation
      5. 7.3.5 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VO(NOM) + 1 V ≤ VIN < 16 V
      2. 7.4.2 Operation With ON/OFF Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Capacitors
          1. 8.2.2.1.1 Input Capacitor
          2. 8.2.2.1.2 Output Capacitors
        2. 8.2.2.2 Capacitor Characteristics
        3. 8.2.2.3 Power Dissipation
        4. 8.2.2.4 Estimating Junction Temperature
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LP2983 is a linear voltage regulator operating from 2.2 V to 16 V on the input and regulates voltages between ≤ 1.2 V with high accuracy and a 150-mA maximum output current. To achieve high efficiency, the dropout voltage (VIN – VOUT) must be as small as possible. Successfully implementing an LDO in an application depends on the application requirements. If the requirements are simply input voltage and output voltage, compliance specifications (such as internal power dissipation or stability) must be verified to ensure performance.

8.2 Typical Application

LP2983 typapp2_snvs170.gif
*ON/OFF input must be actively terminated. Tie to VIN if this function is not to be used.
**Minimum capacitance is shown to ensure stability (may be increased without limit). A ceramic capacitor is required for output (see External Capacitors).
Figure 23. LP2983 Typical Application

8.2.1 Design Requirements

For typical voltage regulator applications, use the parameters listed in Table 1:

Table 1. Design Parameters

PARAMETER DESIGN REQUIREMENT
Input voltage 2.2 V to 16 V
Output voltage 1V or 1.2 V
Output current 0 mA to 150 mA
Output tolerance (1 mA ≤ IL ≤ 50 mA at 25°C) ±1.5% (±1% with A-grade version)

8.2.2 Detailed Design Procedure

8.2.2.1 External Capacitors

Like any low-dropout regulator, the LP2983 requires external capacitors for regulator stability. These capacitors must be correctly selected for good performance.

8.2.2.1.1 Input Capacitor

An input capacitor whose capacitance is ≥ 1 µF is required between the LP2983 input and ground (the amount of capacitance may be increased without limit).

This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean analog ground. Any good-quality ceramic, tantalum, or film capacitor may be used at the input.

NOTE

Tantalum capacitors can suffer catastrophic failure due to surge current when connected to a low-impedance source of power (like a battery or very large capacitor). If a tantalum capacitor is used at the input, it must be ensured by the manufacturer to have a surge current rating sufficient for the application.

There are no requirements for ESR on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the capacitor to ensure the capacitance is ≥ 1 µF over the entire operating temperature range.

8.2.2.1.2 Output Capacitors

The LP2983 is designed specifically to work with ceramic output capacitors, utilizing circuitry which allows the regulator to be stable across the entire range of output current with an output capacitor whose ESR is as low as 0 Ω.

The ceramic output capacitor must be connected between the OUT pin (device pin 5) and the ESR pin (device pin 4) (see Figure 24).

LP2983 20029120.png Figure 24. Ceramic to ESR Pin (COUT = 2.2 µF)

The LP2983 requires a minimum of 2.2 µF on the output (output capacitor size can be increased without limit).

It is important to remember that capacitor tolerance and variation with temperature must be taken into consideration when selecting an output capacitor so that the minimum required amount of output capacitance is provided over the full operating temperature range. Note that ceramic capacitors can exhibit large changes in capacitance with temperature (see Capacitor Characteristics).

The output capacitor must be located not more than 1 cm from the output pin and returned to a clean analog ground via the ESR pin.

8.2.2.2 Capacitor Characteristics

The LP2983 was designed to work with ceramic capacitors on the output to take advantage of the benefits they offer: for capacitance values in the 2.2-µF to 4.7-µF range, ceramics are the least expensive and also have the lowest ESR values (which makes them best for eliminating high-frequency noise).

One disadvantage of ceramic capacitors is that their capacitance can vary with temperature. Most large value ceramic capacitors (≥ 2.2 µF) are manufactured with the Z5U or Y5V temperature characteristic, which results in the capacitance dropping by more than 50% as the temperature goes from 25°C to 85°C.

This could cause problems if a 2.2-µF capacitor were used on the output since it will drop down to approximately 1 µF at high ambient temperatures (which could cause the LP2983 to oscillate). If Z5U or Y5V capacitors are used on the output, a minimum capacitance value of 4.7 µF must be observed.

A better choice for temperature coefficient in ceramic capacitors is X7R, which holds the capacitance within ±15%. Unfortunately, the larger values of capacitance are not offered by all manufacturers in the X7R dielectric.

8.2.2.3 Power Dissipation

Knowing the device power dissipation and proper sizing of the thermal plane connected to the tab or pad is critical to ensuring reliable operation. Device power dissipation depends on input voltage, output voltage, and load conditions and can be calculated with Equation 1.

Equation 1. PD(MAX) = (VIN(MAX) – VOUT) × IOUT

Power dissipation can be minimized, and greater efficiency can be achieved, by using the lowest available voltage drop option that would still be greater than the dropout voltage (VDO). However, keep in mind that higher voltage drops result in better dynamic (that is, PSRR and transient) performance.

On the SOT-23 (DBV) package, the primary conduction path for heat is through the pins to the PCB. The maximum allowable junction temperature (TJ(MAX))determines maximum power dissipation allowed (PD(MAX)) for the device package.

Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient air (TA), according to Equation 2 or Equation 3:

Equation 2. TJ(MAX) = TA(MAX) + (RθJA × PD(MAX))
Equation 3. PD = TJ(MAX) – TA(MAX) / RθJA

Unfortunately, this RθJA is highly dependent on the heat-spreading capability of the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The RθJA recorded in Thermal Information is determined by the specific EIA/JEDEC JESD51-7 standard for PCB and copper-spreading area, and is to be used only as a relative measure of package thermal performance. For a well-designed thermal layout, RθJA is actually the sum of the package junction-to-case (bottom) thermal resistance (RθJCbot) plus the thermal resistance contribution by the PCB copper area acting as a heat sink.

8.2.2.4 Estimating Junction Temperature

The EIA/JEDEC standard recommends the use of psi (Ψ) thermal characteristics to estimate the junction temperatures of surface mount devices on a typical PCB board application. These characteristics are not true thermal resistance values, but rather package specific thermal characteristics that offer practical and relative means of estimating junction temperatures. These psi metrics are determined to be significantly independent of copper-spreading area. The key thermal characteristics (ΨJT and ΨJB) are given in Thermal Information and are used in accordance with Equation 4 or Equation 5.

Equation 4. TJ(MAX) = TTOP + (ΨJT × PD(MAX))

where

  • PD(MAX) is explained in Equation 3
  • TTOP is the temperature measured at the center-top of the device package.
Equation 5. TJ(MAX) = TBOARD + (ΨJB × PD(MAX))

where

  • PD(MAX) is explained in Equation 3.
  • TBOARD is the PCB surface temperature measured 1-mm from the device package and centered on the package edge.

For more information about the thermal characteristics ΨJT and ΨJB, see Semiconductor and IC Package Thermal Metrics (SPRA953); for more information about measuring TTOP and TBOARD, see Using New Thermal Metrics (SBVA025); and for more information about the EIA/JEDEC JESD51 PCB used for validating RθJA, see Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs (SZZA017). These application notes are available at www.ti.com.

8.2.3 Application Curves

Unless otherwise specified, CIN = 1 μF, COUT = 2.2 μF, VIN = VOUT(NOM) + 1, TA = 25°C, ON/OFF pin is tied to VIN..
LP2983 20029113.png
Figure 25. Line Transient Response
LP2983 20029126.png
Figure 26. Load Transient Response