SNVS539H November 2007 – September 2015 LP38500-ADJ , LP38502-ADJ
PRODUCTION DATA.
TI's FlexCap low-dropout (LDO) linear regulators feature unique compensation that allow use of any type of output capacitor with no limits on minimum or maximum equivalent series resistance (ESR). The LP38500 and LP38502 series of LDOs operates from a 2.7-V to 5.5-V input supply. These ultra-low-dropout linear regulators respond very quickly to step changes in load, making them suitable for low-voltage microprocessor applications. Developed on a CMOS process (utilizing a PMOS pass transistor) the LP38500-ADJ and LP38502-ADJ have low quiescent currents that changes little with load current.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LP38500 LP38502 |
DDPAK/TO-263 (5) | 10.16 mm x 8.42 mm |
TO-263 (5) | 10.16 mm x 9.85 mm | |
WSON (8) | 3.00 mm x 2.50 mm |
Changes from G Revision (June 2015) to H Revision
Changes from F Revision (April 2013) to G Revision
Changes from E Revision (April 2013) to F Revision
PIN | TYPE | DESCRIPTION | |||
---|---|---|---|---|---|
NAME | KTT | NDQ | NGS | ||
ADJ | 5 | 5 | 8 | O | Sets output voltage |
EN | 1 | 1 | 2 | I | Enable (LP38502-ADJ only). Pull high to enable the output, low to disable the output. This pin has no internal bias and must be either tied to the input voltage, or actively driven. |
GND | 3 | 3 | 1 | G | Ground |
IN | — | — | 2 | I | Input supply (LP38500-ADJ only). Input supply pins share current and must be connected together on the PC board. |
IN | 2 | 2 | 3, 4 | I | Input supply. Input Supply pins share current and must be connected together on the PC board. |
N/C | 1 | 1 | — | — | In the LP38500-ADJ, this pin has no internal connections. It can be left floating or used for trace routing. |
OUT | 4 | 4 | 5, 6, 7 | O | Regulated output voltage. Output pins share current and must be connected together on the PC board. |
DAP | √ | √ | √ | — | The DAP is used to remove heat from the device by conducting it to a copper clad area on the PCB which acts as a heatsink. The DAP is electrically connected to the backside of the die. The DAP must be connected to ground potential, but can not be used as the only ground connection. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Input pin voltage (survival) | −0.3 | 6 | V | |
Enable pin voltage (survival) | −0.3 | 6 | V | |
Output pin voltage (survival) | −0.3 | 6 | V | |
IOUT (survival) | Internally limited | |||
Power dissipation(3) | Internally limited | |||
Storage temperature, Tstg | −65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
VESD | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Input supply voltage | 2.7 | 5.5 | V | ||
Enable input voltage | 0 | 5.5 | V | ||
Output current (DC) | 0 | 1.5 | A | ||
VOUT | 0.6 | 5 | V | ||
Junction temperature(1) | −40 | 125 | °C |
THERMAL METRIC(1) | LP38500 and LP38502 | UNIT | |||
---|---|---|---|---|---|
KTT(DDPAK/TO-263) | NDQ (TO-263) | NGS (WSON) | |||
5 PINS | 5 PINS | 8 PINS | |||
RθJA(2) | Junction-to-ambient thermal resistance | 41.8 | 33.3 | 52.5(3) | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 45.0 | 22.1 | 53.6 | °C/W |
RθJB | Junction-to-board thermal resistance | 24.8 | 16.9 | 26.1 | °C/W |
ψJT | Junction-to-top characterization parameter | 13.1 | 5.8 | 0.6 | °C/W |
ψJB | Junction-to-board characterization parameter | 23.8 | 16.8 | 26.3 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 2.4 | 2.3 | 7.4 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VADJ | Adjust pin voltage(1) | 2.7 V ≤ VIN ≤ 5.5 V 10 mA ≤ IOUT ≤ 1.5 A TJ = 25°C |
0.584 | 0.605 | 0.626 | V |
2.7 V ≤ VIN ≤ 5.5 V 10 mA ≤ IOUT ≤ 1.5 A |
0.575 | 0.635 | ||||
VADJ | Adjust pin voltage (A grade)(1) | 2.7 V ≤ VIN ≤ 5.5 V 10 mA ≤ IOUT ≤ 1.5 A TJ = 25°C |
0.596 | 0.605 | 0.614 | V |
2.7 V ≤ VIN ≤ 5.5 V 10 mA ≤ IOUT ≤ 1.5 A |
0.587 | 0.623 | ||||
IADJ | ADJUST pin bias current | 2.7 V ≤ VIN ≤ 5.5 V TJ = 25°C |
50 | nA | ||
2.7 V ≤ VIN ≤ 5.5 V | 750 | nA | ||||
VDO | Dropout voltage(2) | IOUT = 1.5 A TJ = 25°C |
220 | 275 | mV | |
IOUT = 1.5 A | 375 | mV | ||||
ΔVOUT / ΔVIN | Output voltage line regulation(1)(3) | 2.7 V ≤ VIN ≤ 5.5 V TJ = 25°C |
0.04 | %/V | ||
2.7 V ≤ VIN ≤ 5.5 V | 0.05 | %/V | ||||
ΔVOUT / ΔIOUT | Output voltage load regulation(1) (4) | 10 mA < IOUT < 1.5 A TJ = 25°C |
0.18 | %/A | ||
10 mA < IOUT < 1.5 A | 0.33 | %/A | ||||
IGND | Ground pin current in normal operation mode | 10 mA < IOUT < 1.5 A TJ = 25°C |
2 | 3.5 | mA | |
10 mA < IOUT < 1.5 A | 4.5 | |||||
IDISABLED | Ground pin current | VEN < VIL(EN), TJ = 25°C | 0.025 | 0.125 | µA | |
VEN < VIL(EN) | 15 | |||||
IOUT(PK)GND | Peak output current | VOUT ≥ VOUT(NOM) – 5% | 3.6 | A | ||
ISC | Short-circuit current | VOUT = 0 V, TJ = 25°C | 3.7 | A | ||
VOUT = 0 V | 2 | |||||
ENABLE INPUT (LP38502 Only) | ||||||
VIH(EN) | Enable logic high | VOUT = ON | 1.4 | V | ||
VIL(EN) | Enable logic low | VOUT = OFF | 0.65 | V | ||
td(off) | Turnoff delay | Time from VEN < VIL(EN) to VOUT = OFF ILOAD = 1.5 A |
25 | µs | ||
td(on) | Turnon delay | Time from VEN >VIH(EN) to VOUT = ON ILOAD = 1.5A |
25 | µs | ||
IIH(EN) | Enable pin high current | VEN = VIN | 1 | nA | ||
IIL(EN) | Enable pin low current | VEN = 0 V | 0.1 | |||
AC PARAMETERS | ||||||
PSRR | Ripple rejection | VIN = 3 V, IOUT = 1.5 A, ƒ = 120 Hz | 58 | dB | ||
VIN = 3 V, IOUT = 1.5 A, ƒ = 1 kHz | 56 | |||||
ρn(l/f) | Output noise density | ƒ = 120 Hz, COUT = 10 µF CER | 1 | µV/√Hz | ||
en | Output noise voltage | BW = 100 Hz – 100 kHz COUT = 10 µF CER |
100 | µV(rms) | ||
THERMALS | ||||||
TSD | Thermal shutdown | TJ rising | 170 | — | °C | |
ΔTSD | Thermal shutdown hysteresis | TJ falling from TSD | 10 | — | °C |