7.3.1 Stability And Phase Margin

Any regulator which operates using a feedback loop must be compensated in such a way as to ensure adequate phase margin, which is defined as the difference between the phase shift and –180 degrees at the frequency where the loop gain crosses unity (0 dB). For most LDO regulators, the ESR of the output capacitor is required to create a zero to add enough phase lead to ensure stable operation. The LP38500-ADJ and LP38502-ADJ each have a unique internal compensation circuit which maintains phase margin regardless of the ESR of the output capacitor, so any type of capacitor may be used.

Figure 14 shows the gain/phase plot of the LP38500-ADJ and LP38502-ADJ with an output of 1.2 V, a 10-µF ceramic output capacitor, delivering 1.5 A of load current. It can be seen that the unity-gain crossover occurs at 150 kHz, and the phase margin is about 40° (which is very stable).

Figure 14. Gain-Bandwidth Plot for 1.5-A Load

Figure 15 shows the gain and phase with no external load. In this case, the only load is provided by the gain setting resistors (about 12 kΩ total in this test). It is immediately obvious that the unity-gain frequency is significantly lower (dropping to about 500 Hz), at which point the phase margin is 125°.

Figure 15. Gain-Bandwidth Plot for No Load

The reduction in unity-gain bandwidth as load current is reduced is normal for any LDO regulator using a P-FET or PNP pass transistor, because they have a pole in the loop gain function given by:

Equation 1.

This illustrates how the pole goes to the highest frequency when R_L is minimum value (maximum load current). In general, LDOs have maximum bandwidth (and lowest phase margin) at full load current. In the case of the LP38500-ADJ or LP38502-ADJ, it can be seen that it has good phase margin even when using ceramic capacitors with ESR values of only a few mΩ.

7.3.2 Load Transient Response

Load transient response is defined as the change in regulated output voltage which occurs as a result of a change in load current. Many applications have loads which vary, and the control loop of the voltage regulator must adjust the current in the pass FET transistor in response to load current changes. For this reason, regulators with wider bandwidths often have better transient response.

The LP38500-ADJ and LP38502-ADJ employs an internal feed-forward design which makes the load transient response much faster than would be predicted simply by loop speed: this feedforward means any voltage changes appearing on the output are coupled through to the high-speed driver used to control the gate of the pass FET along a signal path using very fast FET devices. Because of this, the pass transistor’s current can change very quickly.

Figure 15 shows the output voltage load transient which occurs on a 1.8-V output when the load changes from 0.1 A to 1.5 A at an average slew rate of 0.5 A/µs. As shown, the peak output voltage change from nominal is about 40 mV, which is about 2.2%.

Figure 16. Load Transient Response

In cases where extremely fast load changes occur, the output capacitance may have to be increased. For fast changing loads, the internal parasitics of ESR (equivalent series resistance) and ESL (equivalent series inductance) degrade the capacitor’s ability to source current quickly to the load. The best capacitor types for transient performance are (in order):

1. Multilayer Ceramic: with the lowest values of ESR and ESL, they can have ESR values in the range of a few mΩ. Disadvantage: capacitance values above about 22 µF significantly increase in cost.
2. Low-ESR Aluminum Electrolytics: these are aluminum types (like OSCON) with a special electrolyte which provides extremely low ESR values, and are the closest to ceramic performance while still providing large amounts of capacitance. These are cheaper (by capacitance) than ceramic.
3. Solid tantalum: can provide several hundred µF of capacitance, transient performance is slightly worse than OSCON type capacitors, cheaper than ceramic in large values.
4. General purpose aluminum electrolytics: cheap and provide a lot of capacitance, but give the worst performance.

In general, managing load transients is done by paralleling ceramic capacitance with a larger bulk capacitance. In this way, the ceramic can source current during the rapidly changing edge and the bulk capacitor can support the load current after the first initial spike in current.

7.3.3 Dropout Voltage

The dropout voltage of a regulator is defined as the input-to-output differential required by the regulator to keep the output voltage within 2% of the nominal value. For CMOS LDOs, the dropout voltage is the product of the load current and the R_DS(on) of the internal MOSFET pass element.

Since the output voltage is beginning to “drop out” of regulation when it drops by 2%, electrical performance of the device will be reduced compared to the values listed in the Electrical Characteristics table for some parameters (line and load regulation and PSRR would be affected).

7.3.4 Reverse Current Path

The internal MOSFET pass element in the LP38500-ADJ and LP38502-ADJ has an inherent parasitic diode. During normal operation, the input voltage is higher than the output voltage and the parasitic diode is reverse biased. However, if the output is pulled above the input in an application, then current flows from the output to the input as the parasitic diode gets forward biased. The output can be pulled above the input as long as the current in the parasitic diode is limited to 200-mA continuous and 1-A peak. The regulator output pin should not be taken below ground potential. If the LP38500-ADJ and LP38502-ADJ is used in a dual-supply system where the regulator load is returned to a negative supply, the output must be diode-clamped to ground.

7.4.1 Short-Circuit Protection

The LP38500-ADJ and LP38502-ADJ contain internal current limiting which will reduce output current to a safe value if the output is overloaded or shorted. Depending upon the value of V_IN, thermal limiting may also become active as the average power dissipated causes the die temperature to increase to the limit value (about 170°C). The hysteresis of the thermal shutdown circuitry can result in a “cyclic” behavior on the output as the die temperature heats and cools.

7.4.2 Enable Operation (LP38502-ADJ Only)

The Enable pin (EN) must be actively terminated by either a 10-kΩ pull-up resistor to V_IN, or a driver which actively pulls high and low (such as a CMOS rail to rail comparator). If active drive is used, the pull-up resistor is not required. This pin must be tied to V_IN if not used (it must not be left floating).