SNVS539H November   2007  – September 2015 LP38500-ADJ , LP38502-ADJ

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configurations and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Stability And Phase Margin
      2. 7.3.2 Load Transient Response
      3. 7.3.3 Dropout Voltage
      4. 7.3.4 Reverse Current Path
    4. 7.4 Device Functional Modes
      1. 7.4.1 Short-Circuit Protection
      2. 7.4.2 Enable Operation (LP38502-ADJ Only)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Capacitors
        2. 8.2.2.2 Input Capacitor
        3. 8.2.2.3 Output Capacitor
        4. 8.2.2.4 Setting The Output Voltage
        5. 8.2.2.5 RFI/EMI Susceptibility
        6. 8.2.2.6 Output Noise
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Dissipation/Heatsinking
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Printed Circuit Board Layout
    2. 10.2 Layout Examples
      1. 10.2.1 Heatsinking WSON Package
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
      2. 11.1.2 Related Links
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

10.1.1 Printed Circuit Board Layout

Good layout practices will minimize voltage error and prevent instability which can result from ground loops. The input and output capacitors should be directly connected to the device pins with short traces that have no other current flowing in them (Kelvin connect).

The best way to do this is to place the capacitors very near the device and make connections directly to the device pins via short traces on the top layer of the PCB. The regulator’s ground pin should be connected through vias to the internal or backside ground plane so that the regulator has a single point ground.

The external resistors which set the output voltage must also be located very near the device with all connections directly tied via short traces to the pins of the device (Kelvin connect). Do not connect the resistive divider to the load point or DC error will be induced.

10.2 Layout Examples

LP38500-ADJ LP38502-ADJ 38500_layout_snvs539.gif Figure 22. LP38500-ADJ TO-263 Layout (LP38500)
LP38500-ADJ LP38502-ADJ 38502_layout_snvs539.gif Figure 23. LP38502-ADJ TO-263 Layout
LP38500-ADJ LP38502-ADJ WSON_layout_snvs539.gif Figure 24. LP3850x WSON Layout

10.2.1 Heatsinking WSON Package

The junction-to-ambient thermal resistance for the WSON package is dependent on how much PCB copper is present to conduct heat away from the device. The LP38502SD-ADJ evaluation board (980600046-100) was tested and gave a result of about 52.5°C/W with a power dissipation of 1 W and no external airflow. This evaluation board is a two layer board using two ounce copper, and the copper area on topside for heatsinking is approximately two square inches. Multiple vias under the DAP also thermally connect to the backside layer which has about three square inches of copper dedicated to heatsinking.

With four thermal vias directly under the DAP to the first copper plane, the modeling predicts a RθJA of 52.5°C/W.

Adding a dog-bone copper area with four additional thermal vias in the dog-bone area to the first copper plane can improve RθJA to 45°C/W.

See Application Note AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Packages (SNVA183) for additional thermal considerations for printed circuit board layouts.