SNVSA55C December   2014  – January 2018 LP3907-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Circuit
  4. 4 Revision History
  5. 5 Device Comparison Tables
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions (Bucks)
    4. 7.4  Thermal Information
    5. 7.5  General Electrical Characteristics
    6. 7.6  Low Dropout Regulators, LDO1 And LDO2
    7. 7.7  Buck Converters SW1, SW2
    8. 7.8  I/O Electrical Characteristics
    9. 7.9  Power-On Reset (POR) Threshold/Function
    10. 7.10 I2C Interface Timing Requirements
    11. 7.11 Typical Characteristics — LDO
    12. 7.12 Typical Characteristics — Bucks
    13. 7.13 Typical Characteristics — Buck1
    14. 7.14 Typical Characteristics — Buck2
    15. 7.15 Typical Characteristics — Bucks
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DC-DC Converters
        1. 8.3.1.1 Linear Low Dropout Regulators (LDOs)
        2. 8.3.1.2 No-Load Stability
        3. 8.3.1.3 LDO and LDO2 Control Registers
      2. 8.3.2 SW1, SW2: Synchronous Step-Down Magnetic DC-DC Converters
        1. 8.3.2.1  Functional Description
        2. 8.3.2.2  Circuit Operation Description
        3. 8.3.2.3  PWM Operation
        4. 8.3.2.4  Internal Synchronous Rectification
        5. 8.3.2.5  Current Limiting
        6. 8.3.2.6  PFM Operation
        7. 8.3.2.7  SW1, SW2 Operation
        8. 8.3.2.8  SW1, SW2 Control Registers
        9. 8.3.2.9  Soft Start
        10. 8.3.2.10 Low Dropout Operation
        11. 8.3.2.11 Flexible Power Sequencing of Multiple Power Supplies
        12. 8.3.2.12 Power-Up Sequencing Using the EN_T Function
      3. 8.3.3 Flexible Power-On Reset (Power Good with Delay)
      4. 8.3.4 Undervoltage Lockout
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
    5. 8.5 Programming
      1. 8.5.1 I2C-Compatible Serial Interface
        1. 8.5.1.1 I2C Signals
        2. 8.5.1.2 I2C Data Validity
        3. 8.5.1.3 I2C Start and Stop Conditions
        4. 8.5.1.4 Transferring Data
      2. 8.5.2 Factory Programmable Options
    6. 8.6 Register Maps
      1. 8.6.1 LP3907-Q1 Control Registers
        1. 8.6.1.1  Interrupt Status Register (ISRA) 0x02
        2. 8.6.1.2  Control 1 Register (SCR1) 0x07
        3. 8.6.1.3  EN_DLY Preset Delay Sequence After EN_T Assertion
        4. 8.6.1.4  Buck and LDO Output Voltage Enable Register (BKLDOEN) – 0x10
        5. 8.6.1.5  Buck and LDO Status Register (BKLDOSR) – 0x11
        6. 8.6.1.6  Buck Voltage Change Control Register 1 (VCCR) – 0x20
        7. 8.6.1.7  Buck1 Target Voltage 1 Register (B1TV1) – 0x23
        8. 8.6.1.8  Buck1 Target Voltage 2 Register (B1TV2) – 0x24
        9. 8.6.1.9  Buck1 Ramp Control Register (B1RC) - 0x25
        10. 8.6.1.10 Buck2 Target Voltage 1 Register (B2TV1) – 0x29
        11. 8.6.1.11 Buck2 Target Voltage 2 Register (B2TV2) – 0x2A
        12. 8.6.1.12 Buck2 Ramp Control Register (B2RC) - 0x2B
        13. 8.6.1.13 Buck Function Register (BFCR) – 0x38
        14. 8.6.1.14 LDO1 Control Register (LDO1VCR) – 0x39
        15. 8.6.1.15 LDO2 Control Register (LDO2VCR) – 0x3A
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Component Selection
          1. 9.2.2.1.1 Inductors for SW1 And SW2
            1. 9.2.2.1.1.1 Method 1:
            2. 9.2.2.1.1.2 Method 2:
          2. 9.2.2.1.2 External Capacitors
        2. 9.2.2.2 LDO Capacitor Selection
          1. 9.2.2.2.1 Input Capacitor
          2. 9.2.2.2.2 Output Capacitor
          3. 9.2.2.2.3 Capacitor Characteristics
          4. 9.2.2.2.4 Input Capacitor Selection for SW1 And SW2
          5. 9.2.2.2.5 Output Capacitor Selection for SW1, SW2
          6. 9.2.2.2.6 I2C Pullup Resistor
        3. 9.2.2.3 Operation Without I2C Interface
          1. 9.2.2.3.1 High VIN High-Load Operation
          2. 9.2.2.3.2 Junction Temperature
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Analog Power Signal Routing
  11. 11Layout
    1. 11.1 DSBGA Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations of WQFN Package
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Trademarks
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

WQFN (RTW)
24 Leads
Top View
LP3907-Q1 30017803.gif
DSBGA (YZR)
25 Pins
Top View
LP3907-Q1 30017890.gif

Pin Functions

PIN I/OTYPE(1)DESCRIPTION
WQFN NUMBERDSBGA NUMBERNAME
1 B4, B5 VINLDO12 I PWR Analog Power for Internal Functions (VREF, BIAS, I2C, Logic)
2 C4 EN_T I D Enable for preset power on sequence. (See .)
3 C3 nPOR O D nPOR Power on reset pin for both Buck1 and Buck 2. Open drain logic output 100-kΩ pullup resistor. nPOR is pulled to ground when the voltages on these supplies are not good. See Flexible Power-On Reset (Power Good with Delay) section for more info.
4 C5 GND_SW1 G G Buck1 NMOS Power Ground
5 D5 SW1 O PWR Buck1 switcher output pin
6 E5 VIN1 I PWR Power in from either DC source or Battery to Buck1
7 D4 ENSW1 I D Enable Pin for Buck1 switcher, a logic HIGH enables Buck1
8 E4 FB1 I A Buck1 input feedback terminal
9 D3 GND_C G G Non switching core ground pin
10 E3 AVDD I PWR Analog Power for Buck converters
11 E2 FB2 I A Buck2 input feedback terminal
12 D2 ENSW2 I D Enable Pin for Buck2 switcher, a logic HIGH enables Buck2
13 E1 VIN2 I PWR Power in from either DC source or Battery to Buck2
14 D1 SW2 O PWR Buck2 switcher output pin
15 C1 GND_SW2 G G Buck2 NMOS Power ground
16 C2 SDA I/O D I2C Data (bidirectional)
17 B2 SCL I D I2C Clock
18 B1 GND_L G G LDO ground
19 A1 VINLDO1 I PWR Power in from either DC source or battery to input terminal to LDO1
20 A2 LDO1 O PWR LDO1 Output
21 B3 ENLDO1 I D LDO1 enable pin, a logic HIGH enables the LDO1
22 A3 ENLDO2 I D LDO2 enable pin, a logic HIGH enables the LDO2
23 A4 LDO2 O PWR LDO2 Output
24 A5 VINLDO2 I PWR Power in from either DC source or battery to input terminal to LDO2.
DAP DAP GND GND Connection isn't necessary for electrical performance, but it is recommended for better thermal dissipation.
(1) A: Analog Pin   D: Digital Pin   G: Ground Pin   PWR: Power Pin   I: Input Pin   I/O: Input/Output Pin   O: Output Pin.