7.3.1 Short-Circuit Protection

The LP3961 and LP3964 are short-circuit protected and in the event of a peak overcurrent condition, the short-circuit control loop will rapidly drive the output PMOS pass element off. Once the power pass element shuts down, the control loop will rapidly cycle the output on and off until the average power dissipation causes the thermal shutdown circuit to respond to servo the on/off cycling to a lower frequency. Please refer to the section on thermal information for power dissipation calculations.

7.3.2 ERROR Flag Operation

The LP3961 produces a logic low signal at the ERROR flag pin when the output drops out of regulation due to low input voltage, current limiting, or thermal limiting. This flag has a built-in hysteresis. The timing diagram in Figure 20 shows the relationship between the ERROR pin and the output voltage. In this example, the input voltage is changed to demonstrate the functionality of the ERROR flag.

The internal ERROR flag comparator has an open drain output stage. Hence, the ERROR pin should be pulled high through a pull-up resistor. Although the ERROR pin can sink current of 1 mA, this current is an energy drain from the input supply. Hence, the value of the pull-up resistor should be in the range of 100 kΩ to 1 MΩ. The ERROR pin must be connected to ground if this function is not used. It should also be noted that when the SD pin is pulled low, the ERROR pin is forced to be invalid for reasons of saving power in shutdown mode.

Figure 20. ERROR Flag Operation

7.3.3 SENSE Pin

In applications where the regulator output is not very close to the load, LP3964 can provide better remote load regulation using the SENSE pin. Figure 21 depicts the advantage of the SENSE option. LP3961 regulates the voltage at the OUT pin. Hence, the voltage at the remote load will be the regulator output voltage minus the drop across the trace resistance. For example, in the case of a 3.3-V output, if the trace resistance is 100 mΩ, the voltage at the remote load will be 3.22 V with 800 mA of load current, I_LOAD. The LP3964 regulates the voltage at the SENSE pin. Connecting the SENSE pin to the remote load will provide regulation at the remote load, as shown in Figure 21. If the sense option pin is not required, the SENSE pin must be connected to the OUT pin.

Figure 21. Improving Remote Load Regulation Using LP3964

7.3.4 Dropout Voltage

The dropout voltage of a regulator is defined as the minimum input-to-output differential required to stay within 2% of the output voltage. The LP3961 and LP3964 use an internal MOSFET with an Rds(on) of 240 mΩ (typically). For CMOS LDOs, the dropout voltage is the product of the load current and the Rds(on) of the internal MOSFET.

7.3.5 Reverse Current Path

The internal MOSFET in LP3961 and LP3964 has an inherent parasitic diode. During normal operation, the input voltage is higher than the output voltage and the parasitic diode is reverse biased. However, if the output is pulled above the input in an application, then current flows from the output to the input as the parasitic diode gets forward biased. The output can be pulled above the input as long as the current in the parasitic diode is limited to 200-mA continuous and 1-A peak.

7.4.1 Operation With V_OUT(TARGET) + 0.35 V ≤ V_IN ≤ 7 V

For the fixed output voltage products, the devices operate if the input voltage is equal to or exceeds V_OUT(TARGET) + 0.35 V. At input voltages below the minimum V_IN requirement, the devices do not operate correctly and output voltage may not reach target value.

7.4.2 Operation With Shutdown (SD) Pin Control

A CMOS logic low level signal at the shutdown (SD) pin will turn off the regulator. The SD pin must be actively terminated through a 10-kΩ pullup resistor for a proper operation. This pin must be tied to the IN pin if not used .