SNVS296J December   2006  – June 2016 LP3991

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Post-Buck Regulator
      2. 7.3.2 Maximum Supply Voltage and Thermal Considerations
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Capacitors
        2. 8.2.2.2 Input Capacitor
        3. 8.2.2.3 Output Capacitor
        4. 8.2.2.4 No-Load Stability
        5. 8.2.2.5 Capacitor Characteristics
        6. 8.2.2.6 Power Dissipation
        7. 8.2.2.7 Estimating Junction Temperature
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 DSBGA Mounting
    4. 10.4 DSBGA Light Sensitivity
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

YZR Package
4-Pin Thin DSBGA, Large Bump
LP3991 20110006.gif

Pin Functions

PIN I/O DESCRIPTION
NUMBER NAME
A1 GND — Common ground. Connect to pad.
A2 EN I Enable Input; enables the regulator when ≥ 0.95 V.
Disables the regulator when ≤ 0.4 V.
Enable input has an internal 1.2-MΩ pulldown resistor to GND.
B1 OUT O Voltage output. A low-ESR ceramic capacitor must be connected from this pin to GND (see Application and Implementation). Connect this output to the load circuit.
B2 IN I Voltage supply input. A 1-µF capacitor must be connected from this pin to GND.