SLDS269A March   2022  – May 2022 LP5891

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Independent and Stackable Mode
        1. 7.3.1.1 Independent Mode
        2. 7.3.1.2 Stackable Mode
      2. 7.3.2 Current Setting
        1. 7.3.2.1 Brightness Control (BC) Function
        2. 7.3.2.2 Color Brightness Control (CC) Function
        3. 7.3.2.3 Choosing BC/CC for a Different Application
      3. 7.3.3 Frequency Multiplier
      4. 7.3.4 Line Transitioning Sequence
      5. 7.3.5 Protections and Diagnostics
        1. 7.3.5.1 Thermal Shutdown Protection
        2. 7.3.5.2 IREF Resistor Short Protection
        3. 7.3.5.3 LED Open Load Detection and Removal
          1. 7.3.5.3.1 LED Open Detection
          2. 7.3.5.3.2 Read LED Open Information
          3. 7.3.5.3.3 LED Open Caterpillar Removal
        4. 7.3.5.4 LED Short and Weak Short Circuitry Detection and Removal
          1. 7.3.5.4.1 LED Short/Weak Short Detection
          2. 7.3.5.4.2 Read LED Short Information
          3. 7.3.5.4.3 LSD Caterpillar Removal
    4. 7.4 Device Functional Modes
    5. 7.5 Continuous Clock Series Interface
      1. 7.5.1 Data Validity
      2. 7.5.2 CCSI Frame Format
      3. 7.5.3 Write Command
        1. 7.5.3.1 Chip Index Write Command
        2. 7.5.3.2 VSYNC Write Command
        3. 7.5.3.3 MPSM Write Command
        4. 7.5.3.4 Standby Clear and Enable Command
        5. 7.5.3.5 Soft_Reset Command
        6. 7.5.3.6 Data Write Command
      4. 7.5.4 Read Command
    6. 7.6 PWM Grayscale Control
      1. 7.6.1 Grayscale Data Storage and Display
        1. 7.6.1.1 Memory Structure Overview
        2. 7.6.1.2 Details of Memory Bank
        3. 7.6.1.3 Write a Frame Data into Memory Bank
      2. 7.6.2 PWM Control for Display
    7. 7.7 Register Maps
      1. 7.7.1  FC0
      2. 7.7.2  FC1
      3. 7.7.3  FC2
      4. 7.7.4  FC3
      5. 7.7.5  FC4
      6. 7.7.6  FC14
      7. 7.7.7  FC15
      8. 7.7.8  FC16
      9. 7.7.9  FC17
      10. 7.7.10 FC18
      11. 7.7.11 FC19
      12. 7.7.12 FC20
      13. 7.7.13 FC21
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 System Structure
        2. 8.2.1.2 SCLK Frequency
        3. 8.2.1.3 Internal GCLK Frequency
        4. 8.2.1.4 Line Switch Time
        5. 8.2.1.5 Blank Time Removal
        6. 8.2.1.6 BC and CC
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Chip Index Command
        2. 8.2.2.2 FC Registers Settings
        3. 8.2.2.3 Grayscale Data Write
        4. 8.2.2.4 VSYNC Command
        5. 8.2.2.5 LED Open/Short Read
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7.5 FC4

FC4 is shown in Figure 7-33 and described in Table 7-11.

Figure 7-33 FC4 Register
47464544434241403938373635343332
RESERVEDDE_COUPLE3_EN DE_COUPLE3DE_COUPLE2FIRST_LINE_DIMCAURSE_BCAURSE_GCAURSE_R
R-000bR/W-0bR/W-1000bR/W-0bR/W-0000bR/W-0bR/W-0bR/W-0b
31302928272625242322212019181716
RESERVEDSR_ON_BSR_ON_GSR_ON_RSR_OFF_BSR_OFF_GSR_OFF_RFINE_BFINE_GFINE_R
R-0000bR/W-01bR/W-01bR/W-01bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
1514131211109876543210
RESERVEDSCAN_REVRESERVEDIMAXRESERVED
R-0bR/W-1bR-0000 0000 1111bR/W-0bR-0b
Table 7-11 FC4 Register Field Descriptions
BitFieldTypeResetDescription
0RESERVEDR0b
1IMAXR/W0bSet the maximum current of each channel
0b: 10mA maximum
01b: 20 mA maximum
13-2RESERVEDR0000 0000 1111b
14SCAN_REVR/W1bWhen 2 device stackable, the scan lines PCB layout is reversed. For the proper scan and SRAM read sequence, SCAN_REV register is provided.
0b: the PCB layout sequence is L0-L15, L16-L31.
1b: the PCB layout sequence is L0-L15, L31-L16.
15RESERVEDR0b
16FINE_RR/W0bEnable the Red brightness compensation level fine range
0b: disable
1b: enable
17FINE_GR/W0bEnable the Green brightness compensation level fine range
0b: disable
1b: enable
18FINE_BR/W0bEnable the Blue brightness compensation level fine range
0b: disable
1b: enable
19SR_OFF_RR/W0bSlew rate control function when Red turns off operation
0b: slow slew rate.
1b: fast slew rate.
20SR_OFF_GR/W0bSlew rate control function when Green turns off operation
0b: slow slew rate.
1b: fast slew rate.
21SR_OFF_BR/W0bSlew rate control function when Blue turns off operation
0b: slow slew rate.
1b: fast slew rate.
23-22SR_ON_RR/W01bSlew rate control function when Red turns on operation
00b: the slower slew rate.
01b: slow slew rate.
10b: fast slew rate.
11b: the faster slew rate.
25-24SR_ON_GR/W01bSlew rate control function when Green turns on operation
00b: the slower slew rate.
01b: slow slew rate.
10b: fast slew rate.
11b: the faster slew rate.
27-26SR_ON_BR/W01bSlew rate control function when Blue turns on operation
00b: the slower slew rate.
01b: slow slew rate.
10b: fast slew rate.
11b: the faster slew rate.
31-28RESERVEDR0000b
32CAURSE_RR/W0bEnable the Red brightness compensation level caurse range
0b: disable
1b: enable
33CAURSE_GR/W0bEnable the Green brightness compensation level caurse range
0b: disable
1b: enable
34CAURSE_BR/W0bEnable the Blue brightness compensation level caurse range
0b: disable
1b: enable
38-35FIRST_LINE_DIMR/W0000bAdjust the first line dim level
0000b: level 1
...
0111b: level 8
...
1111b: level 16
39DE_COUPLE2R/W0bDecoupling between ON and OFF channels
0b: disabled
1b: enabled
43-40DE_COUPLE3R/W1000bSet decoupling enhancement level
0000b: level 1
...
0111b: level 8
...
1111b: level 16
44DE_COUPLE3_ENR/W0bEnable decoupling enhancement
0b: disabled
1b: enabled
47-45RESERVEDR000b