SLVSHF3 October   2024 LP5899-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Internal Oscillator and Clocks
        1. 7.3.1.1 System Clock
        2. 7.3.1.2 Continuous Clock Serial Interface (CCSI) Clock
      2. 7.3.2 Continuous Clock Serial Interface (CCSI)
        1. 7.3.2.1 Command Format
        2. 7.3.2.2 Command Recognition and Synchronization
        3. 7.3.2.3 CCSI Command Queue
        4. 7.3.2.4 CCSI Start Bit and Check Bits Insertion and Removal
      3. 7.3.3 FIFO
        1. 7.3.3.1 FIFO level and Data Ready (DRDY) Interrupt
        2. 7.3.3.2 FIFO Clearance
      4. 7.3.4 Diagnostics
        1. 7.3.4.1  Undervoltage Lockout
        2. 7.3.4.2  Oscillator Fault Diagnostics
        3. 7.3.4.3  SPI Communications Loss
        4. 7.3.4.4  SPI Communications Error
          1. 7.3.4.4.1 Reset Timer
          2. 7.3.4.4.2 Chip Select (CS) Reset
          3. 7.3.4.4.3 CRC Error
          4. 7.3.4.4.4 Register write failure
        5. 7.3.4.5  CCSI Communications Loss
          1. 7.3.4.5.1 SIN Stuck-at Diagnostics
        6. 7.3.4.6  CCSI Communications Error
          1. 7.3.4.6.1 CHECK Bit Error
          2. 7.3.4.6.2 Data Integrity Diagnostics
          3. 7.3.4.6.3 CCSI Command Queue Overflow
        7. 7.3.4.7  FIFO Diagnostics
          1. 7.3.4.7.1 TXFIFO Overflow
          2. 7.3.4.7.2 TXFIFO Underflow
          3. 7.3.4.7.3 TXFIFO Single Error Detection (SED)
          4. 7.3.4.7.4 RXFIFO Overflow
          5. 7.3.4.7.5 RXFIFO Underflow
          6. 7.3.4.7.6 RXFIFO Single Error Detection (SED)
        8. 7.3.4.8  OTP CRC Error
        9. 7.3.4.9  Fault Masking
        10. 7.3.4.10 Diagnostics Table
    4. 7.4 Device Functional Modes
      1. 7.4.1 Unpowered
      2. 7.4.2 Initialization State
      3. 7.4.3 Normal State
      4. 7.4.4 Failsafe State
    5. 7.5 Programming
      1. 7.5.1 SPI Data Validity
      2. 7.5.2 Chip Select (CS) and SPI Reset Control
      3. 7.5.3 SPI Command Format
      4. 7.5.4 SPI Command Detail
    6. 7.6 Device Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Programming Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.2 Chip Select (CS) and SPI Reset Control

The CS signal provides the ability to gate any spurious clock and data pulses. A HIGH logic signal on CS blocks the peripheral to receive data. This prevents the SPI peripheral from losing synchronization with the controller. TI does not recommend that the CS always be tied to the active state.

If the SPI peripheral does ever lose synchronization with the controller, providing a HIGH logic signal on CS resets SPI peripheral including the bit counter. Another method is to stop the SCLK and wait longer than the setting of the field SPI_RST_TIMEOUT_CFG in the SPICTRL register. This timeout starts counting from the first rising clock edge of SCLK when the SPI peripheral is expecting the command word.