SNVSAT4A September   2017  – June 2021 LP873220-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Parameters
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DC/DC Converters
        1. 7.3.1.1 Overview
        2. 7.3.1.2 Transition Between PWM and PFM Modes
        3. 7.3.1.3 Buck Converter Load Current Measurement
        4. 7.3.1.4 Spread-Spectrum Mode
      2. 7.3.2  Sync Clock Functionality
      3. 7.3.3  Low-Dropout Linear Regulators (LDOs)
      4. 7.3.4  Power-Up
      5. 7.3.5  Regulator Control
        1. 7.3.5.1 Enabling and Disabling Regulators
        2. 7.3.5.2 Changing Output Voltage
      6. 7.3.6  Enable and Disable Sequences
      7. 7.3.7  Device Reset Scenarios
      8. 7.3.8  Diagnosis and Protection Features
        1. 7.3.8.1 Power-Good Information (PGOOD pin)
          1. 7.3.8.1.1 PGOOD Pin Gated Mode
          2. 7.3.8.1.2 PGOOD Pin Continuous Mode
          3. 7.3.8.1.3 PGOOD Pin Inactive Mode
        2. 7.3.8.2 Warnings for Diagnosis (Interrupt)
          1. 7.3.8.2.1 Output Power Limit
          2. 7.3.8.2.2 Thermal Warning
        3. 7.3.8.3 Protection (Regulator Disable)
          1. 7.3.8.3.1 Short-Circuit and Overload Protection
          2. 7.3.8.3.2 Overvoltage Protection
          3. 7.3.8.3.3 Thermal Shutdown
        4. 7.3.8.4 Fault (Power Down)
          1. 7.3.8.4.1 Undervoltage Lockout
      9. 7.3.9  Operation of the GPO Signals
      10. 7.3.10 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Auto-Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1  DEV_REV
        2. 7.6.1.2  OTP_REV
        3. 7.6.1.3  BUCK0_CTRL_1
        4. 7.6.1.4  BUCK0_CTRL_2
        5. 7.6.1.5  BUCK1_CTRL_1
        6. 7.6.1.6  BUCK1_CTRL_2
        7. 7.6.1.7  BUCK0_VOUT
        8. 7.6.1.8  BUCK1_VOUT
        9. 7.6.1.9  LDO0_CTRL
        10. 7.6.1.10 LDO1_CTRL
        11. 7.6.1.11 LDO0_VOUT
        12. 7.6.1.12 LDO1_VOUT
        13. 7.6.1.13 BUCK0_DELAY
        14. 7.6.1.14 BUCK1_DELAY
        15. 7.6.1.15 LDO0_DELAY
        16. 7.6.1.16 LDO1_DELAY
        17. 7.6.1.17 GPO_DELAY
        18. 7.6.1.18 GPO2_DELAY
        19. 7.6.1.19 GPO_CTRL
        20. 7.6.1.20 CONFIG
        21. 7.6.1.21 PLL_CTRL
        22. 7.6.1.22 PGOOD_CTRL_1
        23. 7.6.1.23 PGOOD_CTRL_2
        24. 7.6.1.24 PG_FAULT
        25. 7.6.1.25 RESET
        26. 7.6.1.26 INT_TOP_1
        27. 7.6.1.27 INT_TOP_2
        28. 7.6.1.28 INT_BUCK
        29. 7.6.1.29 INT_LDO
        30. 7.6.1.30 TOP_STAT
        31. 7.6.1.31 BUCK_STAT
        32. 7.6.1.32 LDO_STAT
        33. 7.6.1.33 TOP_MASK_1
        34. 7.6.1.34 TOP_MASK_2
        35. 7.6.1.35 BUCK_MASK
        36. 7.6.1.36 LDO_MASK
        37. 7.6.1.37 SEL_I_LOAD
        38. 7.6.1.38 I_LOAD_2
        39. 7.6.1.39 I_LOAD_1
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Inductor Selection
        2. 8.2.1.2 Buck Input Capacitor Selection
        3. 8.2.1.3 Buck Output Capacitor Selection
        4. 8.2.1.4 LDO Input Capacitor Selection
        5. 8.2.1.5 LDO Output Capacitor Selection
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, specified VVANA, VVIN_Bx, VVIN_LDOx, VVOUT_Bx, VVOUT_LDOx and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = VVIN_LDOx = 3.7 V, and VOUT = 1 V, unless otherwise noted(1)(2).
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
EXTERNAL COMPONENTS
CIN_BUCKInput filtering capacitance for buck regulatorsEffective capacitance, connected from VIN_Bx to PGND_Bx1.910µF
COUT_BUCKOutput filtering capacitance for buck regulatorsEffective capacitance 1022500µF
CPOL_BUCKPoint-of-load (POL) capacitance for buck regulatorsOptional POL capacitance22µF
COUT-TOTAL_BUCKBuck output capacitance, total (local and POL)Total output capacitance 500µF
CIN_LDOInput filtering capacitance for LDO regulatorsEffective capacitance, connected from VIN_LDOx to AGND. CIN_LDO must be at least two times larger than COUT_LDO0.62.2µF
COUT_LDOOutput filtering capacitance for LDO regulatorsEffective capacitance0.412.7µF
ESRCInput and output capacitor ESR[1-10] MHz210mΩ
LInductorInductance of the inductor0.47 µH
–30%30%
DCRLInductor DCR25mΩ
BUCK REGULATORS
V(VIN_Bx), V(VANA)Input voltage rangeVIN_Bx and VANA pins must be connected to the same supply line2.83.75.5V
VOUT_BxOutput voltageProgrammable voltage range0.713.36V
Step size, 0.7 V ≤ VOUT < 0.73 V10mV
Step size, 0.73 V ≤ VOUT < 1.4 V5
Step size, 1.4 V ≤ VOUT ≤ 3.36 V20
IOUT_BxOutput currentOutput current2(3)A
Input and Output voltage differenceMinimum voltage between V(VIN_Bx) and VOUT to fulfill the electrical characteristics0.8V
VOUT_Bx_DCDC output voltage accuracy, includes voltage reference, DC load and line regulations, process and temperatureForce PWM mode, VOUT < 1 V–2020mV
Force PWM mode, VOUT ≥ 1 V–2%2%
PFM mode, VOUT < 1 V, the average output voltage level is increased by max. 20 mV–2040mV
PFM mode, VOUT ≥ 1 V, the average output voltage level is increased by max. 20 mV–2%2% + 20 mV
Ripple voltagePWM mode10mVp-p
PFM mode, IOUT = 10 mA25
DCLNRDC line regulationIOUT = 1 A±0.05%/V
DCLDRDC load regulation in PWM modeVOUT_Bx = 1 V, IOUT from 0 to IOUT(max)0.3%
TLDSRTransient load step responseIOUT = 0.1 A to 2 A, TR = TF = 400 ns, PWM mode±55mV
TLNSRTransient line responseV(VIN_Bx) stepping 3 V ↔ 3.5 V, TR = TF = 10 µs, IOUT = IOUT(max)±10mV
ILIM FWDForward current limit per phase (peak for every switching cycle)Programmable range1.53A
Step size0.5
Accuracy, V(VIN_Bx) ≥ 3 V, ILIM = 3 A–5%7.5%20%
Accuracy, 2.8 V ≤ V(VIN_Bx) < 3 V, ILIM = 3 A–20%7.5%20%
ILIM NEGNegative current limit per phase1.62.03.0A
RDS(ON) HS FETOn-resistance, high-side FETEach phase, between VIN_Bx and SW_Bx pins (I = 1 A)50110mΩ
RDS(ON) LS FETOn-resistance, low-side FETEach phase, between SW_Bx and PGND_Bx pins (I = 1 A)4590mΩ
ƒSWSwitching frequencyPWM mode1.822.2MHz
Start-up time (soft start)From ENx to VOUT_Bx = 0.35 V (slew-rate control begins)120µs
Output voltage slew-rate(4)SLEW_RATEx[2:0] = 010, COUT-TOTAL_BUCK < 80 µF –15%1015%mV/µs
SLEW_RATEx[2:0] = 011, COUT-TOTAL_BUCK < 130 µF 7.5
SLEW_RATEx[2:0] = 100, COUT-TOTAL_BUCK < 250 µF 3.8
SLEW_RATEx[2:0] = 101, COUT-TOTAL_BUCK < 500 µF 1.9
SLEW_RATEx[2:0] = 110, COUT-TOTAL_BUCK < 500 µF 0.94
SLEW_RATEx[2:0] = 111, COUT-TOTAL_BUCK < 500 µF 0.47
IPFM-PWMPFM-to-PWM - current threshold(5)550mA
IPWM-PFMPWM-to-PFM - current threshold(5)290mA
RDIS_BxOutput pulldown resistanceRegulator disabled150250350Ω
Output voltage monitoring for PGOOD pin and for power-good InterruptV(VIN_Bx) and V(VANA) fixed 3.7 V
Overvoltage threshold (compared to DC output voltage level, VVOUT_Bx_DC)395064mV
Undervoltage threshold (compared to DC output voltage level, VVOUT_Bx_DC)–53–40–29
Deglitch time during operation and after voltage change415µs
Gating time for PGOOD signal after regulator enable or voltage changePGOOD_MODE = 0800µs
LDO REGULATORS
VIN_LDOxInput voltage range for LDO power inputsVIN_LDOx can be higher or lower than V(VANA)2.53.75.5V
VOUT_LDOxOutput voltageProgrammable voltage range0.83.3V
Step size0.1
IOUT_LDOxOutput current300mA
Dropout voltageV(VIN_LDOx) – V(VOUT_LDOx), IOUT = IOUT(max), Programmed output voltage is higher than V(VIN_LDOx)200mV
VOUT_LDO_DC DC output voltage accuracy, includes voltage reference, DC load and line regulations, process, temperature VOUT < 1 V –20 20 mV
VOUT ≥ 1 V–2%2%
DCLNRDC line regulationIOUT = 1 mA0.1%/V
DCLDRDC load regulationIOUT = 1 mA to IOUT(max)0.8%
TLDSRTransient load step responseIOUT = 1 mA to 300 mA, TR = TF = 1 µs–50/+40mV
TLNSRTransient line responseV(VIN_LDOx) stepping 3 V ↔ 3.5 V, TR = TF = 10 µs, IOUT = IOUT(max)±7mV
PSRRPower supply ripple rejectionƒ = 10 kHz, IOUT = IOUT(max)53dB
Noise10 Hz < F < 100 kHz, IOUT = IOUT(max)82µVrms
ISHORT(LDOx)LDO current limitVOUT = 0 V400500600mA
Start-up timeFrom enable to valid output voltage300µs
Slew rate during start-up15mV/µs
RDIS_LDOxOutput pulldown resistanceRegulator disabled150250350Ω
Output voltage monitoring for PGOOD pin and for power-good interruptOvervoltage monitoring, voltage rising (compared to DC output voltage level, VOUT_LDO_DC)106%108%110%
Overvoltage monitoring, hysteresis3%3.5%4%
Undervoltage monitoring, voltage falling (compared to DC output voltage level, VOUT_LDO_DC)90%92%94%
Undervoltage monitoring, hysteresis3%3.5%4%
Deglitch time during operation and after voltage change415µs
Gating time for PGOOD signal after regulator enable or voltage changePGOOD_MODE = 0800µs
EXTERNAL CLOCK AND PLL
fEXT_CLKExternal input clock(6)Nominal frequency124MHz
Nominal frequency step size1
Required accuracy from nominal frequency–30%10%
External clock detectionDelay for missing clock detection1.8µs
Delay and debounce for clock detection20
Clock change delay (internal to external)Delay from valid clock detection to use of external clock600µs
PLL output clock jitterCycle to cycle300ps, p-p
PROTECTION FUNCTIONS
Thermal warningTemperature rising, TDIE_WARN_LEVEL = 0115125135°C
Temperature rising, TDIE_WARN_LEVEL = 1127137147
Hysteresis20
Thermal shutdownTemperature rising140150160°C
Hysteresis20
VANAOVP VANA overvoltage Voltage rising 5.6 5.8 6.1 V
Voltage falling5.455.735.96
Hysteresis40mV
VANAUVLOVANA undervoltage lockoutVoltage rising2.512.632.75V
Voltage falling2.52.62.7
Buck short-circuit detectionThreshold280360440mV
LDO short-circuit detectionThreshold190300450mV
LOAD CURRENT MEASUREMENT FOR BUCK REGULATORS
Current measurement rangeMaximum code10.22A
ResolutionLSB20mA
Measurement accuracyIOUT > 1 A <10%
Measurement timePFM mode (automatically changing to PWM mode for the measurement)45µs
PWM mode4
CURRENT CONSUMPTION
Standby current consumption, regulators disabled9µA
Active current consumption, one buck regulator enabled in auto mode, internal RC oscillator, PGOOD monitoring enabled IOUT_Bx = 0 mA, not switching58µA
Active current consumption, two buck regulators enabled in auto mode, internal RC oscillator, PGOOD monitoring enabled IOUT_Bx = 0 mA, not switching100µA
Active current consumption during PWM operation, one buck regulator enabled IOUT_Bx = 0 mA15mA
Active current consumption during PWM operation, two buck regulators enabled IOUT_Bx = 0 mA30mA
LDO regulator enabledAdditional current consumption per LDO, IOUT_LDOx = 0 mA86µA
PLL and clock detector current consumptionfEXT_CLK = 1 MHz, Additional current consumption when enabled2mA
DIGITAL INPUT SIGNALS EN, SCL, SDA, CLKIN
VILInput low level0.4V
VIHInput high level1.2
VHYSHysteresis of Schmitt Trigger inputs1080200mV
EN/CLKIN pulldown resistanceEN_PD/CLKIN_PD = 1500kΩ
DIGITAL OUTPUT SIGNALS nINT, SDA
VOLOutput low levelnINT: ISOURCE = 2 mA0.4V
SDA: ISOURCE = 20 mA0.4V
RPExternal pullup resistor for nINTTo VIO Supply10kΩ
DIGITAL OUTPUT SIGNALS PGOOD, GPO, GPO2
VOLOutput low levelISOURCE = 2 mA0.4V
VOHOutput high level, configured to push-pullISINK = 2 mAVVANA – 0.4VVANAV
VPUSupply voltage for external pullup resistor, configured to open-drainVVANAV
RPUExternal pullup resistor, configured to open-drain10kΩ
ALL DIGITAL INPUTS
ILEAKInput currentAll logic inputs over pin voltage range−11µA
(1) All voltage values are with respect to network ground.
(2) Minimum (MIN) and Maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers are not verified, but do represent the most likely norm.
(3) The maximum output current can be limited by the forward current limit ILIM FWD. The power dissipation inside the die increases the junction temperature and limits the maximum current depending of the length of the current pulse, efficiency, board and ambient temperature.
(4) The slew-rate can be limited by the current limit (forward or negative current limit), output capacitance and load current.
(5) The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependent on the output voltage, input voltage and the inductor current level.
(6) The external clock frequency must be selected so that buck switching frequency is above 1.7 MHz.