SNVSAW2B April 2017 – December 2018 LP87524B-Q1 , LP87524J-Q1 , LP87524P-Q1
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
The output voltage of the regulator can be changed by the ENx pin (voltage levels defined by the BUCKx_VOUT and BUCKx_FLOOR_VOUT registers) or by writing to the BUCKx_VOUT and BUCKx_FLOOR_VOUT registers. The voltage change is always slew-rate controlled, 3.8 mV/µs. During voltage change the forced-PWM mode is used automatically. When the programmed output voltage is achieved, the mode becomes the one defined by the load current and the BUCKx_FPWM bit in BUCKx_CTRL1 register.
The Power-Good interrupt is generated when the output voltage reaches the programmed voltage level, as shown in Figure 9.