SNVSB22 March 2018 LP87561-Q1 , LP87562-Q1 , LP87563-Q1 , LP87564-Q1 , LP87565-Q1
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
Automotive Infotainment, Cluster, Radar, and Camera Power Applications
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The LP8756x-Q1 device is designed to meet the power-management requirements of the latest processors and platforms in various automotive power applications. The device contains four step-down DC/DC converter cores, which are configured as a 4-phase output, 3-phase and 1-phase outputs, 2-phase and 2-phase outputs, one 2-phase and two 1-phase outputs, or four 1-phase outputs. The device is controlled by an I2C-compatible serial interface and by enable signals.
The automatic pulse-width-modulation (PWM) to pulsed-frequency-modulation (PFM) operation (AUTO mode), together with the automatic phase adding and phase shedding, maximizes efficiency over a wide output-current range. The LP8756x-Q1 supports remote differential-voltage sensing for multiphase outputs to compensate IR drop between the regulator output and the point-of-load (POL) improving the accuracy of the output voltage. The switching clock can be forced to PWM mode and also synchronized to an external clock to minimize the disturbances.
The LP8756x-Q1 device supports load-current measurement without the addition of external current-sense resistors. The device also supports programmable start-up and shutdown delays and sequences synchronized to enable signals. The sequences can include GPIO signals to control external regulators, load switches, and processor reset. During start-up and voltage change, the device controls the output slew rate to minimize output-voltage overshoot and in-rush current.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
LP87561-Q1 | VQFN-HR (26) | 4.50 mm × 4.00 mm |
LP87562-Q1 | ||
LP87563-Q1 | ||
LP87564-Q1 | ||
LP87565-Q1 |
DATE | REVISION | NOTES |
---|---|---|
March 2018 | * | Initial Release |
PART NUMBER | DC/DC CONFIGURATIONS |
---|---|
LP87561-Q1 | One 4-phase output |
LP87562-Q1 | One 3-phase and one 1-phase outputs |
LP87563-Q1 | One 2-phase and two 1-phase outputs |
LP87564-Q1 | Four 1-phase outputs |
LP87565-Q1 | Two 2-phase outputs |
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | FB_B2 | A | Output voltage feedback (positive) for the BUCK2 converter. |
2 | EN3 | D/I/O | Programmable enable signal for the buck regulators (can be also configured to select between two buck output-voltage levels). This pin functions alternatively as GPIO3. |
3 | CLKIN | D/I | External clock input. Connect this pin to ground if the external clock is not used. |
4, 17, Thermal Pad | AGND | G | Ground |
5 | SCL | D/I | Serial interface clock input for I2C access. Connect this pin to a pullup resistor. |
6 | SDA | D/I/O | Serial interface data input and output for I2C access. Connect this pin to a pullup resistor. |
7 | EN1 | D/I/O | Programmable enable signal for the buck regulators (can be also configured to select between two buck output voltage levels). This pin functions alternatively as GPIO1. |
8 | FB_B0 | A | Output voltage feedback (positive) for the BUCK0 converter. |
9 | VIN_B0 | P | Input for the BUCK0 converter. The separate power pins, VIN_Bx, are not connected together internally. The VIN_Bx pins must be connected together in the application and be locally bypassed. |
10 | SW_B0 | A | BUCK0 switch node |
11 | PGND_B01 | G | Power ground for the BUCK0 and BUCK1 converters |
12 | SW_B1 | A | BUCK1 switch node |
13 | VIN_B1 | P | Input for the BUCK1 converter. The separate power pins, VIN_Bx, are not connected together internally. The VIN_Bx pins must be connected together in the application and be locally bypassed. |
14 | FB_B1 | A | Output voltage feedback (positive) for the BUCK1 converter. This pin functions alternatively as the output ground feedback (negative) for the BUCK0 converter. |
15 | EN2 | D/I/O | Programmable enable signal for the buck regulators (can be also configured to select between two buck output voltage levels). This pin functions alternatively as GPIO2. |
16 | PGOOD | D/O | Power-good indication signal |
18 | VANA | P | Supply voltage for the analog and digital blocks. This pin must be connected to the same node as VIN_Bx. |
19 | nINT | D/O | Open-drain interrupt output. This pin is active low. |
20 | NRST | D/I | Reset signal for the device |
21 | FB_B3 | A | Output voltage feedback (positive) for the BUCK3 converter. This pin functions alternatively as the output ground feedback (negative) for the BUCK2 converter. |
22 | VIN_B3 | P | Input for the BUCK3 converter. The separate power pins, VIN_Bx, are not connected together internally. The VIN_Bx pins must be connected together in the application and be locally bypassed. |
23 | SW_B3 | A | BUCK3 switch node |
24 | PGND_B23 | G | Power ground for the BUCK2 and BUCK3 converters |
25 | SW_B2 | A | BUCK2 switch node |
26 | VIN_B2 | P | Input for the BUCK2 converter. The separate power pins, VIN_Bx, are not connected together internally. The VIN_Bx pins must be connected together in the application and be locally bypassed. |