SNVSB22 March 2018 LP87561-Q1 , LP87562-Q1 , LP87563-Q1 , LP87564-Q1 , LP87565-Q1
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
Address: 0x15
D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
BUCK3_SHUTDOWN_DELAY[3:0] | BUCK3_STARTUP_DELAY[3:0] |
Bits | Field | Type | Default | Description |
---|---|---|---|---|
7:4 | BUCK3_SHUTDOWN_DELAY[3:0] | R/W | X | Shutdown delay of the BUCK3 regulator from the falling edge of the ENx signal (the DOUBLE_DELAY bit is set to 0h in the CONFIG register and the HALF_DELAY bit is set to 0h in the PGOOD_CTRL2 register). For other delay options, see the Start-Up and Shutdown Delays table.
0h = 0 ms 1h = 1 ms Fh = 15 ms |
3:0 | BUCK3_STARTUP_DELAY[3:0] | R/W | X | Startup delay of the BUCK3 regulator from the rising edge of the ENx signal (the DOUBLE_DELAY bit is set to 0h in the CONFIG register and the HALF_DELAY bit is set to 0h in the PGOOD_CTRL2 register). For other delay options, see the Start-Up and Shutdown Delays table.
0h = 0 ms 1h = 1 ms Fh = 15 ms |