SNVSC07A June   2021  – September 2022 LP876242-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
    1. 5.1 Digital Signal Descriptions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Internal Low Drop-Out Regulators (LDOVINT)
    6. 6.6  BUCK1, BUCK2, BUCK3, and BUCK4 Regulators
    7. 6.7  Reference Generator (REFOUT)
    8. 6.8  Monitoring Functions
    9. 6.9  Clocks, Oscillators, and DPLL
    10. 6.10 Thermal Monitoring and Shutdown
    11. 6.11 System Control Thresholds
    12. 6.12 Current Consumption
    13. 6.13 Digital Input Signal Parameters
    14. 6.14 Digital Output Signal Parameters
    15. 6.15 I/O Pullup and Pulldown Resistance
    16. 6.16 I2C Interface
    17. 6.17 Serial Peripheral Interface (SPI)
    18.     25
    19. 6.18 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage Monitor
      2. 7.3.2 Power Resources
        1. 7.3.2.1 Buck Regulators
          1. 7.3.2.1.1 BUCK Regulator Overview
          2. 7.3.2.1.2 Spread-Spectrum Mode
          3. 7.3.2.1.3 Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support
          4. 7.3.2.1.4 BUCK Output Voltage Setting
          5. 7.3.2.1.5 Sync Clock Functionality
        2. 7.3.2.2 Internal Low Dropout Regulator (LDOVINT)
      3. 7.3.3 Residual Voltage Checking
      4. 7.3.4 Output Voltage Monitor and PGOOD Generation
      5. 7.3.5 General-Purpose I/Os (GPIO Pins)
      6. 7.3.6 Thermal Monitoring
        1. 7.3.6.1 Thermal Warning Function
        2. 7.3.6.2 Thermal Shutdown
      7. 7.3.7 Interrupts
      8. 7.3.8 Watchdog (WD)
        1. 7.3.8.1 Watchdog Fail Counter and Status
        2. 7.3.8.2 Watchdog Start-Up and Configuration
        3. 7.3.8.3 MCU to Watchdog Synchronization
        4. 7.3.8.4 Watchdog Disable Function
        5. 7.3.8.5 Watchdog Sequence
        6. 7.3.8.6 Watchdog Trigger Mode
        7. 7.3.8.7 WatchDog Flow Chart and Timing Diagrams in Trigger Mode
        8.       55
        9. 7.3.8.8 Watchdog Question-Answer Mode
          1. 7.3.8.8.1 Watchdog Q&A Related Definitions
          2. 7.3.8.8.2 Question Generation
          3. 7.3.8.8.3 Answer Comparison
            1. 7.3.8.8.3.1 Sequence of the 2-bit Watchdog Answer Counter
            2. 7.3.8.8.3.2 Watchdog Sequence Events and Status Updates
            3. 7.3.8.8.3.3 Watchdog Q&A Sequence Scenarios
      9. 7.3.9 Error Signal Monitor (ESM)
        1. 7.3.9.1 ESM Error-Handling Procedure
        2. 7.3.9.2 Level Mode
        3.       66
        4. 7.3.9.3 PWM Mode
          1. 7.3.9.3.1 Good-Events and Bad-Events
          2. 7.3.9.3.2 ESM Error-Counter
            1. 7.3.9.3.2.1 ESM Start-Up in PWM Mode
          3. 7.3.9.3.3 ESM Flow Chart and Timing Diagrams in PWM Mode
          4.        72
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device State Machine
        1. 7.4.1.1 Fixed Device Power FSM
          1. 7.4.1.1.1 Register Resets and EEPROM read at INIT state
        2. 7.4.1.2 Pre-Configurable Mission States
          1. 7.4.1.2.1 PFSM Commands
            1. 7.4.1.2.1.1  REG_WRITE_IMM Command
            2. 7.4.1.2.1.2  REG_WRITE_MASK_IMM Command
            3. 7.4.1.2.1.3  REG_WRITE_MASK_PAGE0_IMM Command
            4. 7.4.1.2.1.4  REG_WRITE_BIT_PAGE0_IMM Command
            5. 7.4.1.2.1.5  REG_WRITE_WIN_PAGE0_IMM Command
            6. 7.4.1.2.1.6  REG_WRITE_VOUT_IMM Command
            7. 7.4.1.2.1.7  REG_WRITE_VCTRL_IMM Command
            8. 7.4.1.2.1.8  REG_WRITE_MASK_SREG Command
            9. 7.4.1.2.1.9  SREG_READ_REG Command
            10. 7.4.1.2.1.10 SREG_WRITE_IMM Command
            11. 7.4.1.2.1.11 WAIT Command
            12. 7.4.1.2.1.12 DELAY_IMM Command
            13. 7.4.1.2.1.13 DELAY_SREG Command
            14. 7.4.1.2.1.14 TRIG_SET Command
            15. 7.4.1.2.1.15 TRIG_MASK Command
            16. 7.4.1.2.1.16 END Command
          2. 7.4.1.2.2 Configuration Memory Organization and Sequence Execution
          3. 7.4.1.2.3 Mission State Configuration
          4. 7.4.1.2.4 Pre-Configured Hardware Transitions
            1. 7.4.1.2.4.1 ON Requests
            2. 7.4.1.2.4.2 OFF Requests
            3. 7.4.1.2.4.3 NSLEEP1 and NSLEEP2 Functions
            4. 7.4.1.2.4.4 WKUP1 and WKUP2 Functions
        3. 7.4.1.3 Error Handling Operations
          1. 7.4.1.3.1 Power Rail Output Error
          2. 7.4.1.3.2 Boot BIST Error
          3. 7.4.1.3.3 Runtime BIST Error
          4. 7.4.1.3.4 Catastrophic Error
          5. 7.4.1.3.5 Watchdog (WDOG) Error
          6. 7.4.1.3.6 Error Signal Monitor (ESM) Error
          7. 7.4.1.3.7 Warnings
        4. 7.4.1.4 Device Start-up Timing
        5. 7.4.1.5 Power Sequences
        6. 7.4.1.6 First Supply Detection
      2. 7.4.2 Multi-PMIC Synchronization
        1. 7.4.2.1 SPMI Interface System Setup
        2. 7.4.2.2 Transmission Protocol and CRC
          1. 7.4.2.2.1 Operation with Transmission Errors
          2. 7.4.2.2.2 Transmitted Information
        3. 7.4.2.3 SPMI Target Device Communication to SPMI Controller Device
          1. 7.4.2.3.1 Incomplete Communication from SPMI Target Device to SPMI Controller Device
        4. 7.4.2.4 SPMI-BIST Overview
          1. 7.4.2.4.1 SPMI Bus during Boot BIST and RUNTIME BIST
          2. 7.4.2.4.2 Periodic Checking of the SPMI
          3. 7.4.2.4.3 SPMI Message Priorities
    5. 7.5 Control Interfaces
      1. 7.5.1 CRC Calculation for I2C and SPI Interface Protocols
      2. 7.5.2 I2C-Compatible Interface
        1. 7.5.2.1 Data Validity
        2. 7.5.2.2 Start and Stop Conditions
        3. 7.5.2.3 Transferring Data
        4. 7.5.2.4 Auto-Increment Feature
      3. 7.5.3 Serial Peripheral Interface (SPI)
    6. 7.6 NVM Configurable Registers
      1. 7.6.1 Register Page Partitioning
      2. 7.6.2 CRC Protection for Configuration, Control, and Test Registers
      3. 7.6.3 CRC Protection for User Registers
      4. 7.6.4 Register Write Protection
        1. 7.6.4.1 ESM and Watchdog Configuration Registers
        2. 7.6.4.2 User Registers
    7. 7.7 Register Map
      1. 7.7.1 LP876242_map Registers
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Buck Inductor Selection
        2. 8.2.1.2 Buck Input Capacitor Selection
        3. 8.2.1.3 Buck Output Capacitor Selection
        4. 8.2.1.4 LDO Output Capacitor Selection
        5. 8.2.1.5 VCCA Supply Filtering Components
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Voltage Scaling Precautions
      4. 8.2.4 Application Curves
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
    4. 8.4 Power Supply Recommendations
  9. Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Digital Signal Descriptions

Table 5-2 Signal Descriptions
SIGNAL NAMEI/OThreshold LevelINPUT TYPE SELECTIONOUTPUT TYPE SELECTIONInternal PU/PD(2)RECOMMENDED EXTERNAL PU/PD(3)Control Registers
Power DomainDEGLITCH TIME(5)Power DomainPush-pull/Open-drain(4)
ENABLE
(Selectable function of GPIO4 pin)(1)
InputVIL, VIHVINT8 µs400 kΩ SPU to VINT, or
400 kΩ SPD to GND
NoneGPIO4_SEL
GPIO4_DEGLITCH_EN
GPIO4_PU_PD_EN
GPIO4_PU_SEL
ENABLE_POL
EN_DRV
(Selectable function of GPIO1 pin)(1)
Output VOL_20 mA VCCA/
PVIN_B4
PP with 10kΩ PU to VCCA 10 kΩ PU to VCCA None GPIO1_SEL
FORCE_EN_DRV_LOW
ENABLE_DRV
SCL_I2C1
(Selectable function of SCL_I2C1/SCK_SPI pin)(1)
InputVIL, VIHVINTHigh-speed mode:
10 ns
All other modes:
50 ns
NonePU to VIONVM-configuration(6)
I2C1_HS
SDA_I2C1
(Selectable function of SDA_I2C1/SDI_SPI pin)(1)
Input/outputVIL, VIH
VOL_20 mA
VINTHigh-speed mode:
10 ns
All other modes:
50 ns
VIOODNonePU to VIONVM-configuration(6)
I2C1_HS
SCL_I2C2
(Selectable function of GPIO2 pin)(1)
InputVIL, VIHVINTHigh-speed mode:
10 ns
All other modes:
50 ns
NonePU to VIONVM-configuration(6)
GPIO2_SEL
I2C2_HS
SDA_I2C2
(Selectable function of GPIO3 pin)(1)
Input/outputVIL, VIH
VOL_20 mA
VINTHigh-speed mode:
10 ns
All other modes:
50 ns
VIOODNonePU to VIONVM-configuration(6)
GPIO3_SEL
I2C2_HS
SCK_SPI
(Selectable function of SCL_I2C1/SCK_SPI pin)(1)
InputVIL, VIHVINTNoneNoneNoneNVM-configuration(6)
SDI_SPI
(Selectable function of SDA_I2C1/SDI_SPI pin)(1)
InputVIL, VIHVINTNoneNoneNoneNVM-configuration(6)
CS_SPI
(Selectable function of GPIO2 pin)(1)
InputVIL, VIHVINTNoneNoneNoneNVM-configuration(6)
GPIO2_SEL
SDO_SPI
(Selectable function of GPIO3 pin)(1)
OutputVOL_20 mA,
VOH(VIO)
VIOPP / HiZNoneNoneNVM-configuration(6)
GPIO3_SEL
SCLK_SPMI
(Configurable function of GPIO8 pin)(1)
Input in Slave Mode
Output in Master Mode
VIL, VIH
VOL_20 mA
VOH(VINT)
VINTNoneVINTPP400 kΩ SPD to GNDNoneGPIO8_SEL
GPIO8_PU_PD_EN
NVM-configuration(6)
SDATA_SPMI
(Configurable function of GPIO9 pin)(1)
Input/outputVIL, VIH
VOL_20 mA
VOH(IO)
VINTNoneVINTPP / HiZ400 kΩ SPD to GNDNoneGPIO9_SEL
GPIO9_PU_PD_EN
NVM-configuration(6)
nINTOutputVOL_20 mAVIOODNonePU to VIO
nRSTOUT(Configurable function of GPIO10 pin)(1)OutputVOL_20 mAVIOPP with 10 kΩ PU to VIO or OD10kΩ PU to VIO if configured as PPPU to VIO or VCCA if Open-drainGPIO10_SEL
GPIO10_OD
nRSTOUT_SOC
(Configurable function of GPIO1, GPIO5, GPIO10 pins)(1)
OutputVOL_20 mAVIOPP with 10kΩ PU to VIO or OD10kΩ PU to VIO if configured as PPPPU to VIO or VCCA if Open-drainGPIO1_SEL
GPIO1_OD
GPIO5_SEL
GPIO5_OD
GPIO10_SEL
GPIO10_OD
PGOOD
(Configurable function of GPIO1, GPIO6, GPIO9 pins)(1)
OutputGPIO1: VOL_20 mA, VOH(VIO)
GPIO6: VOL_3 mA, VOH(VIO)
GPIO9: VOL_20 mA, VOH(VINT)
VIO / VINTPP or ODNonePU to VIO if Open-drainGPIO1_SEL
GPIO1_OD
GPIO6_SEL
GPIO6_OD
GPIO9_SEL
GPIO9_OD
PGOOD_POL
PGOOD_WINDOW
PGOOD_SEL_x
nERR_MCU
(Configurable function of GPIO6, GPIO7 pins)(1)
Input VIL, VIH VINT 8 µs 400 kΩ PD to GND None GPIO6_SEL
GPIO7_SEL
TRIG_WDOG
(Configurable function of GPIO2, GPIO4 pins)(1)
Input VIL, VIH VINT 30 µs 400 kΩ SPD to GND None GPIO2_SEL
GPIO2_PU_PD_EN
GPIO4_SEL
GPIO4_PU_PD_EN
nSLEEP1
(Configurable function of all GPIO pins)(1)
InputVIL, VIHVINT8 µsGPIO4, 7, 8 or 9:
400 kΩ SPU to VINT
GPIO1, 2, 3, 5, 6, or 10:
400 kΩ SPU to VIO
NoneGPIOx_SEL
GPIOx_PU_PD_EN
nSLEEP2
(Configurable function of all GPIO pins)(1)
InputVIL, VIHVINT8 µsGPIO4, 7, 8 or 9:
400 kΩ SPU to VINT
GPIO1, 2, 3, 5, 6, or 10:
400 kΩ SPU to VIO
NoneGPIOx_SEL
GPIOx_PU_PD_EN
WKUP1
(Configurable function of all GPIO pins)(1)
InputVIL, VIHVINT8 µsGPIO4, 7, 8 or 9:
400 kΩ SPU to VINT
400 kΩ SPD to GND
GPIO1, 2, 3, 5, 6, or 10:
400 kΩ SPU to VIO
400 kΩ SPD to GND
NoneGPIOx_SEL
GPIOx_DEGLITCH_EN
GPIOx_PU_PD_EN
GPIOx_PU_SEL
WKUP2
(Configurable function of all GPIO pins)(1)
InputVIL, VIHVINT8 µsGPIO4, 7, 8 or 9:
400 kΩ SPU to VINT
400 kΩ SPD to GND
GPIO1, 2, 3, 5, 6, or 10:
400 kΩ SPU to VIO
400 kΩ SPD to GND
NoneGPIOx_SEL
GPIOx_DEGLITCH_EN
GPIOx_PU_PD_EN
GPIOx_PU_SEL
GPIO1
(Configurable function of GPIO1 pin)(1)
Input/outputVIL, VIH
VOL_20 mA
VOH(VIO)
VINT8 µsVIOPP or OD400 kΩ SPU to VIO
400 kΩ SPD to GND
PU to VIO or VCCA
if Open-drain
GPIO1_SEL
GPIO1_DEGLITCH_EN
GPIO1_PU_PD_EN
GPIO1_PU_SEL
GPIO1_OD
GPIO1_DIR
GPIO2
(Configurable function of GPIO2 pin)(1)
Input/outputVIL, VIH
VOL_3 mA
VOH(VIO)
VINT8 µsVIOPP or OD400 kΩ SPU to VIO
400 kΩ SPD to GND
PU to VIO or VCCA
if Open-drain
GPIO2_SEL
GPIO2_DEGLITCH_EN
GPIO2_PU_PD_EN
GPIO2_PU_SEL
GPIO2_OD
GPIO2_DIR
GPIO3
(Configurable function of GPIO3 pin)(1)
Input/outputVIL, VIH
VOL_20 mA
VOH(VIO)
VINT8 µsVIOPP or OD400 kΩ SPU to VIO
400 kΩ SPD to GND
PU to VIO or VCCA
if Open-drain
GPIO3_SEL
GPIO3_DEGLITCH_EN
GPIO3_PU_PD_EN
GPIO3_PU_SEL
GPIO3_OD
GPIO3_DIR
GPIO4
(Configurable function of GPIO4 pin)(1)
Input/outputVIL, VIH
VOL_3 mA
VOH(VINT)
VINT8 µsVINTPP or OD400 kΩ SPU to VINT
400 kΩ SPD to GND
PU to VIO
if Open-drain
GPIO4_SEL
GPIO4_DEGLITCH_EN
GPIO4_PU_PD_EN
GPIO4_PU_SEL
GPIO4_OD
GPIO4_DIR
GPIO5
(Configurable function of GPIO5 pin)(1)
Input/outputVIL, VIH
VOL_20 mA
VOH(VIO)
VINT8 µsVIOPP or OD400 kΩ SPU to VIO
400 kΩ SPD to GND
PU to VIO or VCCA
if Open-drain
GPIO5_SEL
GPIO5_DEGLITCH_EN
GPIO5_PU_PD_EN
GPIO5_PU_SEL
GPIO5_OD
GPIO5_DIR
GPIO6
(Configurable function of GPIO6 pin)(1)
Input/outputVIL, VIH
VOL_3 mA
VOH(VIO)
VINT8 µsVIOPP or OD400 kΩ SPU to VIO
400 kΩ SPD to GND
PU to VIO or VCCA
if Open-drain
GPIO6_SEL
GPIO6_DEGLITCH_EN
GPIO6_PU_PD_EN
GPIO6_PU_SEL
GPIO6_OD
GPIO6_DIR
GPIO7
(Configurable function of GPIO7 pin)(1)
Input/outputVIL, VIH
VOL_3 mA
VOH(VINT)
VINT8 µsVINTPP or OD400 kΩ SPU to VINT
400 kΩ SPD to GND
PU to VIO
if Open-drain
GPIO7_SEL
GPIO7_DEGLITCH_EN
GPIO7_PU_PD_EN
GPIO7_PU_SEL
GPIO7_OD
GPIO7_DIR
GPIO8
(Configurable function of GPIO8 pin)(1)
Input/outputVIL, VIH
VOL_20 mA
VOH(VINT)
VINT8 µsVINTPP or OD400 kΩ SPU to VINT
400 kΩ SPD to GND
PU to VIO
if Open-drain
GPIO8_SEL
GPIO8_DEGLITCH_EN
GPIO8_PU_PD_EN
GPIO8_PU_SEL
GPIO8_OD
GPIO8_DIR
GPIO9
(Configurable function of GPIO9 pin)(1)
Input/outputVIL, VIH
VOL_20 mA
VOH(VINT)
VINT8 µsVINTPP or OD400 kΩ SPU to VINT
400 kΩ SPD to GND
PU to VIO
if Open-drain
GPIO9_SEL
GPIO9_DEGLITCH_EN
GPIO9_PU_PD_EN
GPIO9_PU_SEL
GPIO9_OD
GPIO9_DIR
GPIO10
(Configurable function of GPIO10 pin)(1)
Input/outputVIL, VIH
VOL_20 mA
VOH(VIO)
VINT8 µsVIOPP or OD400 kΩ SPU to VIO
400 kΩ SPD to GND
PU to VIO or VCCA
if Open-drain
GPIO10_SEL
GPIO10_DEGLITCH_EN
GPIO10_PU_PD_EN
GPIO10_PU_SEL
GPIO10_OD
GPIO10_DIR
SYNCCLKIN
(Configurable function of GPIO5, GPIO9 pins)(1)
InputVIL, VIHVINTNone400 kΩ SPD to GNDNoneGPIO5_SEL
GPIO5_PU_PD_EN
GPIO9_SEL
GPIO9_PU_PD_EN
SYNCCLKOUT
(Configurable function of GPIO5, GPIO6 pins)(1)
OutputGPIO5: VOL_20 mA, VOH(VIO)
GPIO6: VOL_3 mA, VOH(VIO)
VIOPPNoneNoneGPIO5_SEL
GPIO6_SEL
VMON1
(Configurable function of GPIO7 pin)(1)
InputAnalogNoneNoneGPIO7_SEL
VMON1_EN
VMON1_RANGE_SEL
VMON2
(Configurable function of GPIO8 pin)(1)
InputAnalogNoneNoneGPIO8_SEL
VMON2_EN
VMON2_RANGE_SEL
BUCK1_VMON
(Configurable function of GPIO4 pin)(1)
InputAnalogNoneNoneGPIO4_SEL
BUCK1_ VMON_EN
REFOUT
(Configurable function of GPIO7 pin)(1)
OutputAnalog400 kΩ PD to GND when REFOUT_EN = 0GPIO7_SEL
REFOUT_EN
Configurable function through NVM register setting.
PU = Pullup, PD = Pulldown, SPU = Software-configurable pullup, SPD = Software-configurable pulldown.
The internal pull-up and pull-down resistors are automatically disabled when the device is configured as a push-pull output pin unless otherwise noted.
PP = Push-pull, OD = Open-drain.
Deglitch time is only applicable when option is enabled.
NVM-configuration for I2C/SPI and SPMI cannot be overwritten during operation.