SNVSC07A June 2021 – September 2022 LP876242-Q1
PRODUCTION DATA
SIGNAL NAME | I/O | Threshold Level | INPUT TYPE SELECTION | OUTPUT TYPE SELECTION | Internal PU/PD(2) | RECOMMENDED EXTERNAL PU/PD(3) | Control Registers | ||
---|---|---|---|---|---|---|---|---|---|
Power Domain | DEGLITCH TIME(5) | Power Domain | Push-pull/Open-drain(4) | ||||||
ENABLE (Selectable function of GPIO4 pin)(1) | Input | VIL, VIH | VINT | 8 µs | 400 kΩ SPU to VINT,
or 400 kΩ SPD to GND | None | GPIO4_SEL GPIO4_DEGLITCH_EN GPIO4_PU_PD_EN GPIO4_PU_SEL ENABLE_POL | ||
EN_DRV (Selectable function of GPIO1 pin)(1) |
Output | VOL_20 mA | VCCA/ PVIN_B4 |
PP with 10kΩ PU to VCCA | 10 kΩ PU to VCCA | None | GPIO1_SEL FORCE_EN_DRV_LOW ENABLE_DRV |
||
SCL_I2C1 (Selectable function of SCL_I2C1/SCK_SPI pin)(1) | Input | VIL, VIH | VINT | High-speed mode: 10 ns All other modes: 50 ns | None | PU to VIO | NVM-configuration(6) I2C1_HS | ||
SDA_I2C1 (Selectable function of SDA_I2C1/SDI_SPI pin)(1) | Input/output | VIL,
VIH VOL_20 mA | VINT | High-speed mode: 10 ns All other modes: 50 ns | VIO | OD | None | PU to VIO | NVM-configuration(6) I2C1_HS |
SCL_I2C2 (Selectable function of GPIO2 pin)(1) | Input | VIL, VIH | VINT | High-speed mode: 10 ns All other modes: 50 ns | None | PU to VIO | NVM-configuration(6) GPIO2_SEL I2C2_HS | ||
SDA_I2C2 (Selectable function of GPIO3 pin)(1) | Input/output | VIL,
VIH VOL_20 mA | VINT | High-speed mode: 10 ns All other modes: 50 ns | VIO | OD | None | PU to VIO | NVM-configuration(6) GPIO3_SEL I2C2_HS |
SCK_SPI (Selectable function of SCL_I2C1/SCK_SPI pin)(1) | Input | VIL, VIH | VINT | None | None | None | NVM-configuration(6) | ||
SDI_SPI (Selectable function of SDA_I2C1/SDI_SPI pin)(1) | Input | VIL, VIH | VINT | None | None | None | NVM-configuration(6) | ||
CS_SPI (Selectable function of GPIO2 pin)(1) | Input | VIL, VIH | VINT | None | None | None | NVM-configuration(6) GPIO2_SEL | ||
SDO_SPI (Selectable function of GPIO3 pin)(1) | Output | VOL_20 mA, VOH(VIO) | VIO | PP / HiZ | None | None | NVM-configuration(6) GPIO3_SEL | ||
SCLK_SPMI (Configurable function of GPIO8 pin)(1) | Input in Slave Mode Output in Master Mode | VIL,
VIH VOL_20 mA VOH(VINT) | VINT | None | VINT | PP | 400 kΩ SPD to GND | None | GPIO8_SEL GPIO8_PU_PD_EN NVM-configuration(6) |
SDATA_SPMI (Configurable function of GPIO9 pin)(1) | Input/output | VIL,
VIH VOL_20 mA VOH(IO) | VINT | None | VINT | PP / HiZ | 400 kΩ SPD to GND | None | GPIO9_SEL GPIO9_PU_PD_EN NVM-configuration(6) |
nINT | Output | VOL_20 mA | VIO | OD | None | PU to VIO | |||
nRSTOUT(Configurable function of GPIO10 pin)(1) | Output | VOL_20 mA | VIO | PP with 10 kΩ PU to VIO or OD | 10kΩ PU to VIO if configured as PP | PU to VIO or VCCA if Open-drain | GPIO10_SEL GPIO10_OD | ||
nRSTOUT_SOC (Configurable function of GPIO1, GPIO5, GPIO10 pins)(1) | Output | VOL_20 mA | VIO | PP with 10kΩ PU to VIO or OD | 10kΩ PU to VIO if configured as PP | PPU to VIO or VCCA if Open-drain | GPIO1_SEL GPIO1_OD GPIO5_SEL GPIO5_OD GPIO10_SEL GPIO10_OD | ||
PGOOD (Configurable function of GPIO1, GPIO6, GPIO9 pins)(1) | Output | GPIO1: VOL_20 mA,
VOH(VIO) GPIO6: VOL_3 mA, VOH(VIO) GPIO9: VOL_20 mA, VOH(VINT) | VIO / VINT | PP or OD | None | PU to VIO if Open-drain | GPIO1_SEL GPIO1_OD GPIO6_SEL GPIO6_OD GPIO9_SEL GPIO9_OD PGOOD_POL PGOOD_WINDOW PGOOD_SEL_x | ||
nERR_MCU (Configurable function of GPIO6, GPIO7 pins)(1) |
Input | VIL, VIH | VINT | 8 µs | 400 kΩ PD to GND | None | GPIO6_SEL GPIO7_SEL |
||
TRIG_WDOG (Configurable function of GPIO2, GPIO4 pins)(1) |
Input | VIL, VIH | VINT | 30 µs | 400 kΩ SPD to GND | None | GPIO2_SEL GPIO2_PU_PD_EN GPIO4_SEL GPIO4_PU_PD_EN |
||
nSLEEP1 (Configurable function of all GPIO pins)(1) | Input | VIL, VIH | VINT | 8 µs | GPIO4, 7, 8 or 9: 400 kΩ SPU to VINT GPIO1, 2, 3, 5, 6, or 10: 400 kΩ SPU to VIO | None | GPIOx_SEL GPIOx_PU_PD_EN | ||
nSLEEP2 (Configurable function of all GPIO pins)(1) | Input | VIL, VIH | VINT | 8 µs | GPIO4, 7, 8 or 9: 400 kΩ SPU to VINT GPIO1, 2, 3, 5, 6, or 10: 400 kΩ SPU to VIO | None | GPIOx_SEL GPIOx_PU_PD_EN | ||
WKUP1 (Configurable function of all GPIO pins)(1) | Input | VIL, VIH | VINT | 8 µs | GPIO4, 7, 8 or 9: 400 kΩ SPU to VINT 400 kΩ SPD to GND GPIO1, 2, 3, 5, 6, or 10: 400 kΩ SPU to VIO 400 kΩ SPD to GND | None | GPIOx_SEL GPIOx_DEGLITCH_EN GPIOx_PU_PD_EN GPIOx_PU_SEL | ||
WKUP2 (Configurable function of all GPIO pins)(1) | Input | VIL, VIH | VINT | 8 µs | GPIO4, 7, 8 or 9: 400 kΩ SPU to VINT 400 kΩ SPD to GND GPIO1, 2, 3, 5, 6, or 10: 400 kΩ SPU to VIO 400 kΩ SPD to GND | None | GPIOx_SEL GPIOx_DEGLITCH_EN GPIOx_PU_PD_EN GPIOx_PU_SEL | ||
GPIO1 (Configurable function of GPIO1 pin)(1) | Input/output | VIL,
VIH VOL_20 mA VOH(VIO) | VINT | 8 µs | VIO | PP or OD | 400 kΩ SPU to VIO 400 kΩ SPD to GND | PU to VIO or VCCA if Open-drain | GPIO1_SEL GPIO1_DEGLITCH_EN GPIO1_PU_PD_EN GPIO1_PU_SEL GPIO1_OD GPIO1_DIR |
GPIO2 (Configurable function of GPIO2 pin)(1) | Input/output | VIL,
VIH VOL_3 mA VOH(VIO) | VINT | 8 µs | VIO | PP or OD | 400 kΩ SPU to VIO 400 kΩ SPD to GND | PU to VIO or VCCA if Open-drain | GPIO2_SEL GPIO2_DEGLITCH_EN GPIO2_PU_PD_EN GPIO2_PU_SEL GPIO2_OD GPIO2_DIR |
GPIO3 (Configurable function of GPIO3 pin)(1) | Input/output | VIL,
VIH VOL_20 mA VOH(VIO) | VINT | 8 µs | VIO | PP or OD | 400 kΩ SPU to VIO 400 kΩ SPD to GND | PU to VIO or VCCA if Open-drain | GPIO3_SEL GPIO3_DEGLITCH_EN GPIO3_PU_PD_EN GPIO3_PU_SEL GPIO3_OD GPIO3_DIR |
GPIO4 (Configurable function of GPIO4 pin)(1) | Input/output | VIL,
VIH VOL_3 mA VOH(VINT) | VINT | 8 µs | VINT | PP or OD | 400 kΩ SPU to VINT 400 kΩ SPD to GND | PU to VIO if Open-drain | GPIO4_SEL GPIO4_DEGLITCH_EN GPIO4_PU_PD_EN GPIO4_PU_SEL GPIO4_OD GPIO4_DIR |
GPIO5 (Configurable function of GPIO5 pin)(1) | Input/output | VIL,
VIH VOL_20 mA VOH(VIO) | VINT | 8 µs | VIO | PP or OD | 400 kΩ SPU to VIO 400 kΩ SPD to GND | PU to VIO or VCCA if Open-drain | GPIO5_SEL GPIO5_DEGLITCH_EN GPIO5_PU_PD_EN GPIO5_PU_SEL GPIO5_OD GPIO5_DIR |
GPIO6 (Configurable function of GPIO6 pin)(1) | Input/output | VIL,
VIH VOL_3 mA VOH(VIO) | VINT | 8 µs | VIO | PP or OD | 400 kΩ SPU to VIO 400 kΩ SPD to GND | PU to VIO or VCCA if Open-drain | GPIO6_SEL GPIO6_DEGLITCH_EN GPIO6_PU_PD_EN GPIO6_PU_SEL GPIO6_OD GPIO6_DIR |
GPIO7 (Configurable function of GPIO7 pin)(1) | Input/output | VIL,
VIH VOL_3 mA VOH(VINT) | VINT | 8 µs | VINT | PP or OD | 400 kΩ SPU to VINT 400 kΩ SPD to GND | PU to VIO if Open-drain | GPIO7_SEL GPIO7_DEGLITCH_EN GPIO7_PU_PD_EN GPIO7_PU_SEL GPIO7_OD GPIO7_DIR |
GPIO8 (Configurable function of GPIO8 pin)(1) | Input/output | VIL,
VIH VOL_20 mA VOH(VINT) | VINT | 8 µs | VINT | PP or OD | 400 kΩ SPU to VINT 400 kΩ SPD to GND | PU to VIO if Open-drain | GPIO8_SEL GPIO8_DEGLITCH_EN GPIO8_PU_PD_EN GPIO8_PU_SEL GPIO8_OD GPIO8_DIR |
GPIO9 (Configurable function of GPIO9 pin)(1) | Input/output | VIL,
VIH VOL_20 mA VOH(VINT) | VINT | 8 µs | VINT | PP or OD | 400 kΩ SPU to VINT 400 kΩ SPD to GND | PU to VIO if Open-drain | GPIO9_SEL GPIO9_DEGLITCH_EN GPIO9_PU_PD_EN GPIO9_PU_SEL GPIO9_OD GPIO9_DIR |
GPIO10 (Configurable function of GPIO10 pin)(1) | Input/output | VIL,
VIH VOL_20 mA VOH(VIO) | VINT | 8 µs | VIO | PP or OD | 400 kΩ SPU to VIO 400 kΩ SPD to GND | PU to VIO or VCCA if Open-drain | GPIO10_SEL GPIO10_DEGLITCH_EN GPIO10_PU_PD_EN GPIO10_PU_SEL GPIO10_OD GPIO10_DIR |
SYNCCLKIN (Configurable function of GPIO5, GPIO9 pins)(1) | Input | VIL, VIH | VINT | None | 400 kΩ SPD to GND | None | GPIO5_SEL GPIO5_PU_PD_EN GPIO9_SEL GPIO9_PU_PD_EN | ||
SYNCCLKOUT (Configurable function of GPIO5, GPIO6 pins)(1) | Output | GPIO5: VOL_20 mA,
VOH(VIO) GPIO6: VOL_3 mA, VOH(VIO) | VIO | PP | None | None | GPIO5_SEL GPIO6_SEL | ||
VMON1 (Configurable function of GPIO7 pin)(1) | Input | Analog | None | None | GPIO7_SEL VMON1_EN VMON1_RANGE_SEL | ||||
VMON2 (Configurable function of GPIO8 pin)(1) | Input | Analog | None | None | GPIO8_SEL VMON2_EN VMON2_RANGE_SEL | ||||
BUCK1_VMON (Configurable function of GPIO4 pin)(1) | Input | Analog | None | None | GPIO4_SEL BUCK1_ VMON_EN | ||||
REFOUT (Configurable function of GPIO7 pin)(1) | Output | Analog | 400 kΩ PD to GND when REFOUT_EN = 0 | GPIO7_SEL REFOUT_EN |