SNVSC07A June   2021  – September 2022 LP876242-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Digital Signal Descriptions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Internal Low Drop-Out Regulators (LDOVINT)
    6. 6.6  BUCK1, BUCK2, BUCK3, and BUCK4 Regulators
    7. 6.7  Reference Generator (REFOUT)
    8. 6.8  Monitoring Functions
    9. 6.9  Clocks, Oscillators, and DPLL
    10. 6.10 Thermal Monitoring and Shutdown
    11. 6.11 System Control Thresholds
    12. 6.12 Current Consumption
    13. 6.13 Digital Input Signal Parameters
    14. 6.14 Digital Output Signal Parameters
    15. 6.15 I/O Pullup and Pulldown Resistance
    16. 6.16 I2C Interface
    17. 6.17 Serial Peripheral Interface (SPI)
    18.     25
    19. 6.18 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage Monitor
      2. 7.3.2 Power Resources
        1. 7.3.2.1 Buck Regulators
          1. 7.3.2.1.1 BUCK Regulator Overview
          2. 7.3.2.1.2 Spread-Spectrum Mode
          3. 7.3.2.1.3 Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support
          4. 7.3.2.1.4 BUCK Output Voltage Setting
          5. 7.3.2.1.5 Sync Clock Functionality
        2. 7.3.2.2 Internal Low Dropout Regulator (LDOVINT)
      3. 7.3.3 Residual Voltage Checking
      4. 7.3.4 Output Voltage Monitor and PGOOD Generation
      5. 7.3.5 General-Purpose I/Os (GPIO Pins)
      6. 7.3.6 Thermal Monitoring
        1. 7.3.6.1 Thermal Warning Function
        2. 7.3.6.2 Thermal Shutdown
      7. 7.3.7 Interrupts
      8. 7.3.8 Watchdog (WD)
        1. 7.3.8.1 Watchdog Fail Counter and Status
        2. 7.3.8.2 Watchdog Start-Up and Configuration
        3. 7.3.8.3 MCU to Watchdog Synchronization
        4. 7.3.8.4 Watchdog Disable Function
        5. 7.3.8.5 Watchdog Sequence
        6. 7.3.8.6 Watchdog Trigger Mode
        7. 7.3.8.7 WatchDog Flow Chart and Timing Diagrams in Trigger Mode
        8.       55
        9. 7.3.8.8 Watchdog Question-Answer Mode
          1. 7.3.8.8.1 Watchdog Q&A Related Definitions
          2. 7.3.8.8.2 Question Generation
          3. 7.3.8.8.3 Answer Comparison
            1. 7.3.8.8.3.1 Sequence of the 2-bit Watchdog Answer Counter
            2. 7.3.8.8.3.2 Watchdog Sequence Events and Status Updates
            3. 7.3.8.8.3.3 Watchdog Q&A Sequence Scenarios
      9. 7.3.9 Error Signal Monitor (ESM)
        1. 7.3.9.1 ESM Error-Handling Procedure
        2. 7.3.9.2 Level Mode
        3.       66
        4. 7.3.9.3 PWM Mode
          1. 7.3.9.3.1 Good-Events and Bad-Events
          2. 7.3.9.3.2 ESM Error-Counter
            1. 7.3.9.3.2.1 ESM Start-Up in PWM Mode
          3. 7.3.9.3.3 ESM Flow Chart and Timing Diagrams in PWM Mode
          4.        72
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device State Machine
        1. 7.4.1.1 Fixed Device Power FSM
          1. 7.4.1.1.1 Register Resets and EEPROM read at INIT state
        2. 7.4.1.2 Pre-Configurable Mission States
          1. 7.4.1.2.1 PFSM Commands
            1. 7.4.1.2.1.1  REG_WRITE_IMM Command
            2. 7.4.1.2.1.2  REG_WRITE_MASK_IMM Command
            3. 7.4.1.2.1.3  REG_WRITE_MASK_PAGE0_IMM Command
            4. 7.4.1.2.1.4  REG_WRITE_BIT_PAGE0_IMM Command
            5. 7.4.1.2.1.5  REG_WRITE_WIN_PAGE0_IMM Command
            6. 7.4.1.2.1.6  REG_WRITE_VOUT_IMM Command
            7. 7.4.1.2.1.7  REG_WRITE_VCTRL_IMM Command
            8. 7.4.1.2.1.8  REG_WRITE_MASK_SREG Command
            9. 7.4.1.2.1.9  SREG_READ_REG Command
            10. 7.4.1.2.1.10 SREG_WRITE_IMM Command
            11. 7.4.1.2.1.11 WAIT Command
            12. 7.4.1.2.1.12 DELAY_IMM Command
            13. 7.4.1.2.1.13 DELAY_SREG Command
            14. 7.4.1.2.1.14 TRIG_SET Command
            15. 7.4.1.2.1.15 TRIG_MASK Command
            16. 7.4.1.2.1.16 END Command
          2. 7.4.1.2.2 Configuration Memory Organization and Sequence Execution
          3. 7.4.1.2.3 Mission State Configuration
          4. 7.4.1.2.4 Pre-Configured Hardware Transitions
            1. 7.4.1.2.4.1 ON Requests
            2. 7.4.1.2.4.2 OFF Requests
            3. 7.4.1.2.4.3 NSLEEP1 and NSLEEP2 Functions
            4. 7.4.1.2.4.4 WKUP1 and WKUP2 Functions
        3. 7.4.1.3 Error Handling Operations
          1. 7.4.1.3.1 Power Rail Output Error
          2. 7.4.1.3.2 Boot BIST Error
          3. 7.4.1.3.3 Runtime BIST Error
          4. 7.4.1.3.4 Catastrophic Error
          5. 7.4.1.3.5 Watchdog (WDOG) Error
          6. 7.4.1.3.6 Error Signal Monitor (ESM) Error
          7. 7.4.1.3.7 Warnings
        4. 7.4.1.4 Device Start-up Timing
        5. 7.4.1.5 Power Sequences
        6. 7.4.1.6 First Supply Detection
      2. 7.4.2 Multi-PMIC Synchronization
        1. 7.4.2.1 SPMI Interface System Setup
        2. 7.4.2.2 Transmission Protocol and CRC
          1. 7.4.2.2.1 Operation with Transmission Errors
          2. 7.4.2.2.2 Transmitted Information
        3. 7.4.2.3 SPMI Target Device Communication to SPMI Controller Device
          1. 7.4.2.3.1 Incomplete Communication from SPMI Target Device to SPMI Controller Device
        4. 7.4.2.4 SPMI-BIST Overview
          1. 7.4.2.4.1 SPMI Bus during Boot BIST and RUNTIME BIST
          2. 7.4.2.4.2 Periodic Checking of the SPMI
          3. 7.4.2.4.3 SPMI Message Priorities
    5. 7.5 Control Interfaces
      1. 7.5.1 CRC Calculation for I2C and SPI Interface Protocols
      2. 7.5.2 I2C-Compatible Interface
        1. 7.5.2.1 Data Validity
        2. 7.5.2.2 Start and Stop Conditions
        3. 7.5.2.3 Transferring Data
        4. 7.5.2.4 Auto-Increment Feature
      3. 7.5.3 Serial Peripheral Interface (SPI)
    6. 7.6 NVM Configurable Registers
      1. 7.6.1 Register Page Partitioning
      2. 7.6.2 CRC Protection for Configuration, Control, and Test Registers
      3. 7.6.3 CRC Protection for User Registers
      4. 7.6.4 Register Write Protection
        1. 7.6.4.1 ESM and Watchdog Configuration Registers
        2. 7.6.4.2 User Registers
    7. 7.7 Register Map
      1. 7.7.1 LP876242_map Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Buck Inductor Selection
        2. 8.2.1.2 Buck Input Capacitor Selection
        3. 8.2.1.3 Buck Output Capacitor Selection
        4. 8.2.1.4 LDO Output Capacitor Selection
        5. 8.2.1.5 VCCA Supply Filtering Components
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Voltage Scaling Precautions
      4. 8.2.4 Application Curves
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
    4. 8.4 Power Supply Recommendations
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
7.3.9.3.1 Good-Events and Bad-Events

In PWM mode, the ESM_MCU monitors the high-pulse and low-pulse duration times its PWM input signal as follows:

  • After a falling edge, the ESM_MCU starts monitoring the low-pulse time-duration. If the input signal remains low after exceeding the maximum low-pulse time-threshold (tLOW_MAX_TH), the ESM_MCU detects a bad event and the low-pulse duration counter reinitializes. Each time the signal further exceeds the maximum threshold, the ESM_MCU detects a bad event. On the next rising edge on the input signal, the ESM starts the high-pulse time-duration monitoring
  • After a rising edge, the ESM_MCU starts monitoring the high-pulse time-duration. If the input signal remains high after exceeding the maximum high-pulse time-threshold (tHIGH_MAX_TH), the ESM_MCU detects a bad event and the high-pulse duration counter reinitializes. Each time the signal further exceeds the maximum threshold, the ESM_MCU detects a bad event. On the next falling edge on the input signal, the ESM_MCU starts the low-pulse time-duration monitoring.

In addition, the ESM_MCU detects a bad-event in PWM mode if one of the events that follow occurs on the deglitched signal of the input pin nERR_MCU:

  • A high-pulse time-duration that is longer than the maximum high-pulse time-threshold (tHIGH_MAX_TH) that is configured in register bits ESM_MCU_HMAX[7:0].
  • A high-pulse time-duration that is shorter than the minimum high-pulse time-threshold (tHIGH_MIN_TH) that is configured in register bits ESM_MCU_HMIN[7:0].
  • A low-pulse time-duration that is longer than the maximum low-pulse time-threshold (tLOW_MAX_TH) that is configured in register bits ESM_MCU_LMAX[7:0].
  • A low-pulse time-duration that is less than the minimum low-pulse time-threshold (tLOW_MIN_TH) that is configured in register bits ESM_MCU_LMIN[7:0].

The ESM_MCU detects a good-event in PWM mode if one of the events that follow occurs on the deglitched signal of the input pin nERR_MCU:

  • A low-pulse time-duration within the minimum and maximum low-pulse time-thresholds is followed by a high-pulse time-duration within the minimum and maximum high-pulse time-thresholds, or
  • A high-pulse duration within the minimum and maximum high-pulse time-thresholds is followed by a low-pulse duration within the minimum and maximum low-pulse time-thresholds

Register bits ESM_MCU_HMAX[7:0] set the maximum high-pulse time-threshold (tHIGH_MAX_TH) for the ESM_MCU. Use Equation 15 and Equation 16 to calculate the worst-case values for the tHIGH_MAX_TH:

Equation 15. Min. tHIGH_MAX_TH = (15 µs +ESM_MCU_HMAX[7:0] × 15 µs) × 0.95
Equation 16. Max. tHIGH_MAX_TH = (15 µs +ESM_MCU_HMAX[7:0] × 15 µs) × 1.05

ESM_MCU_HMIN[7:0] set the minimum high-pulse time-threshold (tHIGH_MIN_TH) for the ESM. Use Equation 17 and Equation 18 to calculate the worst-case values for the tHIGH_MIN_TH:

Equation 17. Min. tHIGH_MIN_TH = (15 µs +ESM_MCU_HMIN[7:0] × 15 µs) × 0.95
Equation 18. Max. tHIGH_MIN_TH = (15 µs +ESM_MCU_HMIN[7:0] × 15 µs) × 1.05

ESM_MCU_LMAX[7:0] set the maximum low-pulse time-threshold (tLOW_MAX_TH) for the ESM_MCU. Use Equation 19 and Equation 20 to calculate the worst-case values for the tLOW_MAX_TH:

Equation 19. Min. tLOW_MAX_TH = (15 µs +ESM_MCU_LMAX[7:0] × 15 µs) × 0.95
Equation 20. Max. tLOW_MAX_TH = (15 µs +ESM_MCU_LMAX[7:0] × 15 µs) × 1.05

ESM_MCU_LMIN[7:0] set the minimum low-pulse time-threshold (tLOW_MIN_TH) for the ESM. Use Equation 21 and Equation 22 to calculate the worst-case values for the tLOW_MIN_TH:

Equation 21. Min. tLOW_MIN_TH = (15 µs +ESM_MCU_LMIN[7:0] × 15 µs) × 0.95
Equation 22. Max. tLOW_MIN_TH = (15 µs +ESM_MCU_LMIN[7:0] × 15 µs) × 1.05

Please note that when setting up the minimum and the maximum low-pulse or high-pulse time-thresholds need to be configured such that clock tolerances from the LP876242-Q1 and from the processor are incorporated. Equation 23, Equation 24, Equation 25, and Equation 26 are a guideline on how to incorporate these clock-tolerances:

Equation 23. ESM_MCU_HMIN[7:0] < 0.5 × (ESM_MCU_HMAX[7:0] + ESM_MCU_HMIN[7:0]) × 0.95 × (1 - MCUclock tolerance)
Equation 24. ESM_MCU_HMAX[7:0] > 0.5 × (ESM_MCU_HMAX[7:0] + ESM_MCU_HMIN[7:0]) × 1.05 × (1 + MCU clock tolerance)
Equation 25. ESM_MCU_LMIN[7:0] < 0.5 × (ESM_MCU_LMAX[7:0] + ESM_MCU_LMIN[7:0]) × 0.95 × (1 - MCUclock tolerance)
Equation 26. ESM_MCU_LMAX[7:0] > 0.5 × (ESM_MCU_LMAX[7:0] + ESM_MCU_LMIN[7:0]) × 1.05 × (1 + MCU clock tolerance)