SNVSC07A June 2021 – September 2022 LP876242-Q1
PRODUCTION DATA
The buck input capacitors CIN1, CIN2, CIN3, and CIN4 are shown in the Section 8.2. A ceramic input bypass capacitor of 10 μF is required for each phase of the regulator. Place the input capacitor as close as possible to the PVIN_Bx pin and PGND pin of the device. A larger value or higher voltage rating improves the input voltage filtering. Use X7R type of capacitors, not Y5V or F. DC bias characteristics capacitors must be considered, minimum effective input capacitance to ensure good performance is 3 μF per buck input at maximum input voltage including tolerances and ambient temperature range. See Table 8-2.
The input filter capacitor supplies current to the high-side FET switch in the first half of each cycle and reduces voltage ripple imposed on the input power source. A ceramic capacitor with low ESR provides the best noise filtering of the input voltage spikes due to this rapidly changing current. Select an input filter capacitor with sufficient ripple current rating. In addition ferrite can be used in front of the input capacitor to reduce the EMI.
For optimal performance, additional 1 μF 3-terminal input capacitors are required. Buck1 and buck2 can share one 3-T capacitor and buck3 and buck4 can share one 3-T capacitor. See Table 8-2 .
MANUFACTURER | PART NUMBER | VALUE | CASE SIZE | DIMENSIONS L × W × H (mm) | VOLTAGE RATING |
---|---|---|---|---|---|
Murata | GCM21BR71A106KE22 | 10 µF (10%) | 0805 | 2 × 1.25 × 1.25 | 10 V |
TDK | CGA4J1X7S1C106K125AB | 10 µF (10%) | 0805 | 2 × 1.25 × 1.25 | 10 V |
Murata | NFM18HC105C1C3 (3-T) | 1 µF (20%) | 0603 | 1.6 × 0.8 × 0.7 | 16 V |
TDK | YFF18AC0J105M (3-T) | 1 µF (20%) | 0603 | 1.6 × 0.8 × 0.6 | 6.3 V |