SNVSC07A June   2021  – September 2022 LP876242-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Digital Signal Descriptions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Internal Low Drop-Out Regulators (LDOVINT)
    6. 6.6  BUCK1, BUCK2, BUCK3, and BUCK4 Regulators
    7. 6.7  Reference Generator (REFOUT)
    8. 6.8  Monitoring Functions
    9. 6.9  Clocks, Oscillators, and DPLL
    10. 6.10 Thermal Monitoring and Shutdown
    11. 6.11 System Control Thresholds
    12. 6.12 Current Consumption
    13. 6.13 Digital Input Signal Parameters
    14. 6.14 Digital Output Signal Parameters
    15. 6.15 I/O Pullup and Pulldown Resistance
    16. 6.16 I2C Interface
    17. 6.17 Serial Peripheral Interface (SPI)
    18.     25
    19. 6.18 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage Monitor
      2. 7.3.2 Power Resources
        1. 7.3.2.1 Buck Regulators
          1. 7.3.2.1.1 BUCK Regulator Overview
          2. 7.3.2.1.2 Spread-Spectrum Mode
          3. 7.3.2.1.3 Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support
          4. 7.3.2.1.4 BUCK Output Voltage Setting
          5. 7.3.2.1.5 Sync Clock Functionality
        2. 7.3.2.2 Internal Low Dropout Regulator (LDOVINT)
      3. 7.3.3 Residual Voltage Checking
      4. 7.3.4 Output Voltage Monitor and PGOOD Generation
      5. 7.3.5 General-Purpose I/Os (GPIO Pins)
      6. 7.3.6 Thermal Monitoring
        1. 7.3.6.1 Thermal Warning Function
        2. 7.3.6.2 Thermal Shutdown
      7. 7.3.7 Interrupts
      8. 7.3.8 Watchdog (WD)
        1. 7.3.8.1 Watchdog Fail Counter and Status
        2. 7.3.8.2 Watchdog Start-Up and Configuration
        3. 7.3.8.3 MCU to Watchdog Synchronization
        4. 7.3.8.4 Watchdog Disable Function
        5. 7.3.8.5 Watchdog Sequence
        6. 7.3.8.6 Watchdog Trigger Mode
        7. 7.3.8.7 WatchDog Flow Chart and Timing Diagrams in Trigger Mode
        8.       55
        9. 7.3.8.8 Watchdog Question-Answer Mode
          1. 7.3.8.8.1 Watchdog Q&A Related Definitions
          2. 7.3.8.8.2 Question Generation
          3. 7.3.8.8.3 Answer Comparison
            1. 7.3.8.8.3.1 Sequence of the 2-bit Watchdog Answer Counter
            2. 7.3.8.8.3.2 Watchdog Sequence Events and Status Updates
            3. 7.3.8.8.3.3 Watchdog Q&A Sequence Scenarios
      9. 7.3.9 Error Signal Monitor (ESM)
        1. 7.3.9.1 ESM Error-Handling Procedure
        2. 7.3.9.2 Level Mode
        3.       66
        4. 7.3.9.3 PWM Mode
          1. 7.3.9.3.1 Good-Events and Bad-Events
          2. 7.3.9.3.2 ESM Error-Counter
            1. 7.3.9.3.2.1 ESM Start-Up in PWM Mode
          3. 7.3.9.3.3 ESM Flow Chart and Timing Diagrams in PWM Mode
          4.        72
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device State Machine
        1. 7.4.1.1 Fixed Device Power FSM
          1. 7.4.1.1.1 Register Resets and EEPROM read at INIT state
        2. 7.4.1.2 Pre-Configurable Mission States
          1. 7.4.1.2.1 PFSM Commands
            1. 7.4.1.2.1.1  REG_WRITE_IMM Command
            2. 7.4.1.2.1.2  REG_WRITE_MASK_IMM Command
            3. 7.4.1.2.1.3  REG_WRITE_MASK_PAGE0_IMM Command
            4. 7.4.1.2.1.4  REG_WRITE_BIT_PAGE0_IMM Command
            5. 7.4.1.2.1.5  REG_WRITE_WIN_PAGE0_IMM Command
            6. 7.4.1.2.1.6  REG_WRITE_VOUT_IMM Command
            7. 7.4.1.2.1.7  REG_WRITE_VCTRL_IMM Command
            8. 7.4.1.2.1.8  REG_WRITE_MASK_SREG Command
            9. 7.4.1.2.1.9  SREG_READ_REG Command
            10. 7.4.1.2.1.10 SREG_WRITE_IMM Command
            11. 7.4.1.2.1.11 WAIT Command
            12. 7.4.1.2.1.12 DELAY_IMM Command
            13. 7.4.1.2.1.13 DELAY_SREG Command
            14. 7.4.1.2.1.14 TRIG_SET Command
            15. 7.4.1.2.1.15 TRIG_MASK Command
            16. 7.4.1.2.1.16 END Command
          2. 7.4.1.2.2 Configuration Memory Organization and Sequence Execution
          3. 7.4.1.2.3 Mission State Configuration
          4. 7.4.1.2.4 Pre-Configured Hardware Transitions
            1. 7.4.1.2.4.1 ON Requests
            2. 7.4.1.2.4.2 OFF Requests
            3. 7.4.1.2.4.3 NSLEEP1 and NSLEEP2 Functions
            4. 7.4.1.2.4.4 WKUP1 and WKUP2 Functions
        3. 7.4.1.3 Error Handling Operations
          1. 7.4.1.3.1 Power Rail Output Error
          2. 7.4.1.3.2 Boot BIST Error
          3. 7.4.1.3.3 Runtime BIST Error
          4. 7.4.1.3.4 Catastrophic Error
          5. 7.4.1.3.5 Watchdog (WDOG) Error
          6. 7.4.1.3.6 Error Signal Monitor (ESM) Error
          7. 7.4.1.3.7 Warnings
        4. 7.4.1.4 Device Start-up Timing
        5. 7.4.1.5 Power Sequences
        6. 7.4.1.6 First Supply Detection
      2. 7.4.2 Multi-PMIC Synchronization
        1. 7.4.2.1 SPMI Interface System Setup
        2. 7.4.2.2 Transmission Protocol and CRC
          1. 7.4.2.2.1 Operation with Transmission Errors
          2. 7.4.2.2.2 Transmitted Information
        3. 7.4.2.3 SPMI Target Device Communication to SPMI Controller Device
          1. 7.4.2.3.1 Incomplete Communication from SPMI Target Device to SPMI Controller Device
        4. 7.4.2.4 SPMI-BIST Overview
          1. 7.4.2.4.1 SPMI Bus during Boot BIST and RUNTIME BIST
          2. 7.4.2.4.2 Periodic Checking of the SPMI
          3. 7.4.2.4.3 SPMI Message Priorities
    5. 7.5 Control Interfaces
      1. 7.5.1 CRC Calculation for I2C and SPI Interface Protocols
      2. 7.5.2 I2C-Compatible Interface
        1. 7.5.2.1 Data Validity
        2. 7.5.2.2 Start and Stop Conditions
        3. 7.5.2.3 Transferring Data
        4. 7.5.2.4 Auto-Increment Feature
      3. 7.5.3 Serial Peripheral Interface (SPI)
    6. 7.6 NVM Configurable Registers
      1. 7.6.1 Register Page Partitioning
      2. 7.6.2 CRC Protection for Configuration, Control, and Test Registers
      3. 7.6.3 CRC Protection for User Registers
      4. 7.6.4 Register Write Protection
        1. 7.6.4.1 ESM and Watchdog Configuration Registers
        2. 7.6.4.2 User Registers
    7. 7.7 Register Map
      1. 7.7.1 LP876242_map Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Buck Inductor Selection
        2. 8.2.1.2 Buck Input Capacitor Selection
        3. 8.2.1.3 Buck Output Capacitor Selection
        4. 8.2.1.4 LDO Output Capacitor Selection
        5. 8.2.1.5 VCCA Supply Filtering Components
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Voltage Scaling Precautions
      4. 8.2.4 Application Curves
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
    4. 8.4 Power Supply Recommendations
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
7.3.2.1.4 BUCK Output Voltage Setting

Table 7-1 shows the coding used to select the BUCK regulator output voltage.

Table 7-1 Output Voltage Selection for BUCK Regulators
BUCKn_VSETn Output Voltage [V]
20 mV steps		 BUCKn_VSETn Output Voltage [V]
5 mV steps		 BUCKn_VSETn Output Voltage [V]
5 mV steps		 BUCKn_VSETn Output Voltage [V]
10 mV steps		 BUCKn_VSETn Output Voltage [V]
20 mV steps		 BUCKn_VSETn Output Voltage [V]
20 mV steps
0x00 0.3 0x0F 0.6 0x41 0.85 0x73 1.1 0xAB 1.66 0xD6 2.52
0x01 0.32 0x10 0.605 0x42 0.855 0x74 1.11 0xAC 1.68 0xD7 2.54
0x02 0.34 0x11 0.61 0x43 0.86 0x75 1.12 0xAD 1.7 0xD8 2.56
0x03 0.36 0x12 0.615 0x44 0.865 0x76 1.13 0xAE 1.72 0xD9 2.58
0x04 0.38 0x13 0.62 0x45 0.87 0x77 1.14 0xAF 1.74 0xDA 2.6
0x05 0.4 0x14 0.625 0x46 0.875 0x78 1.15 0xB0 1.76 0xDB 2.62
0x06 0.42 0x15 0.63 0x47 0.88 0x79 1.16 0xB1 1.78 0xDC 2.64
0x07 0.44 0x16 0.635 0x48 0.885 0x7A 1.17 0xB2 1.8 0xDD 2.66
0x08 0.46 0x17 0.64 0x49 0.89 0x7B 1.18 0xB3 1.82 0xDE 2.68
0x09 0.48 0x18 0.645 0x4A 0.895 0x7C 1.19 0xB4 1.84 0xDF 2.7
0x0A 0.5 0x19 0.65 0x4B 0.9 0x7D 1.2 0xB5 1.86 0xE0 2.72
0x0B 0.52 0x1A 0.655 0x4C 0.905 0x7E 1.21 0xB6 1.88 0xE1 2.74
0x0C 0.54 0x1B 0.66 0x4D 0.91 0x7F 1.22 0xB7 1.9 0xE2 2.76
0x0D 0.56 0x1C 0.665 0x4E 0.915 0x80 1.23 0xB8 1.92 0xE3 2.78
0x0E 0.58 0x1D 0.67 0x4F 0.92 0x81 1.24 0xB9 1.94 0xE4 2.8
0x1E 0.675 0x50 0.925 0x82 1.25 0xBA 1.96 0xE5 2.82
0x1F 0.68 0x51 0.93 0x83 1.26 0xBB 1.98 0xE6 2.84
0x20 0.685 0x52 0.935 0x84 1.27 0xBC 2 0xE7 2.86
0x21 0.69 0x53 0.94 0x85 1.28 0xBD 2.02 0xE8 2.88
0x22 0.695 0x54 0.945 0x86 1.29 0xBE 2.04 0xE9 2.9
0x23 0.7 0x55 0.95 0x87 1.3 0xBF 2.06 0xEA 2.92
0x24 0.705 0x56 0.955 0x88 1.31 0xC0 2.08 0xEB 2.94
0x25 0.71 0x57 0.96 0x89 1.32 0xC1 2.1 0xEC 2.96
0x26 0.715 0x58 0.965 0x8A 1.33 0xC2 2.12 0xED 2.98
0x27 0.72 0x59 0.97 0x8B 1.34 0xC3 2.14 0xEE 3.0
0x28 0.725 0x5A 0.975 0x8C 1.35 0xC4 2.16 0xEF 3.02
0x29 0.73 0x5B 0.98 0x8D 1.36 0xC5 2.18 0xF0 3.04
0x2A 0.735 0x5C 0.985 0x8E 1.37 0xC6 2.2 0xF1 3.06
0x2B 0.74 0x5D 0.99 0x8F 1.38 0xC7 2.22 0xF2 3.08
0x2C 0.745 0x5E 0.995 0x90 1.39 0xC8 2.24 0xF3 3.1
0x2D 0.75 0x5F 1.0 0x91 1.4 0xC9 2.26 0xF4 3.12
0x2E 0.755 0x60 1.005 0x92 1.41 0xCA 2.28 0xF5 3.14
0x2F 0.76 0x61 1.01 0x93 1.42 0xCB 2.3 0xF6 3.16
0x30 0.765 0x62 1.015 0x94 1.43 0xCC 2.32 0xF7 3.18
0x31 0.77 0x63 1.02 0x95 1.44 0xCD 2.34 0xF8 3.2
0x32 0.775 0x64 1.025 0x96 1.45 0xCE 2.36 0xF9 3.22
0x33 0.78 0x65 1.03 0x97 1.46 0xCF 2.38 0xFA 3.24
0x34 0.785 0x66 1.035 0x98 1.47 0xD0 2.4 0xFB 3.26
0x35 0.79 0x67 1.04 0x99 1.48 0xD1 2.42 0xFC 3.28
0x36 0.795 0x68 1.045 0x9A 1.49 0xD2 2.44 0xFD 3.3
0x37 0.8 0x69 1.05 0x9B 1.5 0xD3 2.46 0xFE 3.32
0x38 0.805 0x6A 1.055 0x9C 1.51 0xD4 2.48 0xFF 3.34
0x39 0.81 0x6B 1.06 0x9D 1.52 0xD5 2.5
0x3A 0.815 0x6C 1.065 0x9E 1.53
0x3B 0.82 0x6D 1.07 0x9F 1.54
0x3C 0.825 0x6E 1.075 0xA0 1.55
0x3D 0.83 0x6F 1.08 0xA1 1.56
0x3E 0.835 0x70 1.085 0xA2 1.57
0x3F 0.84 0x71 1.09 0xA3 1.58
0x40 0.845 0x72 1.095 0xA4 1.59
0xA5 1.6
0xA6 1.61
0xA7 1.62
0xA8 1.63
0xA9 1.64
0xAA 1.65