SNVSC07A June 2021 – September 2022 LP876242-Q1
PRODUCTION DATA
The LP876242-Q1 device includes a static CRC-16 engine to protect all the static registers of the device. Static registers are registers in Page 1, 2, and 3, with values that do not change once loaded from NVM. The CRC-16 engine continuously checks the control registers on the device. The expected CRC-16 value is stored in the NVM. When the CRC-16 engine detects a mismatch between the calculated and expected CRC-16 values, the interrupt bit REG_CRC_ERR_INT is set and the device forces an orderly shutdown sequence to return to the SAFE RECOVERY state. The device NVM control, configuration, and test registers in page 1 are protected against read or write access when the device is in normal functional mode. .
The CRC-16 engine uses a standard CRC-16 polynomial to calculate the internal known-good checksum-value, which is X16 + X14 + X13 + X12 + X10 + X8 + X6 + X4 + X3 + X + 1.
The initial value for the remainder of the polynomial is all 1s and is in big-endian bit-stream order. The inversion of the calculated result is enabled.
The CRC-16 engine assumes a default value of '0' for all undefined or reserved bits in all control registers. Therefore, the software MUST NOT write the value of '1' to any of these undefined or reserved bits. If the value of '1 is written to any undefined or reserved bit of a writable register, the CRC-16 engine detects a mismatch between the calculated and expected CRC-16 values, and hence the interrupt bit REG_CRC_ERR_INT is set and the device forces an orderly shutdown sequence to return to the SAFE RECOVERY state.