SNVSC07A June 2021 – September 2022 LP876242-Q1
PRODUCTION DATA
When the LP876242-Q1 device is configured to use the Watchdog Trigger Mode, the watchdog receives the watchdog-triggers from the MCU on the pre-assigned GPIO pin . A rising edge on this , followed by a stable logic-high level on that pin for more than the maximum pulse time, tWD_pulse(max), is a watchdog-trigger. The watchdog uses a deglitch filter with a tWD_pulse filter time and the internal 20-MHz system clock to create the internally-generated trigger pulse from the watchdog-trigger on the pre-assigned GPIO pin .
The watchdog detects a good event when the watchdog-trigger comes in Window-2. The rising edge of the watchdog-trigger on the pre-assigned GPIO pin must occur for at least the tWD_pulse time before the end of Window-2 to generate such a good event.
The watchdog detects a bad event when one of the following events occurs:
Please consider that the minimum WD-pulse duration needs to meet the maximum deglitch time tWD_pulse (max).
The status bit WD_BAD_EVENT is read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of the watchdog-sequence.
WatchDog Flow Chart and Timing Diagrams in Trigger Mode shows the flow-chart of the watchdog in Trigger mode.