SNVSC07A June 2021 – September 2022 LP876242-Q1
PRODUCTION DATA
The SPMI-BIST is performed during BIST state and regularly during runtime operation. Figure 7-45 below illustrates how the SPMI-BIST operates during device power-up.
After the input power is detected and verified to be at the correct level, the LP876242-Q1 initializes itself by reading the NVM and performs all actions that are needed to prepare for operation . After this initialization, the LP876242-Q1 enters the BOOT BIST state, in which the internal logic performs a series of tests to verify that the LP876242-Q1 device is OK. As part of this test, the SPMI- BIST is performed. After it is completed successfully, the LP876242-Q1 device goes to the standby state and waits for further signals from the system to initiate the power-up sequence of the processor.
A valid on request initiates the processor power-up sequence. The controller device communicates this event through the SPMI bus to all of the target devices. After that, the power-up sequence is executed and LP876242-Q1 enters the configured mission state.