SNVSC07A June   2021  – September 2022 LP876242-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Digital Signal Descriptions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Internal Low Drop-Out Regulators (LDOVINT)
    6. 6.6  BUCK1, BUCK2, BUCK3, and BUCK4 Regulators
    7. 6.7  Reference Generator (REFOUT)
    8. 6.8  Monitoring Functions
    9. 6.9  Clocks, Oscillators, and DPLL
    10. 6.10 Thermal Monitoring and Shutdown
    11. 6.11 System Control Thresholds
    12. 6.12 Current Consumption
    13. 6.13 Digital Input Signal Parameters
    14. 6.14 Digital Output Signal Parameters
    15. 6.15 I/O Pullup and Pulldown Resistance
    16. 6.16 I2C Interface
    17. 6.17 Serial Peripheral Interface (SPI)
    18.     25
    19. 6.18 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage Monitor
      2. 7.3.2 Power Resources
        1. 7.3.2.1 Buck Regulators
          1. 7.3.2.1.1 BUCK Regulator Overview
          2. 7.3.2.1.2 Spread-Spectrum Mode
          3. 7.3.2.1.3 Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support
          4. 7.3.2.1.4 BUCK Output Voltage Setting
          5. 7.3.2.1.5 Sync Clock Functionality
        2. 7.3.2.2 Internal Low Dropout Regulator (LDOVINT)
      3. 7.3.3 Residual Voltage Checking
      4. 7.3.4 Output Voltage Monitor and PGOOD Generation
      5. 7.3.5 General-Purpose I/Os (GPIO Pins)
      6. 7.3.6 Thermal Monitoring
        1. 7.3.6.1 Thermal Warning Function
        2. 7.3.6.2 Thermal Shutdown
      7. 7.3.7 Interrupts
      8. 7.3.8 Watchdog (WD)
        1. 7.3.8.1 Watchdog Fail Counter and Status
        2. 7.3.8.2 Watchdog Start-Up and Configuration
        3. 7.3.8.3 MCU to Watchdog Synchronization
        4. 7.3.8.4 Watchdog Disable Function
        5. 7.3.8.5 Watchdog Sequence
        6. 7.3.8.6 Watchdog Trigger Mode
        7. 7.3.8.7 WatchDog Flow Chart and Timing Diagrams in Trigger Mode
        8.       55
        9. 7.3.8.8 Watchdog Question-Answer Mode
          1. 7.3.8.8.1 Watchdog Q&A Related Definitions
          2. 7.3.8.8.2 Question Generation
          3. 7.3.8.8.3 Answer Comparison
            1. 7.3.8.8.3.1 Sequence of the 2-bit Watchdog Answer Counter
            2. 7.3.8.8.3.2 Watchdog Sequence Events and Status Updates
            3. 7.3.8.8.3.3 Watchdog Q&A Sequence Scenarios
      9. 7.3.9 Error Signal Monitor (ESM)
        1. 7.3.9.1 ESM Error-Handling Procedure
        2. 7.3.9.2 Level Mode
        3.       66
        4. 7.3.9.3 PWM Mode
          1. 7.3.9.3.1 Good-Events and Bad-Events
          2. 7.3.9.3.2 ESM Error-Counter
            1. 7.3.9.3.2.1 ESM Start-Up in PWM Mode
          3. 7.3.9.3.3 ESM Flow Chart and Timing Diagrams in PWM Mode
          4.        72
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device State Machine
        1. 7.4.1.1 Fixed Device Power FSM
          1. 7.4.1.1.1 Register Resets and EEPROM read at INIT state
        2. 7.4.1.2 Pre-Configurable Mission States
          1. 7.4.1.2.1 PFSM Commands
            1. 7.4.1.2.1.1  REG_WRITE_IMM Command
            2. 7.4.1.2.1.2  REG_WRITE_MASK_IMM Command
            3. 7.4.1.2.1.3  REG_WRITE_MASK_PAGE0_IMM Command
            4. 7.4.1.2.1.4  REG_WRITE_BIT_PAGE0_IMM Command
            5. 7.4.1.2.1.5  REG_WRITE_WIN_PAGE0_IMM Command
            6. 7.4.1.2.1.6  REG_WRITE_VOUT_IMM Command
            7. 7.4.1.2.1.7  REG_WRITE_VCTRL_IMM Command
            8. 7.4.1.2.1.8  REG_WRITE_MASK_SREG Command
            9. 7.4.1.2.1.9  SREG_READ_REG Command
            10. 7.4.1.2.1.10 SREG_WRITE_IMM Command
            11. 7.4.1.2.1.11 WAIT Command
            12. 7.4.1.2.1.12 DELAY_IMM Command
            13. 7.4.1.2.1.13 DELAY_SREG Command
            14. 7.4.1.2.1.14 TRIG_SET Command
            15. 7.4.1.2.1.15 TRIG_MASK Command
            16. 7.4.1.2.1.16 END Command
          2. 7.4.1.2.2 Configuration Memory Organization and Sequence Execution
          3. 7.4.1.2.3 Mission State Configuration
          4. 7.4.1.2.4 Pre-Configured Hardware Transitions
            1. 7.4.1.2.4.1 ON Requests
            2. 7.4.1.2.4.2 OFF Requests
            3. 7.4.1.2.4.3 NSLEEP1 and NSLEEP2 Functions
            4. 7.4.1.2.4.4 WKUP1 and WKUP2 Functions
        3. 7.4.1.3 Error Handling Operations
          1. 7.4.1.3.1 Power Rail Output Error
          2. 7.4.1.3.2 Boot BIST Error
          3. 7.4.1.3.3 Runtime BIST Error
          4. 7.4.1.3.4 Catastrophic Error
          5. 7.4.1.3.5 Watchdog (WDOG) Error
          6. 7.4.1.3.6 Error Signal Monitor (ESM) Error
          7. 7.4.1.3.7 Warnings
        4. 7.4.1.4 Device Start-up Timing
        5. 7.4.1.5 Power Sequences
        6. 7.4.1.6 First Supply Detection
      2. 7.4.2 Multi-PMIC Synchronization
        1. 7.4.2.1 SPMI Interface System Setup
        2. 7.4.2.2 Transmission Protocol and CRC
          1. 7.4.2.2.1 Operation with Transmission Errors
          2. 7.4.2.2.2 Transmitted Information
        3. 7.4.2.3 SPMI Target Device Communication to SPMI Controller Device
          1. 7.4.2.3.1 Incomplete Communication from SPMI Target Device to SPMI Controller Device
        4. 7.4.2.4 SPMI-BIST Overview
          1. 7.4.2.4.1 SPMI Bus during Boot BIST and RUNTIME BIST
          2. 7.4.2.4.2 Periodic Checking of the SPMI
          3. 7.4.2.4.3 SPMI Message Priorities
    5. 7.5 Control Interfaces
      1. 7.5.1 CRC Calculation for I2C and SPI Interface Protocols
      2. 7.5.2 I2C-Compatible Interface
        1. 7.5.2.1 Data Validity
        2. 7.5.2.2 Start and Stop Conditions
        3. 7.5.2.3 Transferring Data
        4. 7.5.2.4 Auto-Increment Feature
      3. 7.5.3 Serial Peripheral Interface (SPI)
    6. 7.6 NVM Configurable Registers
      1. 7.6.1 Register Page Partitioning
      2. 7.6.2 CRC Protection for Configuration, Control, and Test Registers
      3. 7.6.3 CRC Protection for User Registers
      4. 7.6.4 Register Write Protection
        1. 7.6.4.1 ESM and Watchdog Configuration Registers
        2. 7.6.4.2 User Registers
    7. 7.7 Register Map
      1. 7.7.1 LP876242_map Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Buck Inductor Selection
        2. 8.2.1.2 Buck Input Capacitor Selection
        3. 8.2.1.3 Buck Output Capacitor Selection
        4. 8.2.1.4 LDO Output Capacitor Selection
        5. 8.2.1.5 VCCA Supply Filtering Components
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Voltage Scaling Precautions
      4. 8.2.4 Application Curves
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
    4. 8.4 Power Supply Recommendations
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.2.2 Start and Stop Conditions

The device is controlled through an I2C-compatible interface. START and STOP conditions classify the beginning and end of the I2C session. A START condition is defined as the SDA signal going from HIGH to LOW while the SCL signal is HIGH. A STOP condition is defined as the SDA signal going from LOW to HIGH while the SCL signal is HIGH. The I2C controller device device always generates the START and STOP conditions.

GUID-EEA51CC7-8B36-4DAD-9969-8B1FE2ECCF4E-low.gifFigure 7-49 Start and Stop Sequences

The I2C bus is considered busy after a START condition and free after a STOP condition. The I2C controller device can generate repeated START conditions during data transmission. A START and a repeated START condition are equivalent function-wise. Figure 7-50 shows the SDA and SCL signal timing for the I2C-compatible bus. For timing values, see the Specification section.

GUID-7C3D1920-848E-4D4E-B060-BD2A9B5EE55F-low.gifFigure 7-50 I2C-Compatible Timing