The Fixed Device Power portion of the
FSM engine manages the power up of the device before the power rails are fully
enabled and ready to power external loadings, and the power down of the device when
in the event of insufficient power supply or device or system error conditions.
While the device is in one of the Hardware Device Powers states, the
ENABLE_DRV bit remains low.
The definitions and transition
triggers of the Device Power States are fixed and cannot be reconfigured.
Following are the definitions of the
Device Power states:
NO SUPPLYThe device is not powered by a valid energy source on the system power
rail. The device is completely powered off.
LP_STANDBYThe device can enter this state from a mission state after receiving a
valid OFF request by ENABLE pin or
I2C trigger and the LP_STANDBY_SEL = 1. The internal LDO (LDOVINT)
is enabled and VCCA monitoring is disabled to minimize power
dissipation. As the accurate VCCA monitoring is disabled, the VCCA
voltage must be above 1.7 V during LP_STANDBY state, or stay below
1.7 V for minimum 20 ms to ensure that the digital is reset
correctly. If this requirement for VCCA cannot be met, STANDBY state
must be used instead of LP_STANDBY. The wake-up from LP_STANDBY
state can be initiated by active edge on ENABLE signal or by WKUPx
pins.
INITThe device is powered by a valid supply on the system power rail (VCCA ≥
VCCA_UV). If the device was previously in LP_STANDBY state, it has
received an external wake-up signal at the WKUP1/2
pins, or an On Request from the ENABLE
pin. Device digital and monitor circuits are powered up. The PMIC reads
its internal NVM memory in this state and configures default values to
registers, IO configuration and FSM accordingly.
BOOT BISTThe device is running the built-in self-test routine
that includes both the ABIST , the LBIST/ and the CRC. An option is available to shorten the device power up time from the
NO_SUPPLY state by setting the NVM bit FAST_BOOT_BIST = '1' to skip
the LBIST. Software can also set the FAST_BIST = '1' to skip LBIST
after the device wakes up from the LP STANDBY state. When the device
arrives at this state from the SAFE_RECOVERY state, LBIST is
automatically skipped if it has not previously failed. If LBIST
failed, but passed after multiple re-tries before exceeding the
recovery counter limit, the device powers up normally. The
following NVM bits are pre-configured options that can be set to disable
parts of the ABIST orCRC tests if further sequence time reduction is
required (please refer to the User's Guide of the orderable part
number):
REG_CRC_EN = '0':
disables the register map and SRAM CRC check
VMON_ABIST_EN = '0': disables the ABIST for the VMON OV/UV
function
Note: Note: the BIST
tests are executed as parallel processes, and the longest process
determines the total BIST duration
RUNTIME BISTA request was received from the MCU to exercise a
run-time built-in self-test (RUNTIME_BIST) on the device. No rails are
modified and all external signals, including all I2C or SPI
interface communications, are ignored during BIST. If the device passed
BIST, it resumes the previous operation. If the device failed BIST, it
shuts down all of the regulator outputs and proceed to the SAFE RECOVERY
state. In order to avoid a register CRC error, all register writes must
be avoided after the request for the BIST operation until the device
pulls the nINT pin low to indicate the completion of BIST. The results
of the BIST are indicated by the BIST_PASS_INT or the BIST_FAIL_INT
bits.
Note:
For executing the
RUNTIME_BIST, the system software must perform following
steps:
Before
RUNTIME_BIST request:
1) Set VCCA_UV_MASK,
VCCA_OV_MASK, all BUCKx_UV_MASK, all BUCKx_OV_MASK, VMONx_UV_MASK and
VMONx_OV_MASK bits to 1
2)
If PGOOD pin is used, clear all PGOOD_SEL_BUCKx and
PGOOD_SEL_VMONx bits to 0
After completion
of RUNTIME_BIST:
1) Clear
VCCA_UV_MASK, VCCA_OV_MASK,
all VMONx_UV_MASK, all VMONx_OV_MASK, all BUCKx_UV_MASK and all
BUCKx_OV_MASK bits to 0
SAFE RECOVERYThe device meets the qualified error condition for immediate or ordered
shutdown request. If the error is recovered within the recovery time
interval or meets the restart condition, the device increments the
recovery counter, and returns to INIT state if the recovery counter
value does not exceed the threshold value. Until a supply power cycle
occurs, the device stays in the SAFE RECOVERY state if one of the
following conditions occur:
the recovery counter exceeds the threshold value
the die temperature cannot be reduced to less than
TWARN level
VCCA stays above OVP threshold
When multiple system conditions occur
simultaneously that demand power state arbitration, the device goes to the higher
priority state according to the following priority order:
NO SUPPLY
SAFE_RECOVERY
LP_STANDBY
MISSION STATES
Figure 7-35 shows the power transition states of the FSM engine.