SNVSC07A June   2021  – September 2022 LP876242-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Digital Signal Descriptions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Internal Low Drop-Out Regulators (LDOVINT)
    6. 6.6  BUCK1, BUCK2, BUCK3, and BUCK4 Regulators
    7. 6.7  Reference Generator (REFOUT)
    8. 6.8  Monitoring Functions
    9. 6.9  Clocks, Oscillators, and DPLL
    10. 6.10 Thermal Monitoring and Shutdown
    11. 6.11 System Control Thresholds
    12. 6.12 Current Consumption
    13. 6.13 Digital Input Signal Parameters
    14. 6.14 Digital Output Signal Parameters
    15. 6.15 I/O Pullup and Pulldown Resistance
    16. 6.16 I2C Interface
    17. 6.17 Serial Peripheral Interface (SPI)
    18.     25
    19. 6.18 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage Monitor
      2. 7.3.2 Power Resources
        1. 7.3.2.1 Buck Regulators
          1. 7.3.2.1.1 BUCK Regulator Overview
          2. 7.3.2.1.2 Spread-Spectrum Mode
          3. 7.3.2.1.3 Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support
          4. 7.3.2.1.4 BUCK Output Voltage Setting
          5. 7.3.2.1.5 Sync Clock Functionality
        2. 7.3.2.2 Internal Low Dropout Regulator (LDOVINT)
      3. 7.3.3 Residual Voltage Checking
      4. 7.3.4 Output Voltage Monitor and PGOOD Generation
      5. 7.3.5 General-Purpose I/Os (GPIO Pins)
      6. 7.3.6 Thermal Monitoring
        1. 7.3.6.1 Thermal Warning Function
        2. 7.3.6.2 Thermal Shutdown
      7. 7.3.7 Interrupts
      8. 7.3.8 Watchdog (WD)
        1. 7.3.8.1 Watchdog Fail Counter and Status
        2. 7.3.8.2 Watchdog Start-Up and Configuration
        3. 7.3.8.3 MCU to Watchdog Synchronization
        4. 7.3.8.4 Watchdog Disable Function
        5. 7.3.8.5 Watchdog Sequence
        6. 7.3.8.6 Watchdog Trigger Mode
        7. 7.3.8.7 WatchDog Flow Chart and Timing Diagrams in Trigger Mode
        8.       55
        9. 7.3.8.8 Watchdog Question-Answer Mode
          1. 7.3.8.8.1 Watchdog Q&A Related Definitions
          2. 7.3.8.8.2 Question Generation
          3. 7.3.8.8.3 Answer Comparison
            1. 7.3.8.8.3.1 Sequence of the 2-bit Watchdog Answer Counter
            2. 7.3.8.8.3.2 Watchdog Sequence Events and Status Updates
            3. 7.3.8.8.3.3 Watchdog Q&A Sequence Scenarios
      9. 7.3.9 Error Signal Monitor (ESM)
        1. 7.3.9.1 ESM Error-Handling Procedure
        2. 7.3.9.2 Level Mode
        3.       66
        4. 7.3.9.3 PWM Mode
          1. 7.3.9.3.1 Good-Events and Bad-Events
          2. 7.3.9.3.2 ESM Error-Counter
            1. 7.3.9.3.2.1 ESM Start-Up in PWM Mode
          3. 7.3.9.3.3 ESM Flow Chart and Timing Diagrams in PWM Mode
          4.        72
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device State Machine
        1. 7.4.1.1 Fixed Device Power FSM
          1. 7.4.1.1.1 Register Resets and EEPROM read at INIT state
        2. 7.4.1.2 Pre-Configurable Mission States
          1. 7.4.1.2.1 PFSM Commands
            1. 7.4.1.2.1.1  REG_WRITE_IMM Command
            2. 7.4.1.2.1.2  REG_WRITE_MASK_IMM Command
            3. 7.4.1.2.1.3  REG_WRITE_MASK_PAGE0_IMM Command
            4. 7.4.1.2.1.4  REG_WRITE_BIT_PAGE0_IMM Command
            5. 7.4.1.2.1.5  REG_WRITE_WIN_PAGE0_IMM Command
            6. 7.4.1.2.1.6  REG_WRITE_VOUT_IMM Command
            7. 7.4.1.2.1.7  REG_WRITE_VCTRL_IMM Command
            8. 7.4.1.2.1.8  REG_WRITE_MASK_SREG Command
            9. 7.4.1.2.1.9  SREG_READ_REG Command
            10. 7.4.1.2.1.10 SREG_WRITE_IMM Command
            11. 7.4.1.2.1.11 WAIT Command
            12. 7.4.1.2.1.12 DELAY_IMM Command
            13. 7.4.1.2.1.13 DELAY_SREG Command
            14. 7.4.1.2.1.14 TRIG_SET Command
            15. 7.4.1.2.1.15 TRIG_MASK Command
            16. 7.4.1.2.1.16 END Command
          2. 7.4.1.2.2 Configuration Memory Organization and Sequence Execution
          3. 7.4.1.2.3 Mission State Configuration
          4. 7.4.1.2.4 Pre-Configured Hardware Transitions
            1. 7.4.1.2.4.1 ON Requests
            2. 7.4.1.2.4.2 OFF Requests
            3. 7.4.1.2.4.3 NSLEEP1 and NSLEEP2 Functions
            4. 7.4.1.2.4.4 WKUP1 and WKUP2 Functions
        3. 7.4.1.3 Error Handling Operations
          1. 7.4.1.3.1 Power Rail Output Error
          2. 7.4.1.3.2 Boot BIST Error
          3. 7.4.1.3.3 Runtime BIST Error
          4. 7.4.1.3.4 Catastrophic Error
          5. 7.4.1.3.5 Watchdog (WDOG) Error
          6. 7.4.1.3.6 Error Signal Monitor (ESM) Error
          7. 7.4.1.3.7 Warnings
        4. 7.4.1.4 Device Start-up Timing
        5. 7.4.1.5 Power Sequences
        6. 7.4.1.6 First Supply Detection
      2. 7.4.2 Multi-PMIC Synchronization
        1. 7.4.2.1 SPMI Interface System Setup
        2. 7.4.2.2 Transmission Protocol and CRC
          1. 7.4.2.2.1 Operation with Transmission Errors
          2. 7.4.2.2.2 Transmitted Information
        3. 7.4.2.3 SPMI Target Device Communication to SPMI Controller Device
          1. 7.4.2.3.1 Incomplete Communication from SPMI Target Device to SPMI Controller Device
        4. 7.4.2.4 SPMI-BIST Overview
          1. 7.4.2.4.1 SPMI Bus during Boot BIST and RUNTIME BIST
          2. 7.4.2.4.2 Periodic Checking of the SPMI
          3. 7.4.2.4.3 SPMI Message Priorities
    5. 7.5 Control Interfaces
      1. 7.5.1 CRC Calculation for I2C and SPI Interface Protocols
      2. 7.5.2 I2C-Compatible Interface
        1. 7.5.2.1 Data Validity
        2. 7.5.2.2 Start and Stop Conditions
        3. 7.5.2.3 Transferring Data
        4. 7.5.2.4 Auto-Increment Feature
      3. 7.5.3 Serial Peripheral Interface (SPI)
    6. 7.6 NVM Configurable Registers
      1. 7.6.1 Register Page Partitioning
      2. 7.6.2 CRC Protection for Configuration, Control, and Test Registers
      3. 7.6.3 CRC Protection for User Registers
      4. 7.6.4 Register Write Protection
        1. 7.6.4.1 ESM and Watchdog Configuration Registers
        2. 7.6.4.2 User Registers
    7. 7.7 Register Map
      1. 7.7.1 LP876242_map Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Buck Inductor Selection
        2. 8.2.1.2 Buck Input Capacitor Selection
        3. 8.2.1.3 Buck Output Capacitor Selection
        4. 8.2.1.4 LDO Output Capacitor Selection
        5. 8.2.1.5 VCCA Supply Filtering Components
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Voltage Scaling Precautions
      4. 8.2.4 Application Curves
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Layout Example
    4. 8.4 Power Supply Recommendations
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 BUCK1, BUCK2, BUCK3, and BUCK4 Regulators

Over operating free-air temperature range (unless otherwise noted). Voltage level refers to the AGNDx ground of the device.
POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Electrical Characteristics - Output Voltage
3.1b VVOUT_Bx_Step Output voltage programmable step size 0.9 V ≤ VVOUT_Bx < 1.1 V 5 mV
3.1c 1.1 V ≤ VVOUT_Bx < 1.66 V 10
3.1d 1.66 V ≤ VVOUT_Bx ≤ 1.9 V 20
3.3 Input and output voltage difference Minimum voltage between PVIN_Bx and VOUT_Bx to fulfill the electrical characteristics 0.7 V
3.4a VVOUT_Bx_Slew_Rate Output voltage slew-rate programmable range(5)(6)(8) BUCKn_SLEW_RATE[2:0] = 000b 26.6 33.3 36.6 mV/µs
3.4b BUCKn_SLEW_RATE[2:0] = 001b 17 20 22
3.4c BUCKn_SLEW_RATE[2:0] = 010b 9 10 11
3.4d BUCKn_SLEW_RATE[2:0] = 011b 4.5 5 5.5
3.4e BUCKn_SLEW_RATE[2:0] = 100b 2.25 2.5 2.75
3.4f BUCKn_SLEW_RATE[2:0] = 101b 1.12 1.25 1.38
3.4g BUCKn_SLEW_RATE[2:0] = 110b 0.56 0.625 0.69
3.4h BUCKn_SLEW_RATE[2:0] = 111b 0.281 0.3125 0.344
Electrical Characteristics - Output Current, Limits and Thresholds
3.6e IOUT_Bx Output current(3)(4) Buck1 2 A
3.6f Buck2 4
3.6g Buck3 / Buck4 3
3.8 ILIM FWD PEAK Range Forward current limit (peak during each switching cycle) Programmable range 2.5 6.5 A
3.9 ILIM FWD PEAK Step Forward current limit step Size 1 A
3.10a ILIM FWD PEAK Accuracy Forward current limit accuracy ILIM = 2.5 A, 3.5 A, 4.5 A, 3.0 V ≤ VPVIN_Bx ≤ 5.5 V -0.55 0.55 A
3.10b ILIM = 5.5 A, 6.5 A 4.5 V ≤ VPVIN_Bx ≤ 5.5 V –10% 10%
3.10c ILIM = 5.5 A, 6.5 A 3.0 V ≤ VPVIN_Bx ≤ 4.5 V –15% 10%
3.11 ILIM NEG Negative current limit (peak during each switching cycle) 1.5 2 2.6 A
Electrical Characteristics - Current Consumption, On Resistance, and Output Pulldown Resistance
3.17 Ioff Shutdown current, BUCKx disabled 1 µA
3.19 RDS(ON) HS FET On-resistance, high-side FET IOUT_Bx = 1 A 26 65 mΩ
3.20 RDS(ON) LS FET On-resistance, low-side FET IOUT_Bx = 1 A 16 35 mΩ
3.21 RDIS_Bx Output pulldown discharge resistance Regulator disabled, per phase, BUCKx_PLDN = 1, between SW_Bx and PGND pins 50 100 150 Ω
3.21b VTH_SC_RV_Bx Threshold voltage for Short Circuit and Residual Voltage Detection 140 150 160 mV
3.22 RSW_SC Resistance threshold for Short circuit detection at the SW pin 3 5 25 Ω
Electrical Characteristics - 8.8MHz Single-Phase Configuration
3.96 VPVIN_Bx Input voltage range 3.0 3.3 5.5 V
3.97a VVOUT_Bx Output voltage programmable range IOUT_Bx ≤ 3 A 0.9 1.9 V
3.97b IOUT_Bx ≤ 4 A 0.9 1.4
3.98 CIN_Bx Input filtering capacitance(1)(2) 3 22 µF
3.99a COUT-Local_Bx Output capacitance, local with filter(2) 24 44 106 µF
3.99b COUT-Filter_Bx Output capacitance, after filter(2) Capacitance after every filter 20 33 80 µF
3.99c COUT-No_Filter_Bx Output capacitance, no filter(2) 24 44 106 µF
3.100a LBx Power inductor Inductance 329 470 611 nH
3.100b DCR 10 mΩ
3.100c LExt Filter1 Inductor, 100nH 70 100 130 nH
3.100d LExt Filter2 Ferrite, MPZ2012S300A
3.101 IQ_PWM PWM mode Quiescent current IOUT_Bx = 0 mA 30 mA
3.167a VOUT_DC_Bx DC output voltage accuracy, includes voltage reference, DC load and line regulations and temperature VVOUT_Bx < 1 V, PWM mode –10 10 mV
3.167b VVOUT_Bx ≥ 1 V, PWM mode –1% 1%
3.103a TLDSR Transient load step response, 1V8(8) CLocal as in Pos3.99a, no additional filter: VVOUT_Bx = 1.8 V, IOUT_Bx = 0.5 A to 1.8 A, tr = tf = 4 µs 18 mV
3.103c Transient load step response, 1V2(8) CLocal as in Pos3.99a, no additional filter: VVOUT_Bx = 1.2 V, IOUT_Bx = 1.95 A to 3 A, tr = tf = 1 µs 20
3.103e Transient load step response, 1V0(8) CLocal as in Pos3.99a, no additional filter: VVOUT_Bx = 1.0 V, IOUT_Bx = 0 A to 2.5 A, tr = tf = 4 µs 34
3.104 TLNSR Transient line response, no filter VPVIN_Bx stepping between 3 V and 3.5 V or between 4.8 V and 5.3 V, tr = tf = 10 µs, IOUT_Bx = IOUT(max) -25 ±5 25 mV
3.105 VOUT_Ripple Ripple voltage(7) PWM mode 4 mVPP
Timing Requirements
3.108 Settling time after voltage scaling From end of voltage ramp to VOUT within 15 mV from VOUT_DC_Bx(9) 105 µs
3.109 Start-up delay From enable to start of output voltage rise 100 150 200 µs
3.110 tdelay_OC Over-current detection delay Peak current limit triggering during every switching cycle 7 µs
3.111 tdeglitch_OC Over-current detection signal deglitch time Digital deglitch time for detected signal. Time duration to filter out short positive and negative pulses 19 23 µs
3.112 tlatency_OC Over-current signal latency time from detection Total delay from over-current detection to interrupt or PFSM trigger 30 µs
Switching Characteristics
3.106c fSW Switching frequency, PWM mode NVM programmable 8.8 MHz setting, internal clock 8 8.8 9.6 MHz
3.106f 8.8 MHz setting, internal clock, spread spectrum enabled 7.0 8.8 10.6
3.106i 8.8 MHz setting, synchronized to external clock 7.0 8.8 10.6
(1) Input capacitors must be placed as close as possible to the device pins.
(2) When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given dc voltage at the outputs of regulators.
(3) The maximum output current can be limited by the forward current limit ILIM FWD. The maximum output current is also limited by the junction temperature and maximum average current over lifetime. The power dissipation inside the die increases the junction temperature and limits the maximum current depending of the length of the current pulse, efficiency, board and ambient temperature.
(4) Advance thermal design is required to avoid thermal shutdown.
(5) SLEW_RATEx[2:0] register default comes from NVM memory, and can be re-programed by software. Output capacitance, forward and negative current limits and load current may limit the maximum and minimum slew rates.
(6) A high slew-rate setting can generate over and undershoot during voltage change. See Application Section for more information.
(7) Please refer to the applications section of the data sheet regarding the power delivery network (PDN) used for the transient load step and output ripple test conditions. All ripple specs are defined across POL capacitor in the described PDN.
(8) Slew-rate is measured from 10% to 90% of the voltage ramp with voltage step ≥ 500 mV.
(9) Voltage ramp is calculated using slew-rate from minimum column.