SNVSC07A June 2021 – September 2022 LP876242-Q1
PRODUCTION DATA
POS | PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|---|
Switching Characteristics: 20-MHz and 128-kHz RC OSCILLATOR CLOCK | |||||||
6.2 | 20 MHz RC Oscillator output frequency | 19 | 20 | 21 | MHz | ||
6.4 | 128 kHz RC Oscillator output frequency | 121 | 128 | 135 | kHz | ||
Switching Characteristics: DPLL, SYNCCLKIN, and SYNCCLKOUT | |||||||
6.6a | External input clock nominal frequency | EXT_CLK_FREQ = 0x0 | 1.1 | MHz | |||
6.6b | EXT_CLK_FREQ = 0x1 | 2.2 | |||||
6.6c | EXT_CLK_FREQ = 0x2 | 4.4 | |||||
6.6d | EXT_CLK_FREQ = 0x3 | 8.8 | |||||
6.7a | External input clock required accuracy from nominal frequency(1) | SS_DEPTH = 0x0 (Spread-spectrum disabled) | –18% | 18% | |||
6.7b | SS_DEPTH = 0x1 | –10% | 10% | ||||
6.7c | SS_DEPTH = 0x2 | –8% | 8% | ||||
6.8a | Logic low time for SYNCCLKIN clock | 40 | ns | ||||
6.8b | Logic high time for SYNCCLKIN clock | 40 | ns | ||||
6.9a | External clock detection delay for missing clock detection | 1.8 | µs | ||||
6.10 | Clock change delay (internal to external) | Delay from valid clock detection to use of external clock | 600 | µs | |||
6.11a | SYNCCLKOUT clock nominal frequency | SYNCCLKOUT_FREQ_SEL = 0x1 | 1.1 | MHz | |||
6.11b | SYNCCLKOUT_FREQ_SEL = 0x2 | 2.2 | |||||
6.11c | SYNCCLKOUT_FREQ_SEL = 0x3 | 4.4 | |||||
6.12 | SYNCCLKOUT duty-cycle | Cycle-to-cycle | 40% | 50% | 60% | ||
6.13 | SYNCCLKOUT output buffer external load | TJ = 25°C | 5 | 35 | 50 | pF | |
6.15a | Spread spectrum variation from nominal frequency | SS_DEPTH = 0x1 | ±6.3% | ||||
6.15b | SS_DEPTH = 0x2 | ±8.4% | |||||
6.17a | tlatency_CLKfail | Clock Monitor Failure signal latency from detection | Failure on 20 MHz system clock | 10 | µs | ||
6.17b | Failure on 128 kHz monitoring clock | 40 | µs | ||||
6.18 | tlatency_CLKdrift | Clock Monitor Drift signal latency from detection | 115 | µs | |||
6.19 | fsysclk | Internal system clock | 19 | 20 | 21 | MHz | |
6.20 | CLKdrift_TH | Threshold for internal system clock frequency drift detection | -20% | 20% | |||
6.21 | CLKfail_TH | Threshold for internal system clock stuck at high or stuck at low detection | 10 | MHz |