The device supports SPI serial-bus
interface and it operates as a peripheral device. The MCU in the system acts as
the controller device. A single read and write transmission consists of 24-bit
write and read cycles (32-bit if CRC is enabled) in the following order:
- Bits 1-8: ADDR[7:0],
Register address
- Bits 9-11: PAGE[2:0],
Page address for register
- Bit 12: Read/Write
definition, 0 = WRITE, 1 = READ.
- Bits 13-16:
RESERVED[4:0], Reserved, use all zeros.
- For Write: Bits 17-24:
WDATA[7:0], write data
- For Write with CRC
enabled: Bits 25-32: R_CRC[7:0], CRC error code calculated from bits
1-24 sent by the controller device (i.e. the MCU). See Section 8.11.1.
- For Read: Bits 17-24:
RDATA[7:0], read data
- For Read with CRC
enabled: Bits 25-32: T_CRC[7:0], CRC error code calculated from bits
1-16 sent by the controller device (i.e. the MCU), and bits 17-24, sent
by the peripheral device (i.e. the LP8764-Q1). See Section 8.11.1.
In parallel with ADDR[7:0],
PAGE[2:0], Read/Write definition and RESERVED[3:0] bits the device sends 16-bit
interrupt status using SDO_SPI pin in the following order:
- Bit 1: always 0
- Bits 2-8: status of
several interrupts and EN_DRV pin
- Bit 9: always 1
- Bits 10-16: status of
several interrupts and EN_DRV pin, with opposite polarity
The status signals are in
INT_SPI_STATUS register:
- Bit 8: always 0
- Bit 7:
COMM_ADR_ERR_SWINT
- Bit 6:
COMM_CRC_ERR_SWINT
- Bit 5:
COMM_FRM_ERR_SWINT
- Bit 4:
ESM_MCU_PIN_SWINT
- Bit 3: TWARN_SWINT
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