SNVSCC5 December   2023 LP87725-Q1

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Description (continued)
  6. 5Pin Configuration and Functions
    1. 5.1 Digital Signal Descriptions
  7. 6Device and Documentation Support
    1. 6.1 Documentation Support
    2. 6.2 Receiving Notification of Documentation Updates
    3. 6.3 Support Resources
    4. 6.4 Trademarks
    5. 6.5 Electrostatic Discharge Caution
    6. 6.6 Glossary
  8. 7Revision History
  9. 8Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • RAG|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.1 Digital Signal Descriptions

Table 5-2 Input Signal Descriptions
PIN NAMEPOWER DOMAIN (recommended max)INTERNAL PU/PDDEGLITCH TIME
nERRVCCA10 kΩ PU to VCCA15 µs
WD_DISVCCA-30 µs
SCLVCCA--
SDAVCCA--
VMON1VCCA-LDO_LS1_VMON1_DEGLITCH_SEL
VMON2 VCCA - LS2_VMON2_DEGLITCH_SEL
SYNCCLKVCCA400 kΩ PD to GND-
ENABLEVCCA400 kΩ PD to GND8 µs
GPIO ( I2C Address select) VCCA - 8 µs

ENABLE input is always functional when VCCA is at the valid level. Other input buffers are disabled until the valid VCCA supply is present and the device startup has progressed to a certain state. The input buffers are enabled after the OTP is read.

Table 5-3 Output Signal Descriptions
PIN NAMEPOWER DOMAINPIN MODEOUTPUT TYPEINTERNAL PU/PD
SDAVCCA--
nRSTOUTVCCA-Open-drain or push-pull
Active low or active high		In OD mode 10 kΩ programmable PU to VCCA when output driven high. PU disabled when output driven low.
nINT/GPOVCCA-Open-drain or push-pull
Active low or active high		In OD mode 10 kΩ programmable PU to VCCA when output driven high. PU disabled when output driven low.