SLVSH98A July 2023 – November 2023 LP8868U-Q1 , LP8868V-Q1 , LP8868W-Q1 , LP8868X-Q1 , LP8868Y-Q1 , LP8868Z-Q1
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
INPUT SUPPLY | ||||||
VVIN_UVLO | VIN undervoltage lockout | Rising VIN | 3.0 | 3.2 | 3.4 | V |
Falling VIN | 2.8 | 3.0 | 3.2 | V | ||
Hysteresis | 0.2 | V | ||||
ISD | Shut down current from VIN | VIN = 12 V, VEN/PWM = 0 V | 0.8 | 2.3 | µA | |
IOFF | PWM off current from VIN | VIN = 12 V, VEN/PWM = 0 V | 2.5 | mA | ||
IOP | Normal operating current | 400-kHz switching frequency | 4.6 | mA | ||
IOP | Normal operating current | 2.2-MHz switching frequency | 10.0 | mA | ||
VVCC | Internal LDO output voltage | IVCC = 10mA | 5.0 | 5.15 | 5.3 | V |
IVCC_LIM | Internal LDO output current limit | 38 | 47 | 56 | mA | |
DIMMING | ||||||
VPWM_L | Low-level input voltage | 0.4 | V | |||
VPWM_H | High-level input voltage | 1.2 | V | |||
VADIM_L | Low-level input voltage | 0.4 | V | |||
VADIM_H | High-level input voltage | 1.2 | V | |||
tPWM_OUT_ON | PWM output minimum on time | 150 | ns | |||
tPWM_IN_ON | PWM input minimum on time | 150 | ns | |||
tPWM_IN_OFF | PWM input minimum off time to disable device | 57 | 77 | ms | ||
fADIM | Analog Dimming input frequency | 6-bit ADIM resolution | 0.1 | 156 | kHz | |
fADIM | Analog Dimming input frequency | 8-bit ADIM resolution | 0.1 | 39 | kHz | |
FAULT | ||||||
VOL | Output level low | I = 3mA | 0.1 | V | ||
ILEAKAGE | Output leakage current | V = 5 V | 1 | µA | ||
FEEDBACK AND ERROR AMPLIFIER | ||||||
gM(ea) | Transconductance gain | ADIM 100% duty cycle, VCSP-CSN = 200mV, VCOMP = 1.5V | 205 | 265 | 325 | μA/V |
ICOMP | Source/sink current | ADIM 100% duty cycle, VCSP-CSN = 200mV ± 200mV, VCOMP = 1.5V | ±24 | ±40 | ±56 | µA |
VCSP-CSN | Current sense threshold | ADIM 100% duty cycle | 194 | 200 | 206 | mV |
VCSP-CSN | Current sense threshold | ADIM 12.5% duty cycle, compared with 100% duty cycle | 11.875 | 12.5 | 13.125 | % |
VCSP-CSN | Current sense threshold | ADIM 1.17% duty cycle, compared with 100% duty cycle | 0.82 | 1.17 | 1.52 | % |
ILEAK_CSP/N | CSP+CSN pin leakage current | VIN = 60 V, VEN/PWM = 5 V | 22 | 31 | µA | |
ILEAK_CSP/N | CSP+CSN pin leakage current | VIN = 60 V, VEN/PWM = 0 V | 10 | 15 | µA | |
POWER STAGE | ||||||
RDSON | Switching FET on resistance | VIN ≥ 5 V | 150 | mΩ | ||
tmin_ON | Switching FET minimum on time | 100 | ns | |||
tmin_OFF | Switching FET minimum off time | 100 | ns | |||
fSW | Switching FET frequency | 0.1 | 2.2 | MHz | ||
CURRENT LIMIT | ||||||
ILIM | Switching FET cycle-by-cycle current limit (LP8868X/LP8868Y/LP8868U/LP8868V) | 5.8 | 6.5 | 7.6 | A | |
ILIM | Switching FET cycle-by-cycle current limit (LP8868Z/LP8868W) | 5.2 | 6 | 7 | A | |
THERMAL PROTECTION | ||||||
Tth | Thermal foldback starting temperature threshold | RTEMP = 20 kΩ | 130 | °C | ||
TTSD | Thermal shutdown temperature | 165 | °C | |||
Hysteresis | 15 | °C |