SDLS975 April   2024 LSF0002

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics (Translating Down): BN = 3.3V
    7. 5.7 Switching Characteristics (Translating Down): BN = 2.5V
    8. 5.8 Switching Characteristics (Translating Up): BN = 3.3V
    9. 5.9 Switching Characteristics (Translating Up):BN = 2.5V
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Auto Bidirectional Voltage Translation
      2. 7.3.2 VBIAS/ Enable
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Open-Drain Interface (I2C, PMBus, SMBus, and GPIO)
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Enable and Disable Guidelines
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Bidirectional Translation
          2. 8.2.1.2.2 Pull-Up Resistor Sizing
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Mixed-Mode Voltage Translation
      3. 8.2.3 Voltage Translation for Vref_B < Vref_A + 0.8V
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DTQ|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The LSF0002 supports bidirectional voltage translation without the need for DIR pin, which minimizes system effort (for PMBus, I2C, SMBus, and so forth). The LSF family of devices supports up to 100MHz up translation and greater than 100MHz down translation at ≤ 30pF capacitive load and up to 40MHz up or down translation at 50pF capacitive load, which allows the LSF family to support more consumer or telecom interfaces (MDIO or SDIO).

LSF family supports 5V tolerance on I/O port, which makes it compatible with TTL levels in industrial and telecom applications. The LSF family can set up different voltage translation levels, which makes it very flexible.

Unlike the LSF0x0x family, the LSF0002 does not require VREF_A and VREF_B power supplies and the 200kΩ bias resistor. The LSF0002 utilizes the VBIAS pin that enables translation by being biased to the same voltage as the lower power supply at the I/Os that is being translated to and from.

Package Information
PART NUMBERPACKAGE(1)PACKAGE SIZE(2)
LSF0002DTQ (X2SON, 6)1mm × 0.8mm
(1) For more information, see Section 11.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
LSF0002 Functional Block Diagram Functional Block Diagram