SLVS033G February   1990  – July 2015 LT1054

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Reference and Error Amplifier for Regulation
      2. 7.3.2 External Oscillator Synchronization
      3. 7.3.3 Output Current and Voltage Loss
      4. 7.3.4 Reference Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Main Operation
      2. 7.4.2 Shutdown
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Voltage Programming
        2. 8.2.2.2 Capacitor Selection
        3. 8.2.2.3 Output Ripple
        4. 8.2.2.4 Power Dissipation
      3. 8.2.3 Application Curve
    3. 8.3 System Examples
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • P|8
  • DW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

  • Try to run the feedback trace as far from the noisy power or clocking traces as possible. In the case that the OSC pin is not being used, as in Figure 31, the FB trace can be ran on a lower layer under the OSC pin. When OSC is being utilized by a noisy clocking signal, it is recommended to run the FB trace on a lower layer through the Vref pin.
    • Keep the FB trace to be as direct as possible and somewhat thick. These two sometimes involve a trade-off, but keeping it away from EMI and other noise sources is the more critical of the two.
  • Keep the external capacitor traces short, specifically on the CAP+ and CAP- nodes that have the fastest rise and fall times.
  • Make all of the power (high current) traces as short, direct, and thick as possible. It is good practice on a standard PCB board to make the traces an absolute minimum of 15 mils (0.381 mm) per Ampere.

10.2 Layout Example

LT1054 lt1054_layout.gifFigure 31. Basic Inverter/Regulator Layout