SLLSFI0C august   2021  – june 2023 MCF8316A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Output Stage
      2. 7.3.2  Device Interface Modes
        1. 7.3.2.1 Interface - Control and Monitoring
        2. 7.3.2.2 I2C Interface
      3. 7.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 7.3.3.1 Buck in Inductor Mode
        2. 7.3.3.2 Buck in Resistor mode
        3. 7.3.3.3 Buck Regulator with External LDO
        4. 7.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 7.3.3.5 Mixed Mode Buck Operation and Control
        6. 7.3.3.6 Buck Undervoltage Protection
        7. 7.3.3.7 Buck Overcurrent Protection
      4. 7.3.4  AVDD Linear Voltage Regulator
      5. 7.3.5  Charge Pump
      6. 7.3.6  Slew Rate Control
      7. 7.3.7  Cross Conduction (Dead Time)
      8. 7.3.8  SPEED Control
        1. 7.3.8.1 Analog-Mode Speed Control
        2. 7.3.8.2 PWM-Mode Speed Control
        3. 7.3.8.3 I2C based Speed Control
        4. 7.3.8.4 Frequency-Mode Speed Control
        5. 7.3.8.5 Speed Profiles
          1. 7.3.8.5.1 Linear Speed Profiles
          2. 7.3.8.5.2 Staircase Speed Profiles
          3. 7.3.8.5.3 Forward-Reverse Speed Profiles
      9. 7.3.9  Starting the Motor Under Different Initial Conditions
        1. 7.3.9.1 Case 1 – Motor is Stationary
        2. 7.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 7.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 7.3.10 Motor Start Sequence (MSS)
        1. 7.3.10.1 Initial Speed Detect (ISD)
        2. 7.3.10.2 Motor Resynchronization
        3. 7.3.10.3 Reverse Drive
          1. 7.3.10.3.1 Reverse Drive Tuning
        4. 7.3.10.4 Motor Start-up
          1. 7.3.10.4.1 Align
          2. 7.3.10.4.2 Double Align
          3. 7.3.10.4.3 Initial Position Detection (IPD)
            1. 7.3.10.4.3.1 IPD Operation
            2. 7.3.10.4.3.2 IPD Release Mode
            3. 7.3.10.4.3.3 IPD Advance Angle
          4. 7.3.10.4.4 Slow First Cycle Startup
          5. 7.3.10.4.5 Open loop
          6. 7.3.10.4.6 Transition from Open to Closed Loop
      11. 7.3.11 Closed Loop Operation
        1. 7.3.11.1 Closed Loop Acceleration/Deceleration Slew Rate
        2. 7.3.11.2 Speed PI Control
        3. 7.3.11.3 Current PI Control
        4. 7.3.11.4 Overmodulation
      12. 7.3.12 Motor Parameters
        1. 7.3.12.1 Motor Resistance
        2. 7.3.12.2 Motor Inductance
        3. 7.3.12.3 Motor Back-EMF constant
      13. 7.3.13 Motor Parameter Extraction Tool (MPET)
      14. 7.3.14 Anti-Voltage Surge (AVS)
      15. 7.3.15 Output PWM Switching Frequency
      16. 7.3.16 Active Braking
      17. 7.3.17 PWM Modulation Schemes
      18. 7.3.18 Dead Time Compensation
      19. 7.3.19 Motor Stop Options
        1. 7.3.19.1 Coast (Hi-Z) Mode
        2. 7.3.19.2 Recirculation Mode
        3. 7.3.19.3 Low-Side Braking
        4. 7.3.19.4 High-Side Braking
        5. 7.3.19.5 Active Spin-Down
        6. 7.3.19.6 Align Braking
      20. 7.3.20 FG Configuration
        1. 7.3.20.1 FG Output Frequency
        2. 7.3.20.2 FG Open-Loop and Lock Behavior
      21. 7.3.21 DC Bus Current Limit
      22. 7.3.22 Protections
        1. 7.3.22.1  VM Supply Undervoltage Lockout
        2. 7.3.22.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 7.3.22.3  BUCK Undervoltage Lockout (BUCK_UV)
        4. 7.3.22.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 7.3.22.5  Overvoltage Protection (OVP)
        6. 7.3.22.6  Overcurrent Protection (OCP)
          1. 7.3.22.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 7.3.22.6.2 OCP Automatic Retry (OCP_MODE = 01b)
          3. 7.3.22.6.3 OCP Report Only (OCP_MODE = 10b)
          4. 7.3.22.6.4 OCP Disabled (OCP_MODE = 11b)
        7. 7.3.22.7  Buck Overcurrent Protection
        8. 7.3.22.8  Hardware Lock Detection Current Limit (HW_LOCK_ILIMIT)
          1. 7.3.22.8.1 HW_LOCK_ILIMIT Latched Shutdown (HW_LOCK_ILIMIT_MODE = 00xxb)
          2. 7.3.22.8.2 HW_LOCK_ILIMIT Automatic recovery (HW_LOCK_ILIMIT_MODE = 01xxb)
          3. 7.3.22.8.3 HW_LOCK_ILIMIT Report Only (HW_LOCK_ILIMIT_MODE = 1000b)
          4. 7.3.22.8.4 HW_LOCK_ILIMIT Disabled (HW_LOCK_ILIMIT_MODE= 1xx1b)
        9. 7.3.22.9  Thermal Warning (OTW)
        10. 7.3.22.10 Thermal Shutdown (TSD)
        11. 7.3.22.11 Motor Lock (MTR_LCK)
          1. 7.3.22.11.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 7.3.22.11.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 7.3.22.11.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 7.3.22.11.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        12. 7.3.22.12 Motor Lock Detection
          1. 7.3.22.12.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 7.3.22.12.2 Lock 2: Abnormal BEMF (ABN_BEMF)
          3. 7.3.22.12.3 Lock3: No-Motor Fault (NO_MTR)
        13. 7.3.22.13 MPET Faults
        14. 7.3.22.14 IPD Faults
    4. 7.4 Device Functional Modes
      1. 7.4.1 Functional Modes
        1. 7.4.1.1 Sleep Mode
        2. 7.4.1.2 Standby Mode
        3. 7.4.1.3 Fault Reset (CLR_FLT)
    5. 7.5 External Interface
      1. 7.5.1 DRVOFF Functionality
      2. 7.5.2 SOX Output
      3. 7.5.3 Oscillator Source
        1. 7.5.3.1 External Clock Source
      4. 7.5.4 External Watchdog
    6. 7.6 EEPROM access and I2C interface
      1. 7.6.1 EEPROM Access
        1. 7.6.1.1 EEPROM Write
        2. 7.6.1.2 EEPROM Read
      2. 7.6.2 I2C Serial Interface
        1. 7.6.2.1 I2C Data Word
        2. 7.6.2.2 I2C Write Operation
        3. 7.6.2.3 I2C Read Operation
        4. 7.6.2.4 Examples of MCF8316A I2C Communication Protocol Packets
        5. 7.6.2.5 Internal Buffers
        6. 7.6.2.6 CRC Byte Calculation
    7. 7.7 EEPROM (Non-Volatile) Register Map
      1. 7.7.1 Algorithm_Configuration Registers
      2. 7.7.2 Fault_Configuration Registers
      3. 7.7.3 Hardware_Configuration Registers
      4. 7.7.4 Internal_Algorithm_Configuration Registers
    8. 7.8 RAM (Volatile) Register Map
      1. 7.8.1 Fault_Status Registers
      2. 7.8.2 System_Status Registers
      3. 7.8.3 Device_Control Registers
      4. 7.8.4 Algorithm_Control Registers
      5. 7.8.5 Algorithm_Variables Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Application Curves
        1. 8.2.1.1 Motor startup
        2. 8.2.1.2 MPET
        3. 8.2.1.3 Dead time compensation
        4. 8.2.1.4 Auto handoff
        5. 8.2.1.5 Motor stop – recirculation mode
        6. 8.2.1.6 Anti voltage surge (AVS)
  10. 9 Power Supply Recommendations
    1. 9.1 Bulk Capacitance
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
      1. 10.3.1 Power Dissipation
  12. 11Device and Documentation Support
    1. 11.1 Support Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.22 Protections

The MCF8316A is protected from a host of fault events including motor lock, VM undervoltage, AVDD undervoltage, buck undervoltage, charge pump undervoltage, overtemperature and overcurrent events. Table 7-5 summarizes the response, recovery modes, power stage status, reporting mechanism for different faults.

Table 7-5 Fault Action and Response
FAULT CONDITION CONFIGURATION REPORT H-BRIDGE LOGIC RECOVERY
VM undervoltage
(NPOR)		 VVM < VUVLO — — Hi-Z Disabled Automatic:
VVM > VUVLO
AVDD undervoltage
(NPOR)		 VAVDD < VAVDD_UV — — Hi-Z Disabled Automatic:
VAVDD > VAVDD_UV
Buck undervoltage
(BUCK_UV)		 VFB_BK < VBK_UV — — Hi-Z Disabled Automatic:
VFB_BK > VBK_UV
Charge pump undervoltage
(VCP_UV)		 VCP < VCPUV — nFAULT and GATE_DRIVER_FAULT_STATUS register Hi-Z Active Automatic:
VVCP > VCPUV
OverVoltage Protection
(OVP)		 VVM > VOVP OVP_EN = 0b None Active Active No action (OVP Disabled)
OVP_EN = 1b nFAULT and GATE_DRIVER_FAULT_STATUS register Hi-Z Active Automatic:
VVM < VOVP
Overcurrent Protection
(OCP)		 IPHASE > IOCP OCP_MODE = 00b nFAULT and GATE_DRIVER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
OCP_MODE = 01b nFAULT and GATE_DRIVER_FAULT_STATUS register Hi-Z Active Retry:
tRETRY
OCP_MODE = 10b nFAULT and GATE_DRIVER_FAULT_STATUS register Active Active No action
OCP_MODE = 11b None Active Active No action
Buck Overcurrent Protection
(BUCK_OCP)		 IBK > IBK_OCP — — Hi-Z Disabled Retry:
tRETRY
Motor Lock
(MTR_LCK )		 Motor lock: Abnormal Speed; No Motor Lock; Abnormal BEMF MTR_LCK_MODE = 0000b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
MTR_LCK_MODE = 0001b nFAULT and CONTROLLER_FAULT_STATUS register Recirculation Active Latched:
CLR_FLT
MTR_LCK_MODE = 0010b nFAULT and CONTROLLER_FAULT_STATUS register High side brake Active Latched:
CLR_FLT
MTR_LCK_MODE = 0011b nFAULT and CONTROLLER_FAULT_STATUS register Low side brake Active Latched:
CLR_FLT
MTR_LCK_MODE = 0100b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Retry:
tLCK_RETRY
MTR_LCK_MODE = 0101b nFAULT and CONTROLLER_FAULT_STATUS register Recirculation Active Retry:
tLCK_RETRY
MTR_LCK_MODE = 0110b nFAULT and CONTROLLER_FAULT_STATUS register High side brake Active Retry:
tLCK_RETRY
MTR_LCK_MODE = 0111b nFAULT and CONTROLLER_FAULT_STATUS register Low side brake Active Retry:
tLCK_RETRY
MTR_LCK_MODE = 1000b nFAULT and CONTROLLER_FAULT_STATUS register Active Active No action
MTR_LCK_MODE = 1xx1b None Active Active No action
Hardware Lock-Detection Current Limit
(HW_LOCK_ILIMIT)
VSOX > HW_LOCK_ILIMIT HW_LOCK_ILIMIT_MODE = 0000b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
HW_LOCK_ILIMIT_MODE = 0001b nFAULT and CONTROLLER_FAULT_STATUS register Recirculation Active Latched:
CLR_FLT
HW_LOCK_ILIMIT_MODE = 0010b nFAULT and CONTROLLER_FAULT_STATUS register High-side brake Active Latched:
CLR_FLT
HW_LOCK_ILIMIT_MODE = 0011b nFAULT and CONTROLLER_FAULT_STATUS register Low-side brake Active Latched:
CLR_FLT
HW_LOCK_ILIMIT_MODE = 0100b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Retry:
tLCK_RETRY
HW_LOCK_ILIMIT_MODE = 0101b nFAULT and CONTROLLER_FAULT_STATUS register Recirculation Active Retry:
tLCK_RETRY
HW_LOCK_ILIMIT_MODE = 0110b nFAULT and CONTROLLER_FAULT_STATUS register High-side brake Active Retry:
tLCK_RETRY
HW_LOCK_ILIMIT_MODE = 0111b nFAULT and CONTROLLER_FAULT_STATUS register Low-side brake Active Retry:
tLCK_RETRY
HW_LOCK_ILIMIT_MODE= 1000b nFAULT and CONTROLLER_FAULT_STATUS register Active Active No action
HW_LOCK_ILIMIT_MODE = 1xx1b None Active Active No action
Software Lock-Detection Current Limit
(LOCK_ILIMIT)
VSOX > LOCK_ILIMIT LOCK_ILIMIT_MODE = 0000b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
LOCK_ILIMIT_MODE = 0001b nFAULT and CONTROLLER_FAULT_STATUS register Recirculation Active Latched:
CLR_FLT
LOCK_ILIMIT_MODE = 0010b nFAULT and CONTROLLER_FAULT_STATUS register High-side brake Active Latched:
CLR_FLT
LOCK_ILIMIT_MODE = 0011b nFAULT and CONTROLLER_FAULT_STATUS register Low-side brake Active Latched:
CLR_FLT
LOCK_ILIMIT_MODE = 0100b nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Retry:
tLCK_RETRY
LOCK_ILIMIT_MODE = 0101b nFAULT and CONTROLLER_FAULT_STATUS register Recirculation Active Retry:
tLCK_RETRY
LOCK_ILIMIT_MODE = 0110b nFAULT and CONTROLLER_FAULT_STATUS register High-side brake Active Retry:
tLCK_RETRY
LOCK_ILIMIT_MODE = 0111b nFAULT and CONTROLLER_FAULT_STATUS register Low-side brake Active Retry:
tLCK_RETRY
LOCK_ILIMIT_MODE= 1000b nFAULT and CONTROLLER_FAULT_STATUS register Active Active No action
LOCK_ILIMIT_MODE = 1xx1b None Active Active No action
IPD Timeout Fault
(IPD_T1_FAULT and IPD_T2_FAULT)		 IPD TIME > 500ms (approx), during IPD current ramp up or ramp down IPD_TIMEOUT_FAULT_EN = 1 nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
IP Frequency Fault
(IPD_FREQ_FAULT)		 IPD pulse before the current decay in previous IPD IPD_TIMEOUT_FAULT_EN = 1 nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
MPET IPD Fault
(MPET_IPD_FAULT)		 Same as IPD Timeout Fault. MPET_CMD = 1 or
MPET_R or MPET_L = 1		 nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
MPET Back-EMF Fault
(MPET_BEMF_FAULT)		 Motor Back EMF < STAT_DETECT_THR MPET_CMD = 1 or
MPET_KE = 1		 nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Latched:
CLR_FLT
Thermal warning
(OTW)		 TJ > TOTW OTW_REP = 0b None Active Active No action
OTW_REP = 1b nFAULT and CONTROLLER_FAULT_STATUS register Active Active Automatic:
TJ < TOTW – TOTW_HYS
CLR_FLT
Thermal shutdown
(TSD)		 TJ > TTSD — nFAULT and CONTROLLER_FAULT_STATUS register Hi-Z Active Automatic:
TJ < TTSD – TTSD_HYS
CLR_FLT