SLAS590P March   2009  – September 2020 MSP430F5513 , MSP430F5514 , MSP430F5515 , MSP430F5517 , MSP430F5519 , MSP430F5521 , MSP430F5522 , MSP430F5524 , MSP430F5525 , MSP430F5526 , MSP430F5527 , MSP430F5528 , MSP430F5529

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagrams
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Signal Descriptions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 8.6  Thermal Resistance Characteristics
    7. 8.7  Schmitt-Trigger Inputs – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7, P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)
    8. 8.8  Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
    9. 8.9  Leakage Current – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)
    10. 8.10 Outputs – General-Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7, P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
    11. 8.11 Outputs – General-Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7, P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
    12. 8.12 Output Frequency – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7, P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
    13. 8.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 8.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    15. 8.15 Crystal Oscillator, XT1, Low-Frequency Mode
    16. 8.16 Crystal Oscillator, XT2
    17. 8.17 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    18. 8.18 Internal Reference, Low-Frequency Oscillator (REFO)
    19. 8.19 DCO Frequency
    20. 8.20 PMM, Brownout Reset (BOR)
    21. 8.21 PMM, Core Voltage
    22. 8.22 PMM, SVS High Side
    23. 8.23 PMM, SVM High Side
    24. 8.24 PMM, SVS Low Side
    25. 8.25 PMM, SVM Low Side
    26. 8.26 Wake-up Times From Low-Power Modes and Reset
    27. 8.27 Timer_A
    28. 8.28 Timer_B
    29. 8.29 USCI (UART Mode) Clock Frequency
    30. 8.30 USCI (UART Mode)
    31. 8.31 USCI (SPI Master Mode) Clock Frequency
    32. 8.32 USCI (SPI Master Mode)
    33. 8.33 USCI (SPI Slave Mode)
    34. 8.34 USCI (I2C Mode)
    35. 8.35 12-Bit ADC, Power Supply and Input Range Conditions
    36. 8.36 12-Bit ADC, Timing Parameters
    37. 8.37 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
    38. 8.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
    39. 8.39 12-Bit ADC, Temperature Sensor and Built-In VMID
    40. 8.40 REF, External Reference
    41. 8.41 REF, Built-In Reference
    42. 8.42 Comparator_B
    43. 8.43 Ports PU.0 and PU.1
    44. 8.44 USB Output Ports DP and DM
    45. 8.45 USB Input Ports DP and DM
    46. 8.46 USB-PWR (USB Power System)
    47. 8.47 USB-PLL (USB Phase-Locked Loop)
    48. 8.48 Flash Memory
    49. 8.49 JTAG and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  CPU
    2. 9.2  Operating Modes
    3. 9.3  Interrupt Vector Addresses
    4. 9.4  Memory Organization
    5. 9.5  Bootloader (BSL)
      1. 9.5.1 USB BSL
      2. 9.5.2 UART BSL
    6. 9.6  JTAG Operation
      1. 9.6.1 JTAG Standard Interface
      2. 9.6.2 Spy-Bi-Wire Interface
    7. 9.7  Flash Memory
    8. 9.8  RAM
    9. 9.9  Peripherals
      1. 9.9.1  Digital I/O
      2. 9.9.2  Port Mapping Controller
      3. 9.9.3  Oscillator and System Clock
      4. 9.9.4  Power-Management Module (PMM)
      5. 9.9.5  Hardware Multiplier
      6. 9.9.6  Real-Time Clock (RTC_A)
      7. 9.9.7  Watchdog Timer (WDT_A)
      8. 9.9.8  System Module (SYS)
      9. 9.9.9  DMA Controller
      10. 9.9.10 Universal Serial Communication Interface (USCI)
      11. 9.9.11 TA0
      12. 9.9.12 TA1
      13. 9.9.13 TA2
      14. 9.9.14 TB0
      15. 9.9.15 Comparator_B
      16. 9.9.16 ADC12_A
      17. 9.9.17 CRC16
      18. 9.9.18 Voltage Reference (REF) Module
      19. 9.9.19 Universal Serial Bus (USB)
      20. 9.9.20 Embedded Emulation Module (EEM)
      21. 9.9.21 Peripheral File Map
    10. 9.10 Input/Output Diagrams
      1. 9.10.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 9.10.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 9.10.3  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 9.10.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 9.10.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 9.10.6  Port P5 (P5.2 and P5.3) Input/Output With Schmitt Trigger
      7. 9.10.7  Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger
      8. 9.10.8  Port P5 (P5.6 and P5.7) Input/Output With Schmitt Trigger
      9. 9.10.9  Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      10. 9.10.10 Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
      11. 9.10.11 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      12. 9.10.12 Port P8 (P8.0 to P8.2) Input/Output With Schmitt Trigger
      13. 9.10.13 Port PU (PU.0/DP, PU.1/DM, PUR) USB Ports
      14. 9.10.14 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      15. 9.10.15 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    11. 9.11 Device Descriptors (TLV)
  10. 10Device and Documentation Support
    1. 10.1  Getting Started and Next Steps
    2. 10.2  Device Nomenclature
    3. 10.3  Tools and Software
    4. 10.4  Documentation Support
    5. 10.5  Related Links
    6. 10.6  Support Resources
    7. 10.7  Trademarks
    8. 10.8  Electrostatic Discharge Caution
    9. 10.9  Export Control Notice
    10. 10.10 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.9.11 TA0

TA0 is a 16-bit timer and counter (Timer_A type) with five capture/compare registers. TA0 can support multiple capture/compare registers, PWM outputs, and interval timing (see Table 9-11). TA0 also has extensive interrupt capabilities. Interrupts can be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 9-11 TA0 Signal Connections
INPUT PIN NUMBERDEVICE INPUT SIGNALMODULE INPUT SIGNALMODULE BLOCKMODULE OUTPUT SIGNALDEVICE OUTPUT SIGNALOUTPUT PIN NUMBER
RGC, YFF, ZXH, ZQEPNRGC, YFF, ZXH, ZQEPN
18, B7, H2 - P1.021 - P1.0TA0CLKTACLKTimerNANA
ACLK (internal)ACLK
SMCLK (internal)SMCLK
18, B7, H2 - P1.021 - P1.0TA0CLKTACLK
19, B6, H3 - P1.122 - P1.1TA0.0CCI0ACCR0TA0TA0.019, B6, H3 - P1.122 - P1.1
DVSSCCI0B
DVSSGND
DVCCVCC
20, C6, J3 - P1.223 - P1.2TA0.1CCI1ACCR1TA1TA0.120, C6, J3 - P1.223 - P1.2
CBOUT (internal)CCI1BADC12 (internal)(1)
ADC12SHSx = {1}		ADC12 (internal)(1)
ADC12SHSx = {1}
DVSSGND
DVCCVCC
21, C8, G4 - P1.324 - P1.3TA0.2CCI2ACCR2TA2TA0.221, C8, G4 - P1.324 - P1.3
ACLK (internal)CCI2B
DVSSGND
DVCCVCC
22, C7, H4 - P1.425 - P1.4TA0.3CCI3ACCR3TA3TA0.322, C7, H4 - P1.425 - P1.4
DVSSCCI3B
DVSSGND
DVCCVCC
23, D6, J4 - P1.526 - P1.5TA0.4CCI4ACCR4TA4TA0.423, D6, J4 - P1.526 - P1.5
DVSSCCI4B
DVSSGND
DVCCVCC
(1) Only on devices with ADC.