SLASEE5D January   2018  – January 2021 MSP430FR2422

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Pin Attributes
    3. 7.3 Signal Descriptions
    4. 7.4 Pin Multiplexing
    5. 7.5 Buffer Types
    6. 7.6 Connection of Unused Pins
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Active Mode Supply Current Per MHz
    6. 8.6  Low-Power Mode (LPM0) Supply Currents Into VCC Excluding External Current
    7. 8.7  Low-Power Mode (LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 8.8  Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
    9. 8.9  Typical Characteristics - Low-Power Mode Supply Currents
    10. 8.10 Typical Characteristics – Current Consumption Per Module
    11. 8.11 Thermal Resistance Characteristics
    12. 8.12 Timing and Switching Characteristics
      1. 8.12.1  Power Supply Sequencing
        1. 8.12.1.1 PMM, SVS and BOR
      2. 8.12.2  Reset Timing
        1. 8.12.2.1 Wake-up Times From Low-Power Modes and Reset
      3. 8.12.3  Clock Specifications
        1. 8.12.3.1 XT1 Crystal Oscillator (Low Frequency)
        2. 8.12.3.2 DCO FLL, Frequency
        3. 8.12.3.3 DCO Frequency
        4. 8.12.3.4 REFO
        5. 8.12.3.5 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        6. 8.12.3.6 Module Oscillator (MODOSC)
      4. 8.12.4  Digital I/Os
        1. 8.12.4.1 Digital Inputs
        2. 8.12.4.2 Digital Outputs
        3. 8.12.4.3 Typical Characteristics – Outputs at 3 V and 2 V
      5. 8.12.5  VREF+ Built-in Reference
        1. 8.12.5.1 VREF+
      6. 8.12.6  Timer_A
        1. 8.12.6.1 Timer_A
      7. 8.12.7  eUSCI
        1. 8.12.7.1 eUSCI (UART Mode) Clock Frequency
        2. 8.12.7.2 eUSCI (UART Mode)
        3. 8.12.7.3 eUSCI (SPI Master Mode) Clock Frequency
        4. 8.12.7.4 eUSCI (SPI Master Mode)
        5. 8.12.7.5 eUSCI (SPI Slave Mode)
        6. 8.12.7.6 eUSCI (I2C Mode)
      8. 8.12.8  ADC
        1. 8.12.8.1 ADC, Power Supply and Input Range Conditions
        2. 8.12.8.2 ADC, 10-Bit Timing Parameters
        3. 8.12.8.3 ADC, 10-Bit Linearity Parameters
      9. 8.12.9  FRAM
        1. 8.12.9.1 FRAM
      10. 8.12.10 Debug and Emulation
        1. 8.12.10.1 JTAG, Spy-Bi-Wire Interface
        2. 8.12.10.2 JTAG, 4-Wire Interface
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Operating Modes
    4. 9.4  Interrupt Vector Addresses
    5. 9.5  Bootloader (BSL)
    6. 9.6  JTAG Standard Interface
    7. 9.7  Spy-Bi-Wire Interface (SBW)
    8. 9.8  FRAM
    9. 9.9  Memory Protection
    10. 9.10 Peripherals
      1. 9.10.1  Power-Management Module (PMM)
      2. 9.10.2  Clock System (CS) and Clock Distribution
      3. 9.10.3  General-Purpose Input/Output Port (I/O)
      4. 9.10.4  Watchdog Timer (WDT)
      5. 9.10.5  System (SYS) Module
      6. 9.10.6  Cyclic Redundancy Check (CRC)
      7. 9.10.7  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
      8. 9.10.8  Timers (Timer0_A3, Timer1_A3)
      9. 9.10.9  Hardware Multiplier (MPY)
      10. 9.10.10 Backup Memory (BAKMEM)
      11. 9.10.11 Real-Time Clock (RTC)
      12. 9.10.12 10-Bit Analog-to-Digital Converter (ADC)
      13. 9.10.13 Embedded Emulation Module (EEM)
    11. 9.11 Input/Output Diagrams
      1. 9.11.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 9.11.2 Port P2 (P2.0 to P2.6) Input/Output With Schmitt Trigger
    12. 9.12 Device Descriptors
    13. 9.13 Memory
      1. 9.13.1 Memory Organization
      2. 9.13.2 Peripheral File Map
    14. 9.14 Identification
      1. 9.14.1 Revision Identification
      2. 9.14.2 Device Identification
      3. 9.14.3 JTAG Identification
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 10.1.2 External Oscillator
      3. 10.1.3 JTAG
      4. 10.1.4 Reset
      5. 10.1.5 Unused Pins
      6. 10.1.6 General Layout Recommendations
      7. 10.1.7 Do's and Don'ts
    2. 10.2 Peripheral- and Interface-Specific Design Information
      1. 10.2.1 ADC Peripheral
        1. 10.2.1.1 Partial Schematic
        2. 10.2.1.2 Design Requirements
        3. 10.2.1.3 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Getting Started and Next Steps
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Export Control Notice
    9. 11.9 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|16
  • RHL|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.11.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger

Figure 9-3 shows the port diagram. Table 9-15 summarizes the selection of pin function.

GUID-BC3540FE-30E5-4873-A029-68AD62B9B805-low.gifFigure 9-3 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
Table 9-15 Port P1 (P1.0 to P1.7) Pin Functions
PIN NAME (P1.x)xFUNCTIONCONTROL BITS AND SIGNALS(2)
P1DIR.xP1SELxANALOG FUNCTION(1)JTAG
P1.0/UCB0STE/A0/ Veref+0P1.0 (I/O)I: 0; O: 10000
UCB0STEX0100
A0,Veref+XADCPCTLx = 1 (x = 0) from SYSCFG2N/A
P1.1/UCB0CLK/ACLK/ A1/VREF+1P1.1 (I/O)I: 0; O: 10000
UCB0CLKX0100
ACLK11000
A1,VREF+XADCPCTLx = 1 (x = 1) from SYSCFG2N/A
P1.2/UCB0SIMO/ UCB0SDA/SMCLK/A2/ Veref-2P1.2 (I/O)I: 0; O: 10000
UCB0SIMO/UCB0SDAX0100
SMCLK11000
A2, Veref-XADCPCTLx = 1 (x = 2) from SYSCFG2N/A
P1.3/UCB0SOMI/ UCB0SCL/MCLK/A33P1.3 (I/O)I: 0; O: 10000
UCB0SOMI/UCB0SCLX0100
MCLK11000
A3XADCPCTLx = 1 (x = 3) from SYSCFG2N/A
P1.4/UCA0TXD/ UCA0SIMO/TA0.1/TCK4P1.4 (I/O)I: 0; O: 1000Disabled
UCA0TXD/UCA0SIMOX010Disabled
TA0.CCI1A0100Disabled
TA0.11
JTAG TCKXXXTCK
P1.5/UCA0RXD/ UCA0SOMI/TA0.2/TMS5P1.5 (I/O)I: 0; O: 1000Disabled
UCA0RXD/UCA0SOMIX010Disabled
TA0.CCI2A0100Disabled
TA0.21
JTAG TMSXXXTMS
P1.6/UCA0CLK/ TA0CLK/TDI/TCLK6P1.6 (I/O)I: 0; O: 1000Disabled
UCA0CLKX010Disabled
TA0CLK0100Disabled
JTAG TDI/TCLKXXXTDI/TCLK
P1.7/UCA0STE/TDO7P1.7 (I/O)I: 0; O: 1000Disabled
UCA0STEX010Disabled
JTAG TDOXXXTDO
(1) Setting the bits disables both the output driver and input Schmitt trigger to prevent leakage when analog signals are applied.
(2) X = don't care