SLASEV3A March   2020  – December 2020 MSP430FR6005 , MSP430FR6007

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Pin Attributes
    3. 7.3 Signal Descriptions
    4. 7.4 Pin Multiplexing
    5. 7.5 Buffer Type
    6. 7.6 Connection of Unused Pins
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Typical Characteristics, Active Mode Supply Currents
    6. 8.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 8.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 8.8  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    9. 8.9  Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
    10. 8.10 Typical Characteristics, Low-Power Mode Supply Currents
    11. 8.11 Current Consumption per Module
    12. 8.12 Thermal Resistance Characteristics for 100-Pin LQFP (PZ) Package
    13. 8.13 Timing and Switching Characteristics
      1. 8.13.1  Power Supply Sequencing
        1. 8.13.1.1 Brownout and Device Reset Power Ramp Requirements
        2. 8.13.1.2 SVS
      2. 8.13.2  Reset Timing
        1. 8.13.2.1 Reset Input
      3. 8.13.3  Clock Specifications
        1. 8.13.3.1 Low-Frequency Crystal Oscillator, LFXT
        2. 8.13.3.2 High-Frequency Crystal Oscillator, HFXT
        3. 8.13.3.3 DCO
        4. 8.13.3.4 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. 8.13.3.5 Module Oscillator (MODOSC)
      4. 8.13.4  Wake-up Characteristics
        1. 8.13.4.1 Wake-up Times From Low-Power Modes and Reset
        2. 8.13.4.2 Typical Wake-up Charges
        3. 8.13.4.3 Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 8.13.5  Digital I/Os
        1. 8.13.5.1 Digital Inputs
        2. 8.13.5.2 Digital Outputs
        3. 8.13.5.3 Typical Characteristics, Digital Outputs
      6. 8.13.6  LEA
        1. 8.13.6.1 Low-Energy Accelerator (LEA) Performance
      7. 8.13.7  Timer_A and Timer_B
        1. 8.13.7.1 Timer_A
        2. 8.13.7.2 Timer_B
      8. 8.13.8  eUSCI
        1. 8.13.8.1 eUSCI (UART Mode) Clock Frequency
        2. 8.13.8.2 eUSCI (UART Mode) Switching Characteristics
        3. 8.13.8.3 eUSCI (SPI Master Mode) Clock Frequency
        4. 8.13.8.4 eUSCI (SPI Master Mode) Switching Characteristics
        5. 8.13.8.5 eUSCI (SPI Master Mode) Timing Diagrams
        6. 8.13.8.6 eUSCI (SPI Slave Mode) Switching Characteristics
        7. 8.13.8.7 eUSCI (SPI Slave Mode) Timing Diagrams
        8. 8.13.8.8 eUSCI (I2C Mode) Switching Characteristics
        9. 8.13.8.9 eUSCI (I2C Mode) Timing Diagram
      9. 8.13.9  Segment LCD Controller
        1. 8.13.9.1 LCD_C Recommended Operating Conditions
        2. 8.13.9.2 LCD_C Electrical Characteristics
      10. 8.13.10 ADC12_B
        1. 8.13.10.1 12-Bit ADC, Power Supply and Input Range Conditions
        2. 8.13.10.2 12-Bit ADC, Timing Parameters
        3. 8.13.10.3 12-Bit ADC, Linearity Parameters
        4. 8.13.10.4 12-Bit ADC, Dynamic Performance With External Reference
        5. 8.13.10.5 12-Bit ADC, Dynamic Performance With Internal Reference
        6. 8.13.10.6 12-Bit ADC, Temperature Sensor and Built-In V1/2
        7. 8.13.10.7 12-Bit ADC, External Reference
      11. 8.13.11 Reference
        1. 8.13.11.1 REF, Built-In Reference
      12. 8.13.12 Comparator
        1. 8.13.12.1 Comparator_E
      13. 8.13.13 FRAM
        1. 8.13.13.1 FRAM
      14. 8.13.14 USS
        1. 8.13.14.1 USS Recommended Operating Conditions
        2. 8.13.14.2 USS LDO
        3. 8.13.14.3 USSXTAL
        4. 8.13.14.4 USS HSPLL
        5. 8.13.14.5 USS SDHS
        6. 8.13.14.6 USS PHY Output Stage
        7. 8.13.14.7 USS PHY Input Stage, Multiplexer
        8. 8.13.14.8 USS PGA
        9. 8.13.14.9 USS Bias Voltage Generator
      15. 8.13.15 Emulation and Debug
        1. 8.13.15.1 JTAG and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Ultrasonic Sensing Solution (USS) Module
    4. 9.4  Low-Energy Accelerator (LEA) for Signal Processing
    5. 9.5  Operating Modes
      1. 9.5.1 Peripherals in Low-Power Modes
      2. 9.5.2 Idle Currents of Peripherals in LPM3 and LPM4
    6. 9.6  Interrupt Vector Table and Signatures
    7. 9.7  Bootloader (BSL)
    8. 9.8  JTAG Operation
      1. 9.8.1 JTAG Standard Interface
      2. 9.8.2 Spy-Bi-Wire (SBW) Interface
    9. 9.9  FRAM Controller A (FRCTL_A)
    10. 9.10 RAM
    11. 9.11 Tiny RAM
    12. 9.12 Memory Protection Unit (MPU) Including IP Encapsulation
    13. 9.13 Peripherals
      1. 9.13.1  Digital I/O
      2. 9.13.2  Oscillator and Clock System (CS)
      3. 9.13.3  Power-Management Module (PMM)
      4. 9.13.4  Hardware Multiplier (MPY)
      5. 9.13.5  Real-Time Clock (RTC_C)
      6. 9.13.6  Watchdog Timer (WDT_A)
      7. 9.13.7  System Module (SYS)
      8. 9.13.8  DMA Controller
      9. 9.13.9  Enhanced Universal Serial Communication Interface (eUSCI)
      10. 9.13.10 TA0, TA1, and TA4
      11. 9.13.11 TA2 and TA3
      12. 9.13.12 TB0
      13. 9.13.13 ADC12_B
      14. 9.13.14 USS
      15. 9.13.15 Comparator_E
      16. 9.13.16 CRC16
      17. 9.13.17 CRC32
      18. 9.13.18 AES256 Accelerator
      19. 9.13.19 True Random Seed
      20. 9.13.20 Shared Reference (REF)
      21. 9.13.21 LCD_C
      22. 9.13.22 Embedded Emulation
        1. 9.13.22.1 Embedded Emulation Module (EEM) (S Version)
        2. 9.13.22.2 EnergyTrace++ Technology
    14. 9.14 Input/Output Diagrams
      1. 9.14.1  Port Function Select Registers (PySEL1 , PySEL0)
      2. 9.14.2  Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger
      3. 9.14.3  Port P1 (P1.2 to P1.7) Input/Output With Schmitt Trigger
      4. 9.14.4  Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
      5. 9.14.5  Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger
      6. 9.14.6  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      7. 9.14.7  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      8. 9.14.8  Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
      9. 9.14.9  Port P6 (P6.0) Input/Output With Schmitt Trigger
      10. 9.14.10 Port P6 (P6.1 to P6.5) Input/Output With Schmitt Trigger
      11. 9.14.11 Port P6 (P6.6 and P6.7) Input/Output With Schmitt Trigger
      12. 9.14.12 Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
      13. 9.14.13 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      14. 9.14.14 Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger
      15. 9.14.15 Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger
      16. 9.14.16 Port P9 (P9.0 to P9.3) Input/Output With Schmitt Trigger
      17. 9.14.17 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
      18. 9.14.18 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
      19. 9.14.19 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
    15. 9.15 Device Descriptors (TLV)
    16. 9.16 Memory Map
      1. 9.16.1 Peripheral File Map
    17. 9.17 Identification
      1. 9.17.1 Revision Identification
      2. 9.17.2 Device Identification
      3. 9.17.3 JTAG Identification
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1  Power Supply Decoupling and Bulk Capacitors
      2. 10.1.2  External Oscillator (HFXT and LFXT)
      3. 10.1.3  USS Oscillator (USSXT)
      4. 10.1.4  Transducer Connection to the USS Module
      5. 10.1.5  Charge Pump Control of Input Multiplexer
      6. 10.1.6  JTAG
      7. 10.1.7  Reset
      8. 10.1.8  Unused Pins
      9. 10.1.9  General Layout Recommendations
      10. 10.1.10 Do's and Don'ts
    2. 10.2 Peripheral- and Interface-Specific Design Information
      1. 10.2.1 ADC12_B Peripheral
        1. 10.2.1.1 Partial Schematic
        2. 10.2.1.2 Design Requirements
        3. 10.2.1.3 Detailed Design Procedure
        4. 10.2.1.4 Layout Guidelines
      2. 10.2.2 LCD_C Peripheral
        1. 10.2.2.1 Partial Schematic
        2. 10.2.2.2 Design Requirements
        3. 10.2.2.3 Detailed Design Procedure
        4. 10.2.2.4 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Getting Started and Next Steps
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Export Control Notice
    9. 11.9 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.6 Interrupt Vector Table and Signatures

The interrupt vectors, the power-up start address, and signatures are in the address range 0FFFFh to 0FF80h. Figure 9-2 summarizes the content of this address range.

GUID-62093FF7-C479-47CC-9451-9D619DDBF704-low.gif Figure 9-2 Interrupt Vectors, Signatures and Passwords

The power-up start address or reset vector is at 0FFFFh to 0FFFEh. It contains the 16-bit address pointing to the start address of the application program.

The interrupt vectors start at 0FFFDh and extend to lower addresses. Each vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 9-4 shows the device-specific interrupt vector locations.

The vectors programmed into the address range from 0FFFFh to 0FFE0h are used as BSL password (if enabled by the corresponding signature).

The signatures start at 0FF80h and extend to higher addresses. Signatures are evaluated during device start-up. Table 9-5 shows the device-specific signature locations.

A JTAG password can be programmed starting from address 0FF88h and extending to higher addresses. The password can extend into the interrupt vector locations using the interrupt vector addresses as additional bits for the password. The length of the JTAG password depends on the JTAG signature.

See the System Resets, Interrupts, and Operating Modes, System Control Module (SYS) chapter in the MSP430FR58xx, MSP430FR59xx, and MSP430FR6xx Family User's Guide for details.

Table 9-4 Interrupt Sources, Flags, and Vectors
INTERRUPT SOURCE INTERRUPT FLAG INTERRUPT VECTOR REGISTER SYSTEM INTERRUPT WORD ADDRESS PRIORITY
System Reset SYSRSTIV(1) (2) Reset 0FFFEh Highest
Power up, brownout, supply supervisor SVSHIFG
External reset RST PMMRSTIFG
Watchdog time-out (watchdog mode) WDTIFG
WDT, FRCTL MPU, CS, PMM password violation WDTPW, FRCTLPW, MPUPW, CSPW, PMMPW
FRAM uncorrectable bit error detection UBDIFG
MPU segment violation MPUSEG1IFG, MPUSEG2IFG, MPUSEG3IFG
Software POR, BOR PMMPORIFG, PMMBORIFG
System NMI SYSSNIV(1) (3) (Non)maskable 0FFFCh
Vacant memory access VMAIFG
JTAG mailbox JMBINIFG, JMBOUTIFG
FRAM access time error ACCTEIFG
FRAM write protection error WPIFG
FRAM bit error detection CBDIFG, UBDIFG
MPU segment violation MPUSEG1IFG, MPUSEG2IFG, MPUSEG3IFG
User NMI SYSUNIV(1) (3) (Non)maskable 0FFFAh
External NMI NMIIFG
Oscillator fault OFIFG
LEA RAM access conflict DACCESSIFG
Comparator_E CEIFG, CEIIFG CEIV(1) Maskable 0FFF8h
TB0 TB0CCR0.CCIFG Maskable 0FFF6h
TB0 TB0CCR1.CCIFG to TB0CCR6.CCIFG,
TB0CTL.TBIFG		 TB0IV(1) Maskable 0FFF4h
Watchdog timer (interval timer mode) WDTIFG Maskable 0FFF2h
eUSCI_A0 receive or transmit UCA0IFG: UCRXIFG, UCTXIFG (SPI mode)
UCA0IFG: UCSTTIFG, UCTXCPTIFG, UCRXIFG, UCTXIFG (UART mode)		 UCA0IV(1) Maskable 0FFF0h
eUSCI_B0 receive or transmit UCB0IFG: UCRXIFG, UCTXIFG (SPI mode)
UCB0IFG: UCALIFG, UCNACKIFG, UCSTTIFG, UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1, UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3, UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode)		 UCB0IV(1) Maskable 0FFEEh
ADC12_B ADC12IFG0 to ADC12IFG31
ADC12LOIFG, ADC12INIFG, ADC12HIIFG, ADC12RDYIFG, ADC21OVIFG, ADC12TOVIFG		 ADC12IV(1) (4) Maskable 0FFECh
TA0 TA0CCR0.CCIFG Maskable 0FFEAh
TA0 TA0CCR1.CCIFG, TA0CCR2.CCIFG,
TA0CTL.TAIFG		 TA0IV(1) Maskable 0FFE8h
eUSCI_A1 receive or transmit UCA1IFG: UCRXIFG, UCTXIFG (SPI mode)
UCA1IFG: UCSTTIFG, UCTXCPTIFG, UCRXIFG, UCTXIFG (UART mode)		 UCA1IV(1) Maskable 0FFE6h
DMA DMA0CTL.DMAIFG, DMA1CTL.DMAIFG, DMA2CTL.DMAIFG DMAIV(1) Maskable 0FFE4h
TA1 TA1CCR0.CCIFG Maskable 0FFE2h
TA1 TA1CCR1.CCIFG, TA1CCR2.CCIFG,
TA1CTL.TAIFG		 TA1IV(1) Maskable 0FFE0h
I/O port P1 P1IFG.0 to P1IFG.7 P1IV(1) Maskable 0FFDEh
TA2 TA2CCR0.CCIFG Maskable 0FFDCh
TA2 TA2CCR1.CCIFG
TA2CTL.TAIFG		 TA2IV(1) Maskable 0FFDAh
I/O port P2 P2IFG.0 to P2IFG.7 P2IV(1) Maskable 0FFD8h
TA3 TA3CCR0.CCIFG Maskable 0FFD6h
TA3 TA3CCR1.CCIFG
TA3CTL.TAIFG		 TA3IV(1) Maskable 0FFD4h
I/O port P3 P3IFG.0 to P3IFG.7 P3IV(1) Maskable 0FFD2h
I/O port P4 P4IFG.0 to P4IFG.7 P4IV(1) Maskable 0FFD0h
LCD_C LCD_C interrupt flags LCDCIV(1) Maskable 0FFCEh
RTC_C RTCRDYIFG, RTCTEVIFG, RTCAIFG, RT0PSIFG, RT1PSIFG, RTCOFIFG RTCIV(1) Maskable 0FFCCh
AES AESRDYIFG Maskable 0FFCAh
TA4 TA4CCR0.CCIFG Maskable 0FFC8h
TA4 TA4CCR1.CCIFG
TA4CTL.TAIFG		 TA4IV(1) Maskable 0FFC6h
I/O port P5 P5IFG.0 to P5IFG.7 P5IV(1) Maskable 0FFC4h
I/O port P6 P6IFG.0 to P6IFG.7 P6IV(1) Maskable 0FFC2h
eUSCI_A2 receive or transmit UCA2IFG: UCRXIFG, UCTXIFG (SPI mode)
UCA2IFG: UCSTTIFG, UCTXCPTIFG, UCRXIFG, UCTXIFG (UART mode)		 UCA2IV(1) Maskable 0FFC0h
eUSCI_A3 receive or transmit UCA3IFG: UCRXIFG, UCTXIFG (SPI mode)
UCA3IFG: UCSTTIFG, UCTXCPTIFG, UCRXIFG, UCTXIFG (UART mode)		 UCA3IV(1) Maskable 0FFBEh
eUSCI_B1 receive or transmit UCB1IFG: UCRXIFG, UCTXIFG (SPI mode)
UCB1IFG: UCALIFG, UCNACKIFG, UCSTTIFG, UCSTPIFG, UCRXIFG0, UCTXIFG0, UCRXIFG1, UCTXIFG1, UCRXIFG2, UCTXIFG2, UCRXIFG3, UCTXIFG3, UCCNTIFG, UCBIT9IFG (I2C mode)		 UCB1IV(1) Maskable 0FFBCh
I/O port P7 P7IFG.0 to P7IFG.7 P7IV(1) Maskable 0FFBAh
I/O port P8 P8IFG.0 to P8IFG.7 P8IV(1) Maskable 0FFB8h
I/O port P9 P9IFG.0 to P9IFG.7 P9IV(1) Maskable 0FFB6h
LEA CMDIFG, SDIIFG, OORIFG, TIFG, COVLIFG LEAIV(1) Maskable 0FFB4h
UUPS PTMOUT, PREQIG IIDX(1) Maskable 0FFB2h
HSPLL PLLUNLOCK IIDX(1) Maskable 0FFB0h
SAPH DATAERR, TAMTO, SEQDN, PNGDN IIDX(1) Maskable 0FFAEh
SDHS OVF, ACQDONE, SSTRG, DTRDY, WINHI, WINLO IIDX(1) Maskable 0FFACh Lowest
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space.
(3) (Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot disable it.
(4) Only on devices with ADC, otherwise reserved.
Table 9-5 Signatures
SIGNATURE WORD ADDRESS
IP Encapsulation Signature2 0FF8Ah
IP Encapsulation Signature1(1) 0FF88h
BSL Signature2 0FF86h
BSL Signature1 0FF84h
JTAG Signature2 0FF82h
JTAG Signature1 0FF80h
(1) Must not contain 0AAAAh if used as the JTAG password.