SLASEB7 Data sheet

SLASEB7D June 2017 – December 2020 MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

PZ|100
- MTQF013A

Thermal pad, mechanical data (Package|Pins)

PZ|100
- QFND428

Orderable Information

8.13.8.6 eUSCI (SPI Slave Mode) Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS	V_CC	MIN	MAX	UNIT
t_STE,LEAD	STE lead time, STE active to clock		2.2 V	45		ns
t_STE,LEAD	STE lead time, STE active to clock		3.0 V	40		ns
t_STE,LAG	STE lag time, Last clock to STE inactive		2.2 V	2		ns
t_STE,LAG	STE lag time, Last clock to STE inactive		3.0 V	3		ns
t_STE,ACC	STE access time, STE active to SOMI data out		2.2 V		45	ns
t_STE,ACC	STE access time, STE active to SOMI data out		3.0 V		40	ns
t_STE,DIS	STE disable time, STE inactive to SOMI high impedance		2.2 V		50	ns
t_STE,DIS	STE disable time, STE inactive to SOMI high impedance		3.0 V		45	ns
t_SU,SI	SIMO input data setup time		2.2 V	4		ns
t_SU,SI	SIMO input data setup time		3.0 V	4		ns
t_HD,SI	SIMO input data hold time		2.2 V	7		ns
t_HD,SI	SIMO input data hold time		3.0 V	7		ns
t_VALID,SO	SOMI output data valid time⁽²⁾	UCLK edge to SOMI valid, C_L = 20 pF	2.2 V		35	ns
t_VALID,SO	SOMI output data valid time⁽²⁾	UCLK edge to SOMI valid, C_L = 20 pF	3.0 V		35	ns
t_HD,SO	SOMI output data hold time⁽³⁾	C_L = 20 pF	2.2 V	0		ns
t_HD,SO	SOMI output data hold time⁽³⁾	C_L = 20 pF	3.0 V	0		ns

(1) f_UCxCLK = 1/2 t_LO/HI with t_LO/HI ≥ max(t_{VALID,MO(Master)} + t_SU,SI(eUSCI), t_{SU,MI(Master)} + t_{VALID,SO(eUSCI)})
For the master parameters t_{SU,MI(Master)} and t_{VALID,MO(Master)}, see the SPI parameters of the attached master.

(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams in Figure 8-14 and Figure 8-15.

(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 8-14 and Figure 8-15.