SLASF11C February   2023  – October 2023 MSPM0G1106 , MSPM0G1107

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 POR and BOR
      2. 7.6.2 Power Supply Ramp
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
        1. 7.9.1.1 SYSOSC Typical Frequency Accuracy
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
      3. 7.9.3 System Phase Lock Loop (SYSPLL)
      4. 7.9.4 Low Frequency Crystal/Clock
      5. 7.9.5 High Frequency Crystal/Clock
    10. 7.10 Digital IO
      1. 7.10.1 Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
      4. 7.12.4 Typical Connection Diagram
    13. 7.13 Temperature Sensor
    14. 7.14 VREF
      1. 7.14.1 Voltage Characteristics
      2. 7.14.2 Electrical Characteristics
    15. 7.15 GPAMP
      1. 7.15.1 Electrical Characteristics
      2. 7.15.2 Switching Characteristics
    16. 7.16 I2C
      1. 7.16.1 I2C Timing Diagram
      2. 7.16.2 I2C Characteristics
      3. 7.16.3 I2C Filter
    17. 7.17 SPI
      1. 7.17.1 SPI
      2. 7.17.2 SPI Timing Diagram
    18. 7.18 UART
    19. 7.19 TIMx
    20. 7.20 Emulation and Debug
      1. 7.20.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode (MSPM0G110x)
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 GPAMP
    16. 8.16 CRC
    17. 8.17 UART
    18. 8.18 I2C
    19. 8.19 SPI
    20. 8.20 WWDT
    21. 8.21 RTC
    22. 8.22 Timers (TIMx)
    23. 8.23 Device Analog Connections
    24. 8.24 Input/Output Diagrams
    25. 8.25 Serial Wire Debug Interface
    26. 8.26 Bootstrap Loader (BSL)
    27. 8.27 Device Factory Constants
    28. 8.28 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Getting Started and Next Steps
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
  13. 12Revision History

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.2 Pin Attributes

The following table describes the functions available on every pin for each device package.

Note: Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) which allows users to configure the desired Pin Function using the PINCM.PF control bits.
Table 6-1 Pin Attributes
PINCMx PIN NAME SIGNAL NAMES PIN NUMBER IO STRUCTURE
ANALOG DIGITAL [PIN FUNCTION] (1) 64 LQFP 48 LQFP, VQFN 32 VQFN 28 VSSOP 24 VQFN
N/A VDD 40 6 4 7 3 Power
N/A VSS 41 7 5 8 4 Power
N/A VCORE 32 48 32 3 23 Power
N/A NRST 38 4 3 6 2 Reset
1 PA0 UART0_TX [2] / I2C0_SDA [3] / TIMA0_C0 [4] / TIMA_FAL1 [5] / TIMG8_C1 [6] / FCC_IN [7]/(Default BSL I2C_SDA) 33 1 1 4 24 5-V tolerant open drain
2 PA1 UART0_RX [2] / I2C0_SCL [3] / TIMA0_C1 [4] / TIMA_FAL2 [5] / TIMG8_IDX [6] / TIMG8_C0 [7]/(Default BSL I2C_SCL) 34 2 2 5 1 5-V tolerant open drain
7 PA2 ROSC TIMG8_C1 [2] / SPI0_CS0 [3] / TIMG7_C1 [4] / SPI1_CS0 [5] 42 8 6 9 5 Standard
8 PA3 LFXIN TIMG8_C0 [2] / SPI0_CS1 [3] / UART2_CTS [4] / TIMA0_C2 [5] / TIMG7_C0 [7] / TIMA0_C1 [8] / I2C1_SDA [9] 43 9 7 10 6 Standard
9 PA4 LFXOUT TIMG8_C1 [2] / SPI0_POCI [3] / UART2_RTS [4] / TIMA0_C3 [5] / LFCLK_IN [6] / TIMG7_C1 [7] / TIMA0_C1N [8] / I2C1_SCL [9] 44 10 8 11 7 Standard
10 PA5 HFXIN TIMG8_C0 [2] / SPI0_PICO [3] / TIMA_FAL1 [4] / TIMG0_C0 [5]/ TIMG6_C0 [6] / FCC_IN [7] 45 11 9 12 - Standard
11 PA6 HFXOUT TIMG8_C1 [2] / SPI0_SCK [3] / TIMA_FAL0 [4] / TIMG0_C1 [5] / HFCLK_IN [6] / TIMG6_C1 [ 7] / TIMA0_C2N [8] 46 12 10 13 - Standard
14 PA7 CLK_OUT [3] / TIMG8_C0 [4] / TIMA0_C2 [5] / TIMG8_IDX [6] / TIMG7_C1 [7] / TIMA0_C1 [8] 49 13 11 - - Standard
19 PA8 UART1_TX [2] / SPI0_CS0 [3] / UART0_RTS [4] / TIMA0_C0 [5] / TIMA1_C0N [6] 54 16 12 - - Standard
20 PA9 UART1_RX [2] / SPI0_PICO [3] / UART0_CTS [4] / TIMA0_C1 [5] / RTC_OUT [6] / TIMA0_C0N [7] / TIMA1_C1N [8] / CLK_OUT [9] 55 17 13 14 8 High-Speed
21 PA10 UART0_TX [2] / SPI0_POCI [3] / I2C0_SDA [4] / TIMA1_C0 [5] / TIMG12_C0 [6] / TIMA0_C2 [7] / I2C1_SDA [8] / CLK_OUT [9]/(Default BSL UART_TX) 56 18 14 15 9 High-Drive
22 PA11 UART0_RX [2] / SPI0_SCK [3] / I2C0_SCL [4] / TIMA1_C1 [5] / TIMA0_C2N [6] / I2C1_SCL [7]/(Default BSL UART_RX) 57 19 15 16 10 High-Drive
34 PA12 UART3_CTS [2] / SPI0_SCK [3] / TIMG0_C0 [4] / TIMA0_C3 [6] / FCC_IN [7] 5 27 16 - - High-Speed
35 PA13 UART3_RTS [2] / SPI0_POCI [3] / UART3_RX [4] / TIMG0_C1 [5] / TIMA0_C3N [7] 6 28 17 - - High-Speed
36 PA14 A0_12 UART0_CTS [2] / SPI0_PICO [3] / UART3_TX [4] / TIMG12_C0 [5] / CLK_OUT [6] 7 29 18 17 - High-Speed
37 PA15 A1_0 UART0_RTS [2] / SPI1_CS2 [3] / I2C1_SCL [4] / TIMA1_C0 [5] / TIMG8_IDX [6] / TIMA1_C0N [7] / TIMA0_C2 [8] 8 30 19 18 11 Standard
38 PA16 A1_1 SPI1_POCI [3] / I2C1_SDA [4] / TIMA1_C1 [5] / TIMA1_C1N [6] / TIMA0_C2N [7] / FCC_IN [8] 9 31 20 19 12 Standard
39 PA17 A1_2 UART1_TX [2] / SPI1_SCK [3] / I2C1_SCL [4] / TIMA0_C3 [5] / TIMG7_C0 [6] / TIMA1_C0 [7] 10 32 21 20 13 Standard with wake(2)
40 PA18 A1_3 / GPAMP_IN- UART1_RX [2] / SPI1_PICO [3] / I2C1_SDA [4] / TIMA0_C3N [5] / TIMG7_C1 [6] / TIMA1_C1 [7]/Default BSL_Invoke 11 33 22 21 14 Standard with wake(2)
41 PA19 SWDIO [2] 12 34 23 22 15 High-Speed
42 PA20 SWCLK [2] 13 35 24 23 16 Standard
46 PA21 A1_7 / VREF- UART2_TX [2] / TIMG8_C0 [3] / UART1_CTS [4] / TIMA0_C0 [5] / TIMG6_C0 [6] 17 39 25 24 17 Standard
47 PA22 A0_7 / GPAMP_OUT UART2_RX [2] / TIMG8_C1 [3] / UART1_RTS [4] / TIMA0_C1 [5] / CLK_OUT [6] / TIMA0_C0N [7] / TIMG6_C1 [8] 18 40 26 25 18 Standard
53 PA23 VREF+ UART2_TX [2] / SPI0_CS3 [3] / TIMA0_C3 [4] / TIMG0_C0 [5] / UART3_CTS [6] / TIMG7_C0 [7]/ TIMG8_C0 [8] 24 43 27 26 19 Standard
54 PA24 A0_3 UART2_RX [2] / SPI0_CS2 [3] / TIMA0_C3N [4] / TIMG0_C1 [5] / UART3_RTS [6] / TIMG7_C1 [7] / TIMA1_C1 [8] 25 44 28 27 20 Standard
55 PA25 A0_2 UART3_RX [2] / SPI1_CS3 [3] / TIMG12_C1 [4] / TIMA0_C3 [5] / TIMA0_C1N [6] 26 45 29 28 21 Standard
59 PA26 A0_1 / GPAMP_IN+ UART3_TX [2] / SPI1_CS0 [3] / TIMG8_C0 [4] / TIMA_FAL0 [5] / TIMG7_C0 [7] 30 46 30 1 22 Standard
60 PA27 A0_0 RTC_OUT [2] / SPI1_CS1 [3] / TIMG8_C1 [4] / TIMA_FAL2 [5] / TIMG7_C1 [7] 31 47 31 2 Standard
3 PA28 UART0_TX [2] / I2C0_SDA [3] / TIMA0_C3 [4] / TIMA_FAL0 [5] / TIMG7_C0 [6] / TIMA1_C0 [ 7] 35 3 - - - High-Drive
4 PA29 I2C1_SCL [2] / UART2_RTS [3] / TIMG8_C0 [4] / TIMG6_C0 [5] 36 - - - - Standard
5 PA30 I2C1_SDA [2] / UART2_CTS [3] / TIMG8_C1 [4] / TIMG6_C1 [5] 37 - - - - Standard
6 PA31 UART0_RX [2] / I2C0_SCL [3] / TIMA0_C3N [4] / TIMG12_C1 [5] / CLK_OUT [6]/ TIMG7_C1 [7] / TIMA1_C1 [8] 39 5 - - - High-Drive
12 PB0 UART0_TX [2] / SPI1_CS2 [3] / TIMA1_C0 [4] / TIMA0_C2 [5] 47 - - - - Standard
13 PB1 UART0_RX [2] / SPI1_CS3 [3] / TIMA1_C1 [4] / TIMA0_C2N [5] 48 – – - - Standard
15 PB2 UART3_TX [2] / UART2_CTS [3] / I2C1_SCL [4] / TIMA0_C3 [5] / UART1_CTS [6] / TIMG6_C0 [ 7] / TIMA1_C0 [8] 50 14 – - - Standard
16 PB3 UART3_RX [2] / UART2_RTS [3] / I2C1_SDA [4] / TIMA0_C3N[5] / UART1_RTS [6] / TIMG6_C1 [7] / TIMA1_C1 [8] 51 15 – - - Standard
17 PB4 UART1_TX [2] / UART3_CTS [3] / TIMA1_C0 [4] /TIMA0_C2 [5] / TIMA1_C0N [6] 52 – – - - Standard
18 PB5 UART1_RX [2] / UART3_RTS [3] / TIMA1_C1 [4] / TIMA0_C2N [5] / TIMA1_C1N [6] 53 - - - - Standard
23 PB6 UART1_TX [2] / SPI1_CS0 [3] / SPI0_CS1 [4] / TIMG8_C0 [5] / UART2_CTS [6] / TIMG6_C0 [7] / TIMA1_C0N [8] 58 20 - - - Standard
24 PB7 UART1_RX [2] / SPI1_POCI [3] / SPI0_CS2 [4] / TIMG8_C1 [5] / UART2_RTS [6] / TIMG6_C1 [7] /TIMA1_C1N [8] 59 21 - - - Standard
25 PB8 UART1_CTS [2] / SPI1_PICO [3] / TIMA0_C0 [4] 60 22 - - - Standard
26 PB9 UART1_RTS [2] / SPI1_SCK [3] / TIMA0_C1 [4] / TIMA0_C0N [5] 61 23 - - - Standard
27 PB10 TIMG0_C0 [2] / TIMG8_C0 [3] / TIMG6_C0 [5] 62 - - - - Standard
28 PB11 TIMG0_C1 [2] / TIMG8_C1 [3] / CLK_OUT [4] / TIMG6_C1 [5] 63 - - - - Standard
29 PB12 UART3_TX [2] / TIMA0_C2 [3] / TIMA_FAL1 [4] / TIMA0_C1 [5] 64 - - - - Standard
30 PB13 UART3_RX [2] / TIMA0_C3 [3] / TIMG12_C0 [4] / TIMA0_C1N [5] 1 - - - - Standard
31 PB14 SPI1_CS3 [2] / SPI1_POCI [3] / SPI0_CS3 [4] / TIMG12_C1 [5] / TIMG8_IDX [6] / TIMA0_C0 [7] 2 24 - - - Standard
32 PB15 UART2_TX [2] / SPI1_PICO [3] / UART3_CTS [4] / TIMG8_C0 [5] / TIMG7_C0 [6] 3 25 - - - Standard
33 PB16 UART2_RX [2] / SPI1_SCK [3] / UART3_RTS [4] / TIMG8_C1 [5] / TIMG7_C1 [6] 4 26 - - - Standard
43 PB17 A1_4 UART2_TX [2] / SPI0_PICO [3] / SPI1_CS1 [4] / TIMA1_C0 [5] / TIMA0_C2 [6] 14 36 - - - Standard
44 PB18 A1_5 UART2_RX [2] / SPI0_SCK [3] / SPI1_CS2 [4] / TIMA1_C1 [5] / TIMA0_C2N [6] 15 37 - - - Standard
45 PB19 A1_6 SPI0_POCI [3] / TIMG8_C1 [4] / UART0_CTS [5] / TIMG7_C1 [6] 16 38 - - - Standard
48 PB20 A0_6 SPI0_CS2 [2] / SPI1_CS0 [3] / TIMA0_C2 [4] / TIMG12_C0 [5] / TIMA_FAL1 [6] / TIMA0_C1 [7] / TIMA1_C1N [8] 19 41 - - - Standard
49 PB21 SPI1_POCI [2] / TIMG8_C0 [3] 20 - - - - Standard
50 PB22 SPI1_PICO [2] / TIMG8_C1 [3] 21 - - - - Standard
51 PB23 SPI1_SCK [2] / TIMA_FAL0 [4] 22 - - - - Standard
52 PB24 A0_5 SPI0_CS3 [2] / SPI0_CS1 [3] / TIMA0_C3 [4] / TIMG12_C1 [5] / TIMA0_C1N [6] / TIMA1_C0N [7] 23 42 - - - Standard
56 PB25 A0_4 UART0_CTS [2] / SPI0_CS0 [3] / TIMA_FAL2 [4] 27 - - - - Standard
57 PB26 UART0_RTS [2] / SPI0_CS1 [3] / TIMA0_C3 [4] / TIMG6_C0 [5] 28 - - - Standard
58 PB27 SPI1_CS1 [3] / TIMA0_C3N [4] / TIMG6_C1 [5] / TIMA1_C1 [6] 29 - - - - Standard
(1) Set PINCM.PF and PINCM.PC in IOMUX to 0 for analog functions (for example, OPA inputs/outputs or COMP inputs). Each digital I/O on a device is mapped to a specific Pin Control Management register (PINCMx) that lets users configure the desired pin function using the PINCM.PF control bits.
(2) Standard with Wake allows the I/O to wake up the device from the lowest low-power mode of SHUTDOWN. All I/O can be configured to wakeup the MCU from higher low-power modes. See section GPIO FastWake in the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual for details.
Table 6-2 Digital IO Features by IO Type
IO STRUCTURE INVERSION CONTROL DRIVE STRENGTH CONTROL HYSTERESIS CONTROL PULLUP RESISTOR PULLDOWN RESISTOR WAKEUP LOGIC
Standard-drive Y Y Y
Standard-drive with wake(1) Y Y Y Y
High-drive Y Y Y Y Y
High-speed Y Y Y Y
5-V tolerant open drain Y Y Y Y
(1) Standard with Wake allows the I/O to wake up the device from the lowest low-power mode of SHUTDOWN. All I/O can be configured to wakeup the MCU from higher low-power modes. See section GPIO FastWake in the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual for details.