SLASEX0D October   2022  – January 2024 MSPM0L1303 , MSPM0L1304 , MSPM0L1305 , MSPM0L1306 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Supply Current Characteristics
      1. 7.5.1 RUN/SLEEP Modes
      2. 7.5.2 STOP/STANDBY Modes
      3. 7.5.3 SHUTDOWN Mode
    6. 7.6  Power Supply Sequencing
      1. 7.6.1 POR and BOR
      2. 7.6.2 Power Supply Ramp
    7. 7.7  Flash Memory Characteristics
    8. 7.8  Timing Characteristics
    9. 7.9  Clock Specifications
      1. 7.9.1 System Oscillator (SYSOSC)
      2. 7.9.2 Low Frequency Oscillator (LFOSC)
    10. 7.10 Digital IO
      1. 7.10.1 Electrical Characteristics
      2. 7.10.2 Switching Characteristics
    11. 7.11 Analog Mux VBOOST
    12. 7.12 ADC
      1. 7.12.1 Electrical Characteristics
      2. 7.12.2 Switching Characteristics
      3. 7.12.3 Linearity Parameters
      4. 7.12.4 Typical Connection Diagram
    13. 7.13 Temperature Sensor
    14. 7.14 VREF
      1. 7.14.1 Voltage Characteristics
      2. 7.14.2 Electrical Characteristics
    15. 7.15 COMP
      1. 7.15.1 Comparator Electrical Characteristics
    16. 7.16 GPAMP
      1. 7.16.1 Electrical Characteristics
      2. 7.16.2 Switching Characteristics
    17. 7.17 OPA
      1. 7.17.1 Electrical Characteristics
      2. 7.17.2 Switching Characteristics
      3. 7.17.3 PGA Mode
    18. 7.18 I2C
      1. 7.18.1 I2C Characteristics
      2. 7.18.2 I2C Filter
      3. 7.18.3 I2C Timing Diagram
    19. 7.19 SPI
      1. 7.19.1 SPI
      2. 7.19.2 SPI Timing Diagram
    20. 7.20 UART
    21. 7.21 TIMx
    22. 7.22 Emulation and Debug
      1. 7.22.1 SWD Timing
  9. 8 Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
      1. 8.2.1 Functionality by Operating Mode
    3. 8.3  Power Management Unit (PMU)
    4. 8.4  Clock Module (CKM)
    5. 8.5  DMA
    6. 8.6  Events
    7. 8.7  Memory
      1. 8.7.1 Memory Organization
      2. 8.7.2 Peripheral File Map
      3. 8.7.3 Peripheral Interrupt Vector
    8. 8.8  Flash Memory
    9. 8.9  SRAM
    10. 8.10 GPIO
    11. 8.11 IOMUX
    12. 8.12 ADC
    13. 8.13 Temperature Sensor
    14. 8.14 VREF
    15. 8.15 COMP
    16. 8.16 CRC
    17. 8.17 GPAMP
    18. 8.18 OPA
    19. 8.19 I2C
    20. 8.20 SPI
    21. 8.21 UART
    22. 8.22 WWDT
    23. 8.23 Timers (TIMx)
    24. 8.24 Device Analog Connections
    25. 8.25 Input/Output Diagrams
    26. 8.26 Serial Wire Debug Interface
    27. 8.27 Bootstrap Loader (BSL)
    28. 8.28 Device Factory Constants
    29. 8.29 Identification
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Typical Application
      1. 9.1.1 Schematic
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGE|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3 Signal Descriptions

Table 6-3 Signal Descriptions
FUNCTION SIGNAL NAME PIN NO. (1) PIN TYPE (2) DESCRIPTION
32 VQFN 28 VSSOP (3) 28 VSSOP (4) 24 VQFN 20 VSSOP 16 WQFN 16 SOT
ADC A0 31 2 2 – 2 – – I ADC0 analog input 0
A1 30 1 1 22 1 – 1 I ADC0 analog input 1
A2 29 28 28 21 20 2 16 I ADC0 analog input 2
A3 28 27 – 20 19 (3) – 15 I ADC0 analog input 3
A4 26 25 25 18 17 1 13 I ADC0 analog input 4
A5 25 24 24 17 – – – I ADC0 analog input 5
A6 24 23 23 16 16 16 12 I ADC0 analog input 6
A7 22 21 21 14 14 14 10 I ADC0 analog input 7
A8 20 19 18 12 12 13 – I ADC0 analog input 8
A9 19 18 17 11 – 12 – I ADC0 analog input 9
BSL BSL_invoke 22 21 21 14 14 14 10 I Input pin used to invoke bootloader
BSL (I2C) BSLSCL 2 5 5 1 5 5 4 I/O Default I2C BSL clock
BSLSDA 1 4 4 24 4 4 3 I/O Default I2C BSL data
BSL (UART) BSLRX 26 25 25 18 17 1 13 I Default UART BSL receive
BSLTX 27 26 26 19 18 2 14 O Default UART BSL transmit
Clock CLK_OUT 11
18
26		 17
25		 16
25		 18 17 1
11		 13 O Configurable clock output
ROSC 6 9 9 5 8 8 7 I External resistor used for improving oscillator accuracy
Comparator COMP0_IN0- 31 2 2 – 2 – – I Comparator 0 inverting input 0
COMP0_IN0+ 30 1 1 22 1 – 1 I Comparator 0 non-inverting input 0
COMP0_IN1- 27 26 26 19 18 2 14 I Comparator 0 inverting input 1
COMP0_IN1+ 24 23 23 16 16 16 12 I Comparator 0 non-inverting input 1
COMP0_OUT 7
11
15
20		 10
16
19		 10
18		 6
12		 11
12		 13 – O Comparator 0 output
Debug SWCLK 24 23 23 16 16 16 12 I Serial wire debug input clock
SWDIO 23 22 22 15 15 15 11 I/O Serial wire debug data input/output
General-Purpose Amplifier GPAMP_IN+ 30 1 1 22 1 – 1 I GPAMP non-inverting terminal input
GPAMP_OUT 26 25 25 18 17 1 13 O GPAMP output
GPAMP_IN- 22 21 21 14 14 14 10 I GPAMP inverting terminal input
GPIO PA0 1 4 4 24 4 4 3 I/O General-purpose digital I/O with wake up from SHUTDOWN
PA1 2 5 5 1 5 5 4 I/O General-purpose digital I/O with wake up from SHUTDOWN
PA2 6 9 9 5 8 8 7 I/O General-purpose digital I/O
PA3 7 10 10 6 – – – I/O General-purpose digital I/O
PA4 8 11 11 7 9 – – I/O General-purpose digital I/O
PA5 9 12 12 – – 9 – I/O General-purpose digital I/O
PA6 10 13 13 – 10 10 8 I/O General-purpose digital I/O
PA7 11 – – – – – – I/O General-purpose digital I/O
PA8 12 – – – – – – I/O General-purpose digital I/O
PA9 13 14 14 8 – – – I/O General-purpose digital I/O
PA10 14 15 – 9 – 11 – I/O General-purpose digital I/O
PA11 15 16 – 10 11 – – I/O General-purpose digital I/O
PA12 16 – – – – – – I/O General-purpose digital I/O
PA13 17 – 15 – – – – I/O General-purpose digital I/O
PA14 18 17 16 – – 11 – I/O General-purpose digital I/O
PA15 19 18 17 11 – 12 – I/O General-purpose digital I/O
PA16 20 19 18 12 12 13 – I/O General-purpose digital I/O
PA17 21 20 19 13 13 (3) 14 9 I/O General-purpose digital I/O with wake up from SHUTDOWN
PA18 22 21 21 14 14 14 10 I/O General-purpose digital I/O with wake up from SHUTDOWN
PA19 23 22 22 15 15 15 11 I/O General-purpose digital I/O
PA20 24 23 23 16 16 16 12 I/O General-purpose digital I/O
PA21 25 24 24 17 – – – I/O General-purpose digital I/O
PA22 26 25 25 18 17 1 13 I/O General-purpose digital I/O
PA23 27 26 26 19 18 2 14 I/O General-purpose digital I/O
PA24 28 27 – 20 19 (3) – 15 I/O General-purpose digital I/O
PA25 29 28 28 21 20 2 16 I/O General-purpose digital I/O
PA26 30 1 1 22 1 – 1 I/O General-purpose digital I/O
PA27 31 2 2 – 2 – – I/O General-purpose digital I/O
I2C I2C0_SCL 2
15		 5
16		 5 1
10		 5
11		 5 4 I/O I2C0 serial clock
I2C0_SDA 1
14		 4
15		 4 24
9		 4 4
11		 3 I/O I2C0 serial data
I2C1_SCL 19
21
24		 18
20
23		 17
19
23		 11
13
16		 13 (3)
16		 12
16		 9
12		 I/O I2C1 serial clock
I2C1_SDA 20
22
23		 19
21
22		 18
21
22		 12
14
15		 12
14
15		 13
14
15		 10
11		 I/O I2C1 serial data
Operational Amplifier with Chopping (Zero-Drift Op-Amp) OPA0_IN0+ 29 28 28 21 20 2 16 I OPA0 non-inverting terminal input 0
OPA0_IN0- 28 27 27 20 19 – 15 I OPA0 inverting terminal input 0
OPA0_IN1- 28 27 – 20 19 (3) – 15 I OPA0 inverting terminal input 1
OPA0_OUT 26 25 25 18 17 1 13 O OPA0 output
OPA1_IN0+ 22 21 21 14 14 14 10 I OPA1 non-inverting terminal input 0
OPA1_IN0- 21 20 20 13 13 14 9 I OPA1 inverting terminal input 0
OPA1_IN1- 21 20 19 13 13 (3) – 9 I OPA1 inverting terminal input 1
OPA1_OUT 20 19 18 12 12 13 – O OPA1 output
Power VSS 5 8 8 4 7 7 6 P Ground supply
VDD 4 7 7 3 6 6 5 P Power supply
VCORE 32 3 3 23 3 3 2 P Regulated core power supply output
QFN Pad Pad – – Pad – Pad – P QFN package exposed thermal pad. TI recommends connection to VSS.
SPI SPI0_CS0 6
12		 9 9 5 8 8 7 I/O SPI0 chip-select 0
SPI0_CS1 1
7
21		 4
10
20		 4
10
19		 6
13
24		 4
13(3)		 4 3
9		 I/O SPI0 chip-select 1
SPI0_CS2 19
28		 18
27		 17 11
20		 19 (3) 12 15 I/O SPI0 chip-select 2
SPI0_CS3 27
31		 2
26		 2
26		 19 2
18		 2 14 I/O SPI0 chip-select 3
SPI0_SCK 10
15
21		 13
16
20		 13
19		 10
13		 10
11
13 (3)		 10 8
9		 I/O SPI0 clock signal input – SPI peripheral mode
Clock signal output – SPI controller mode
SPI0_POCI 8
14
20
23
30		 1
11
15
19
22		 1
11
18
22		 7
9
12
15
22		 1
9
12
15		 11
13
15		 1
11		 I/O SPI0 controller in/peripheral out
SPI0_PICO 9
13
22
29		 12
14
21
28		 12
14
21
28		 8
14
21		 14
20		 2
9
14		 10
16		 I/O SPI0 controller out/peripheral in
System NRST 3 6 6 2 5 5 4 I Reset input active low
Timer TIMG0_C0 9
16
20
27		 12
19
26		 12
18
26		 12
19		 12
18		 2
9
13		 14 I/O General purpose timer 0 CCR0 capture input/ compare output
TIMG0_C1 10
17
28		 13
27		 13
15		 20 10
19 (3)		 10 8
15		 I/O General purpose timer 0 CCR1 capture input/ compare output
TIMG1_C0 1
11
18
30		 1
4
17		 1
4
16		 22
24		 1
4		 4
11		 1
3		 I/O General purpose timer 1 CCR0 capture input/ compare output
TIMG1_C1 2
6
31		 2
5
9		 2
5
9		 1
5		 2
5
8		 5
8 		4
7		 I/O General purpose timer 1 CCR1 capture input/ compare output
TIMG2_C0 7
12
25		 10
24		 10
24		 6
17		 – – – I/O General purpose timer 2 CCR0 capture input/ compare output
TIMG2_C1 8
13
26		 11
14
25		 11
14
25		 7
8
18		 9
17		 1 13 I/O General purpose timer 2 CCR1 capture input/ compare output
TIMG4_C0 14
21
24		 15
20
23		 19
23		 9
13
16		 13(3)
16		 11
16		 9
12		 I/O General purpose timer 4 CCR0 capture input/ compare output
TIMG4_C1 15
19
22
29		 16
18
21
28		 17
21
28		 10
11
14
21		 11
14
20		 2
12
14		 10
16		 I/O General purpose timer 4 CCR1 capture input/ compare output
UART UART0_TX 12
21
25
27
29		 20
24
26
28		 19
24
26
28		 13
17
19
21		 13 (3)
18
20		 2 9
14
16		 O UART0 transmit data
UART0_RX 13
22
26
30		 1
14
21
25		 1
14
21
25		 8
14
18
22		 1
14
17		 1
14		 1
10
13		 I UART0 receive data
UART0_CTS 16
25
27		 24
26		 24
26		 17
19		 18 2 14 I UART0 "clear to send" flow control input
UART0_RTS 17
26
28		 25
27		 15
25		 18
20		 17
19 (3)		 1 13
15		 O UART0 "request to send" flow control output
UART1_TX 1
14
18
27		 4
15
17
26		 4
16
26		 9
19
24		 4
18		 2
4
11		 3
14		 O UART1 transmit data
UART1_RX 2
15
17
26		 5
16
25		 5
15
25 		1
10
18		 5
11
17		 1
5		 4
13		 I UART1 receive data
UART1_CTS 7
13
18		 10
14
17		 10
14
16		 6
8		 – 11 – I UART1 "clear to send" flow control input
UART1_RTS 8
12
19		 11
18		 11
17		 7
11		 9 12 – O UART1 "request to send" flow control output
Voltage Reference(5) VREF+ 27 26 26 19 18 2 14 I Voltage reference power supply - external reference input
VREF- 25 24 24 17 – – – I Voltage reference ground supply - external reference input
(1) – = not available
(2) I = input, O = output, I/O = input or output, P = power
(3) MSPM0L130x only
(4) MSPM0L134x only
(5) When using VREF+ and VREF- to bring in an external voltage reference for analog peripherals such as the ADC, a decoupling capacitor must be placed on VREF+ to VREF-/GND with a capacitance based on the external reference source