SLASF59 Data sheet

SLASF59A May 2023 – December 2023 MSPM0L1304-Q1 , MSPM0L1305-Q1 , MSPM0L1306-Q1

PRODUCTION DATA

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

DGS|28
DYY|16
RGE|24
RHB|32
DGS|32
DGS|20

Thermal pad, mechanical data (Package|Pins)

Orderable Information

10.2 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP MCU devices and support tools. Each MSP MCU automotive family member has one of two prefixes: M0 or XM0. These prefixes represent evolutionary stages of product development from engineering prototypes (XM0) through fully qualified production devices (M0).

X or XMS – Experimental device that is not necessarily representative of the final device's electrical specifications

M0 – Fully qualified production device

X and XMS devices are shipped against the following disclaimer:

"Developmental product is intended for internal evaluation purposes." MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (X) have a greater failure rate than the standard production devices. TI recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature range, package type, and distribution format. Figure 10-1 provides a legend for reading the complete device name.

Figure 10-1 Device Nomenclature

Table 10-1 Device Nomenclature

MCU Platform	M0 = Arm-based 32-bit M0+ XM0 = Experimental silicon Arm-based 32-bit M0+
Product Family	L = 32-MHz frequency
Device Subfamily	130 = ADC, 2x OPA, COMP
Internal Memory	4 = 16KB flash, 2KB SRAM 5 = 32KB flash, 4KB SRAM 6 = 64KB flash, 4KB SRAM
Temperature Range	Q = –40°C to 125°C , AEC-Q100 qualified
Package Type	See top map SLASEX0 SLASF57 SLASF59 MSPM0L130x-Q1 Automotive Mixed-Signal Microcontrollers MSPM0L130x-Q1 Automotive Mixed-Signal Microcontrollers Features Features Applications Applications Description Description Functional Block Diagram Functional Block Diagram Table of Contents Table of Contents Device Comparison Device Comparison Pin Configuration and Functions Pin Configuration and Functions Pin Diagrams Pin Diagrams Pin Attributes Pin Attributes Signal Descriptions Signal Descriptions Connections for Unused Pins Connections for Unused Pins Specifications Specifications Absolute Maximum Ratings Absolute Maximum Ratings ESD Ratings ESD Ratings Recommended Operating Conditions Recommended Operating Conditions Thermal Information Thermal Information Supply Current Characteristics Supply Current Characteristics RUN/SLEEP Modes RUN/SLEEP Modes STOP/STANDBY Modes STOP/STANDBY Modes SHUTDOWN Mode SHUTDOWN Mode Power Supply Sequencing Power Supply Sequencing POR and BOR POR and BOR Power Supply Ramp Power Supply Ramp Flash Memory Characteristics Flash Memory Characteristics Timing Characteristics Timing Characteristics Clock Specifications Clock Specifications System Oscillator (SYSOSC) System Oscillator (SYSOSC) Low Frequency Oscillator (LFOSC) Low Frequency Oscillator (LFOSC) Digital IO Digital IO Electrical Characteristics Electrical Characteristics Switching Characteristics Switching Characteristics Analog Mux VBOOST Analog Mux VBOOST ADC ADC Electrical Characteristics Electrical Characteristics Switching Characteristics Switching Characteristics Linearity Parameters Linearity Parameters Typical Connection Diagram Typical Connection Diagram Temperature Sensor Temperature Sensor VREF VREF Voltage Characteristics Voltage Characteristics Electrical Characteristics Electrical Characteristics COMP COMP Comparator Electrical Characteristics Comparator Electrical Characteristics GPAMP GPAMP Electrical Characteristics Electrical Characteristics Switching Characteristics Switching Characteristics OPA OPA Electrical Characteristics Electrical Characteristics Switching Characteristics Switching Characteristics PGA Mode PGA Mode I2C I2C I2C Characteristics I2C Characteristics I2C Filter I2C Filter I2C Timing Diagram I2C Timing Diagram SPI SPI SPI SPI SPI Timing Diagram SPI Timing Diagram UART UART TIMx TIMx Emulation and Debug Emulation and Debug SWD Timing SWD Timing Detailed Description Detailed Description CPU CPU Operating Modes Operating Modes Functionality by Operating Mode Functionality by Operating Mode Power Management Unit (PMU) Power Management Unit (PMU) Clock Module (CKM) Clock Module (CKM) DMA DMA Events Events Memory Memory Memory Organization Memory Organization Peripheral File Map Peripheral File Map Peripheral Interrupt Vector Peripheral Interrupt Vector Flash Memory Flash Memory SRAM SRAM GPIO GPIO IOMUX IOMUX ADC ADC Temperature Sensor Temperature Sensor VREF VREF COMP COMP CRC CRC GPAMP GPAMP OPA OPA I2C I2C SPI SPI UART UART WWDT WWDT Timers (TIMx) Timers (TIMx) Device Analog Connections Device Analog Connections Input/Output Diagrams Input/Output Diagrams Serial Wire Debug Interface Serial Wire Debug Interface Bootstrap Loader (BSL) Bootstrap Loader (BSL) Device Factory Constants Device Factory Constants Identification Identification Applications, Implementation, and Layout Applications, Implementation, and Layout Typical Application Typical Application Schematic Schematic Device and Documentation Support Device and Documentation Support Getting Started and Next Steps Getting Started and Next Steps Device Nomenclature Device Nomenclature Tools and Software Tools and Software Documentation Support Documentation Support Support Resources Support Resources Trademarks Trademarks Electrostatic Discharge Caution Electrostatic Discharge Caution Glossary Glossary Revision History Revision History Mechanical, Packaging, and Orderable Information Mechanical, Packaging, and Orderable Information IMPORTANT NOTICE AND DISCLAIMER IMPORTANT NOTICE AND DISCLAIMER MSPM0L130x-Q1 Automotive Mixed-Signal Microcontrollers MSPM0L130x-Q1 Automotive Mixed-Signal MicrocontrollersMSPM0L130x-Q1 Automotive Features 20231201 Changes throughout document for final device characterization and release as Production Data yes AEC-Q100 qualified for automotive applications Temperature grade 1: –40°C to +125°C, TA Functional Safety Quality-Managed Documentation available to aid in functional safety system design Core Arm 32-bit Cortex-M0+ CPU, frequency up to 32 MHz Operating characteristics Wide supply voltage range: 1.62 V to 3.6 V Memories Up to 64KB of flash Up to 4KB of SRAM High-performance analog peripherals One 12-bit 1.68-Msps analog-to-digital converter (ADC) with up to 10 total external channels Configurable 1.4-V or 2.5-V internal ADC voltage reference (VREF) Two zero-drift, zero-crossover chopper operational amplifiers (OPA) 0.5-µV/°C drift with chopping Integrated programmable gain stage (1-32x) One general-purpose amplifier (GPAMP) One high-speed comparator (COMP) with 8-bit reference DAC 32-ns propagation delay Low power mode down to <1-µA Programmable analog connections between ADC, OPAs, COMP, and DAC Integrated temperature sensor Optimized low-power modes RUN: 71 µA/MHz (CoreMark) STOP: 151 µA at 4 MHz and 44 µA at 32 kHz STANDBY: 1.0 µA with 32-kHz 16-bit timer running, SRAM/registers fully retained, and 32MHz clock wakeup in 3.2µs SHUTDOWN: 61 nA with IO wakeup capability Intelligent digital peripherals 3-channel DMA controller 3-channel event fabric signaling system Four 16-bit general-purpose timers, each with two capture/compare registers supporting low-power operation in STANDBY mode, supporting a total of 8 PWM channels Windowed watchdog timer Enhanced communication interfaces Two UART interfaces; one supporting LIN, IrDA, DALI, Smart Card, Manchester and both supporting low-power operation in STANDBY Two I2C interfaces; one supporting FM+ (1 Mbit/s) and both supporting SMBus, PMBus, and wakeup from STOP One SPI supporting up to 16 Mbit/s Clock system Internal 4- to 32-MHz oscillator with ±1.2% accuracy (SYSOSC) Internal 32-kHz low-frequency oscillator with ±3% accuracy (LFOSC) Data integrity Cyclic redundancy checker (CRC-16 or CRC-32) Flexible I/O features Up to 28 GPIOs Two 5-V-tolerant open-drain IOs with fail-safe protection Development support 2-pin serial wire debug (SWD) Package options 32-pin VQFN (RHB) 32-pin VSSOP (DGS) 28-pin VSSOP (DGS) 24-pin VQFN (RGE) 20-pin VSSOP (DGS) 16-pin SOT(DYY) Family members (also see Device Comparison ) MSPM0L1304: 16KB of flash, 2KB of RAM MSPM0L1305: 32KB of flash, 4KB of RAM MSPM0L1306: 64KB of flash, 4KB of RAM Development kits and software (also see Tools and Software ) LP-MSPM0L1306 LaunchPad development kit MSP Software Development Kit (SDK) Features 20231201 Changes throughout document for final device characterization and release as Production Data yes 20231201 Changes throughout document for final device characterization and release as Production Data yes 20231201 Changes throughout document for final device characterization and release as Production Data yes 20231201Changes throughout document for final device characterization and release as Production Datayes AEC-Q100 qualified for automotive applications Temperature grade 1: –40°C to +125°C, TA Functional Safety Quality-Managed Documentation available to aid in functional safety system design Core Arm 32-bit Cortex-M0+ CPU, frequency up to 32 MHz Operating characteristics Wide supply voltage range: 1.62 V to 3.6 V Memories Up to 64KB of flash Up to 4KB of SRAM High-performance analog peripherals One 12-bit 1.68-Msps analog-to-digital converter (ADC) with up to 10 total external channels Configurable 1.4-V or 2.5-V internal ADC voltage reference (VREF) Two zero-drift, zero-crossover chopper operational amplifiers (OPA) 0.5-µV/°C drift with chopping Integrated programmable gain stage (1-32x) One general-purpose amplifier (GPAMP) One high-speed comparator (COMP) with 8-bit reference DAC 32-ns propagation delay Low power mode down to <1-µA Programmable analog connections between ADC, OPAs, COMP, and DAC Integrated temperature sensor Optimized low-power modes RUN: 71 µA/MHz (CoreMark) STOP: 151 µA at 4 MHz and 44 µA at 32 kHz STANDBY: 1.0 µA with 32-kHz 16-bit timer running, SRAM/registers fully retained, and 32MHz clock wakeup in 3.2µs SHUTDOWN: 61 nA with IO wakeup capability Intelligent digital peripherals 3-channel DMA controller 3-channel event fabric signaling system Four 16-bit general-purpose timers, each with two capture/compare registers supporting low-power operation in STANDBY mode, supporting a total of 8 PWM channels Windowed watchdog timer Enhanced communication interfaces Two UART interfaces; one supporting LIN, IrDA, DALI, Smart Card, Manchester and both supporting low-power operation in STANDBY Two I2C interfaces; one supporting FM+ (1 Mbit/s) and both supporting SMBus, PMBus, and wakeup from STOP One SPI supporting up to 16 Mbit/s Clock system Internal 4- to 32-MHz oscillator with ±1.2% accuracy (SYSOSC) Internal 32-kHz low-frequency oscillator with ±3% accuracy (LFOSC) Data integrity Cyclic redundancy checker (CRC-16 or CRC-32) Flexible I/O features Up to 28 GPIOs Two 5-V-tolerant open-drain IOs with fail-safe protection Development support 2-pin serial wire debug (SWD) Package options 32-pin VQFN (RHB) 32-pin VSSOP (DGS) 28-pin VSSOP (DGS) 24-pin VQFN (RGE) 20-pin VSSOP (DGS) 16-pin SOT(DYY) Family members (also see Device Comparison ) MSPM0L1304: 16KB of flash, 2KB of RAM MSPM0L1305: 32KB of flash, 4KB of RAM MSPM0L1306: 64KB of flash, 4KB of RAM Development kits and software (also see Tools and Software ) LP-MSPM0L1306 LaunchPad development kit MSP Software Development Kit (SDK) AEC-Q100 qualified for automotive applications Temperature grade 1: –40°C to +125°C, TA Functional Safety Quality-Managed Documentation available to aid in functional safety system design Core Arm 32-bit Cortex-M0+ CPU, frequency up to 32 MHz Operating characteristics Wide supply voltage range: 1.62 V to 3.6 V Memories Up to 64KB of flash Up to 4KB of SRAM High-performance analog peripherals One 12-bit 1.68-Msps analog-to-digital converter (ADC) with up to 10 total external channels Configurable 1.4-V or 2.5-V internal ADC voltage reference (VREF) Two zero-drift, zero-crossover chopper operational amplifiers (OPA) 0.5-µV/°C drift with chopping Integrated programmable gain stage (1-32x) One general-purpose amplifier (GPAMP) One high-speed comparator (COMP) with 8-bit reference DAC 32-ns propagation delay Low power mode down to <1-µA Programmable analog connections between ADC, OPAs, COMP, and DAC Integrated temperature sensor Optimized low-power modes RUN: 71 µA/MHz (CoreMark) STOP: 151 µA at 4 MHz and 44 µA at 32 kHz STANDBY: 1.0 µA with 32-kHz 16-bit timer running, SRAM/registers fully retained, and 32MHz clock wakeup in 3.2µs SHUTDOWN: 61 nA with IO wakeup capability Intelligent digital peripherals 3-channel DMA controller 3-channel event fabric signaling system Four 16-bit general-purpose timers, each with two capture/compare registers supporting low-power operation in STANDBY mode, supporting a total of 8 PWM channels Windowed watchdog timer Enhanced communication interfaces Two UART interfaces; one supporting LIN, IrDA, DALI, Smart Card, Manchester and both supporting low-power operation in STANDBY Two I2C interfaces; one supporting FM+ (1 Mbit/s) and both supporting SMBus, PMBus, and wakeup from STOP One SPI supporting up to 16 Mbit/s Clock system Internal 4- to 32-MHz oscillator with ±1.2% accuracy (SYSOSC) Internal 32-kHz low-frequency oscillator with ±3% accuracy (LFOSC) Data integrity Cyclic redundancy checker (CRC-16 or CRC-32) Flexible I/O features Up to 28 GPIOs Two 5-V-tolerant open-drain IOs with fail-safe protection Development support 2-pin serial wire debug (SWD) Package options 32-pin VQFN (RHB) 32-pin VSSOP (DGS) 28-pin VSSOP (DGS) 24-pin VQFN (RGE) 20-pin VSSOP (DGS) 16-pin SOT(DYY) Family members (also see Device Comparison ) MSPM0L1304: 16KB of flash, 2KB of RAM MSPM0L1305: 32KB of flash, 4KB of RAM MSPM0L1306: 64KB of flash, 4KB of RAM Development kits and software (also see Tools and Software ) LP-MSPM0L1306 LaunchPad development kit MSP Software Development Kit (SDK) AEC-Q100 qualified for automotive applications Temperature grade 1: –40°C to +125°C, TA Functional Safety Quality-Managed Documentation available to aid in functional safety system design Core Arm 32-bit Cortex-M0+ CPU, frequency up to 32 MHz Operating characteristics Wide supply voltage range: 1.62 V to 3.6 V Memories Up to 64KB of flash Up to 4KB of SRAM High-performance analog peripherals One 12-bit 1.68-Msps analog-to-digital converter (ADC) with up to 10 total external channels Configurable 1.4-V or 2.5-V internal ADC voltage reference (VREF) Two zero-drift, zero-crossover chopper operational amplifiers (OPA) 0.5-µV/°C drift with chopping Integrated programmable gain stage (1-32x) One general-purpose amplifier (GPAMP) One high-speed comparator (COMP) with 8-bit reference DAC 32-ns propagation delay Low power mode down to <1-µA Programmable analog connections between ADC, OPAs, COMP, and DAC Integrated temperature sensor Optimized low-power modes RUN: 71 µA/MHz (CoreMark) STOP: 151 µA at 4 MHz and 44 µA at 32 kHz STANDBY: 1.0 µA with 32-kHz 16-bit timer running, SRAM/registers fully retained, and 32MHz clock wakeup in 3.2µs SHUTDOWN: 61 nA with IO wakeup capability Intelligent digital peripherals 3-channel DMA controller 3-channel event fabric signaling system Four 16-bit general-purpose timers, each with two capture/compare registers supporting low-power operation in STANDBY mode, supporting a total of 8 PWM channels Windowed watchdog timer Enhanced communication interfaces Two UART interfaces; one supporting LIN, IrDA, DALI, Smart Card, Manchester and both supporting low-power operation in STANDBY Two I2C interfaces; one supporting FM+ (1 Mbit/s) and both supporting SMBus, PMBus, and wakeup from STOP One SPI supporting up to 16 Mbit/s Clock system Internal 4- to 32-MHz oscillator with ±1.2% accuracy (SYSOSC) Internal 32-kHz low-frequency oscillator with ±3% accuracy (LFOSC) Data integrity Cyclic redundancy checker (CRC-16 or CRC-32) Flexible I/O features Up to 28 GPIOs Two 5-V-tolerant open-drain IOs with fail-safe protection Development support 2-pin serial wire debug (SWD) Package options 32-pin VQFN (RHB) 32-pin VSSOP (DGS) 28-pin VSSOP (DGS) 24-pin VQFN (RGE) 20-pin VSSOP (DGS) 16-pin SOT(DYY) Family members (also see Device Comparison ) MSPM0L1304: 16KB of flash, 2KB of RAM MSPM0L1305: 32KB of flash, 4KB of RAM MSPM0L1306: 64KB of flash, 4KB of RAM Development kits and software (also see Tools and Software ) LP-MSPM0L1306 LaunchPad development kit MSP Software Development Kit (SDK) AEC-Q100 qualified for automotive applications Temperature grade 1: –40°C to +125°C, TA AEC-Q100 qualified for automotive applications Temperature grade 1: –40°C to +125°C, TA AEC-Q100 qualified for automotive applications Temperature grade 1: –40°C to +125°C, TA Temperature grade 1: –40°C to +125°C, TA A Functional Safety Quality-Managed Documentation available to aid in functional safety system design Functional Safety Quality-Managed Functional Safety Quality-Managed Documentation available to aid in functional safety system design Documentation available to aid in functional safety system design Core Arm 32-bit Cortex-M0+ CPU, frequency up to 32 MHz Core Arm 32-bit Cortex-M0+ CPU, frequency up to 32 MHz Arm 32-bit Cortex-M0+ CPU, frequency up to 32 MHzArmCortex Operating characteristics Wide supply voltage range: 1.62 V to 3.6 V Operating characteristics Wide supply voltage range: 1.62 V to 3.6 V Wide supply voltage range: 1.62 V to 3.6 V Memories Up to 64KB of flash Up to 4KB of SRAM Memories Up to 64KB of flash Up to 4KB of SRAM Up to 64KB of flashUp to 4KB of SRAM High-performance analog peripherals One 12-bit 1.68-Msps analog-to-digital converter (ADC) with up to 10 total external channels Configurable 1.4-V or 2.5-V internal ADC voltage reference (VREF) Two zero-drift, zero-crossover chopper operational amplifiers (OPA) 0.5-µV/°C drift with chopping Integrated programmable gain stage (1-32x) One general-purpose amplifier (GPAMP) One high-speed comparator (COMP) with 8-bit reference DAC 32-ns propagation delay Low power mode down to <1-µA Programmable analog connections between ADC, OPAs, COMP, and DAC Integrated temperature sensor High-performance analog peripherals One 12-bit 1.68-Msps analog-to-digital converter (ADC) with up to 10 total external channels Configurable 1.4-V or 2.5-V internal ADC voltage reference (VREF) Two zero-drift, zero-crossover chopper operational amplifiers (OPA) 0.5-µV/°C drift with chopping Integrated programmable gain stage (1-32x) One general-purpose amplifier (GPAMP) One high-speed comparator (COMP) with 8-bit reference DAC 32-ns propagation delay Low power mode down to <1-µA Programmable analog connections between ADC, OPAs, COMP, and DAC Integrated temperature sensor One 12-bit 1.68-Msps analog-to-digital converter (ADC) with up to 10 total external channelsConfigurable 1.4-V or 2.5-V internal ADC voltage reference (VREF)Two zero-drift, zero-crossover chopper operational amplifiers (OPA) 0.5-µV/°C drift with chopping Integrated programmable gain stage (1-32x) 0.5-µV/°C drift with chopping Integrated programmable gain stage (1-32x) 0.5-µV/°C drift with choppingIntegrated programmable gain stage (1-32x) One general-purpose amplifier (GPAMP)One high-speed comparator (COMP) with 8-bit reference DAC 32-ns propagation delay Low power mode down to <1-µA 32-ns propagation delay Low power mode down to <1-µA 32-ns propagation delayLow power mode down to <1-µAProgrammable analog connections between ADC, OPAs, COMP, and DACIntegrated temperature sensor Optimized low-power modes RUN: 71 µA/MHz (CoreMark) STOP: 151 µA at 4 MHz and 44 µA at 32 kHz STANDBY: 1.0 µA with 32-kHz 16-bit timer running, SRAM/registers fully retained, and 32MHz clock wakeup in 3.2µs SHUTDOWN: 61 nA with IO wakeup capability Optimized low-power modes RUN: 71 µA/MHz (CoreMark) STOP: 151 µA at 4 MHz and 44 µA at 32 kHz STANDBY: 1.0 µA with 32-kHz 16-bit timer running, SRAM/registers fully retained, and 32MHz clock wakeup in 3.2µs SHUTDOWN: 61 nA with IO wakeup capability RUN: 71 µA/MHz (CoreMark)STOP: 151 µA at 4 MHz and 44 µA at 32 kHzSTANDBY: 1.0 µA with 32-kHz 16-bit timer running, SRAM/registers fully retained, and 32MHz clock wakeup in 3.2µsSHUTDOWN: 61 nA with IO wakeup capability Intelligent digital peripherals 3-channel DMA controller 3-channel event fabric signaling system Four 16-bit general-purpose timers, each with two capture/compare registers supporting low-power operation in STANDBY mode, supporting a total of 8 PWM channels Windowed watchdog timer Intelligent digital peripherals 3-channel DMA controller 3-channel event fabric signaling system Four 16-bit general-purpose timers, each with two capture/compare registers supporting low-power operation in STANDBY mode, supporting a total of 8 PWM channels Windowed watchdog timer 3-channel DMA controller3-channel event fabric signaling systemFour 16-bit general-purpose timers, each with two capture/compare registers supporting low-power operation in STANDBY mode, supporting a total of 8 PWM channelsWindowed watchdog timer Enhanced communication interfaces Two UART interfaces; one supporting LIN, IrDA, DALI, Smart Card, Manchester and both supporting low-power operation in STANDBY Two I2C interfaces; one supporting FM+ (1 Mbit/s) and both supporting SMBus, PMBus, and wakeup from STOP One SPI supporting up to 16 Mbit/s Enhanced communication interfaces Two UART interfaces; one supporting LIN, IrDA, DALI, Smart Card, Manchester and both supporting low-power operation in STANDBY Two I2C interfaces; one supporting FM+ (1 Mbit/s) and both supporting SMBus, PMBus, and wakeup from STOP One SPI supporting up to 16 Mbit/s Two UART interfaces; one supporting LIN, IrDA, DALI, Smart Card, Manchester and both supporting low-power operation in STANDBYTwo I2C interfaces; one supporting FM+ (1 Mbit/s) and both supporting SMBus, PMBus, and wakeup from STOP2One SPI supporting up to 16 Mbit/s Clock system Internal 4- to 32-MHz oscillator with ±1.2% accuracy (SYSOSC) Internal 32-kHz low-frequency oscillator with ±3% accuracy (LFOSC) Clock system Internal 4- to 32-MHz oscillator with ±1.2% accuracy (SYSOSC) Internal 32-kHz low-frequency oscillator with ±3% accuracy (LFOSC) Internal 4- to 32-MHz oscillator with ±1.2% accuracy (SYSOSC)Internal 32-kHz low-frequency oscillator with ±3% accuracy (LFOSC) Data integrity Cyclic redundancy checker (CRC-16 or CRC-32) Data integrity Cyclic redundancy checker (CRC-16 or CRC-32) Cyclic redundancy checker (CRC-16 or CRC-32) Flexible I/O features Up to 28 GPIOs Two 5-V-tolerant open-drain IOs with fail-safe protection Flexible I/O features Up to 28 GPIOs Two 5-V-tolerant open-drain IOs with fail-safe protection Up to 28 GPIOsTwo 5-V-tolerant open-drain IOs with fail-safe protection Development support 2-pin serial wire debug (SWD) Development support 2-pin serial wire debug (SWD) 2-pin serial wire debug (SWD) Package options 32-pin VQFN (RHB) 32-pin VSSOP (DGS) 28-pin VSSOP (DGS) 24-pin VQFN (RGE) 20-pin VSSOP (DGS) 16-pin SOT(DYY) Package options 32-pin VQFN (RHB) 32-pin VSSOP (DGS) 28-pin VSSOP (DGS) 24-pin VQFN (RGE) 20-pin VSSOP (DGS) 16-pin SOT(DYY) 32-pin VQFN (RHB)32-pin VSSOP (DGS)28-pin VSSOP (DGS)24-pin VQFN (RGE)20-pin VSSOP (DGS)16-pin SOT(DYY) Family members (also see Device Comparison ) MSPM0L1304: 16KB of flash, 2KB of RAM MSPM0L1305: 32KB of flash, 4KB of RAM MSPM0L1306: 64KB of flash, 4KB of RAM Family members (also see Device Comparison Device Comparison Device Comparison MSPM0L1304: 16KB of flash, 2KB of RAM MSPM0L1305: 32KB of flash, 4KB of RAM MSPM0L1306: 64KB of flash, 4KB of RAM MSPM0L1304: 16KB of flash, 2KB of RAMMSPM0L1305: 32KB of flash, 4KB of RAMMSPM0L1306: 64KB of flash, 4KB of RAM Development kits and software (also see Tools and Software ) LP-MSPM0L1306 LaunchPad development kit MSP Software Development Kit (SDK) Development kits and software Tools and Software Tools and Software LP-MSPM0L1306 LaunchPad development kit MSP Software Development Kit (SDK) LP-MSPM0L1306 LaunchPad development kitLaunchPadMSP Software Development Kit (SDK) Applications Automotive body electronics and Lighting Automotive Gateway Steering Wheel Systems Automotive Motor Control DC to AC Inverters Automotive Interior Lighting Door handle modules Kick to open modules Vehicle Occupancy Detection Seat Comfort Module Applications Automotive body electronics and Lighting Automotive Gateway Steering Wheel Systems Automotive Motor Control DC to AC Inverters Automotive Interior Lighting Door handle modules Kick to open modules Vehicle Occupancy Detection Seat Comfort Module Automotive body electronics and Lighting Automotive Gateway Steering Wheel Systems Automotive Motor Control DC to AC Inverters Automotive Interior Lighting Door handle modules Kick to open modules Vehicle Occupancy Detection Seat Comfort Module Automotive body electronics and Lighting Automotive Gateway Steering Wheel Systems Automotive Motor Control DC to AC Inverters Automotive Interior Lighting Door handle modules Kick to open modules Vehicle Occupancy Detection Seat Comfort Module Automotive body electronics and Lighting Automotive body electronics and Lighting Automotive Gateway Automotive Gateway Steering Wheel Systems Steering Wheel Systems Automotive Motor Control Automotive Motor Control DC to AC Inverters DC to AC Inverters Automotive Interior Lighting Automotive Interior Lighting Door handle modules Door handle modules Kick to open modules Kick to open modules Vehicle Occupancy Detection Vehicle Occupancy Detection Seat Comfort Module Seat Comfort Module Description MSPM0L130x microcontrollers (MCUs) are part of the MSP highly-integrated, ultra-low-power 32-bit MSPM0 MCU family based on the enhanced Arm Cortex-M0+ core platform operating at up to 32-MHz frequency. These cost-optimized MCUs offer high-performance analog peripheral integration, support extended temperature ranges from -40°C to 125°C, and operate with supply voltages ranging from 1.62 V to 3.6 V. The MSPM0L130x devices provide up to 64KB embedded flash program memory with up to 4KB SRAM. These MCUs incorporate a high-speed on-chip oscillator with an accuracy up to ±1.2%, eliminating the need for an external crystal. Additional features include a 3-channel DMA, 16- and 32-bit CRC accelerator, and a variety of high-performance analog peripherals such as one 12-bit 1.68-MSPS ADC with configurable internal voltage reference, one high-speed comparator with built-in reference DAC, two zero-drift zero-crossover operational amplifiers with programmable gain, one general-purpose amplifier, and an on-chip temperature sensor. These devices also offer intelligent digital peripherals such as four 16-bit general purpose timers, one windowed watchdog timer, and a variety of communication peripherals including two UARTs, one SPI, and two I2Cs. These communication peripherals offer protocol support for LIN, IrDA, DALI, Manchester, Smart Card, SMBus, and PMBus. The TI MSPM0 family of low-power MCUs consists of devices with varying degrees of analog and digital integration allowing for customers find the MCU that meets their project's needs. The architecture combined with extensive low-power modes are optimized to achieve extended battery life in portable measurement applications. MSPM0L130x MCUs are supported by an extensive hardware and software ecosystem with reference designs and code examples to get the design started quickly. Development kits include a LaunchPad development kit available for purchase and design files for a target-socket board. TI also provides a free MSP Software Development Kit (SDK), which is available as a component of Code Composer Studio IDE desktop and cloud version within the TI Resource Explorer. MSPM0 MCUs are also supported by extensive online collateral, training with MSP Academy, and online support through the TI E2E support forums. For complete module descriptions, see the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . System-level ESD protection must be applied in compliance with the device-level ESD specification to prevent electrical overstress or disturbing of data or code memory. See MSP430™ System-Level ESD Considerations for more information; the principles in this application note are applicable to MSPM0 MCUs. Description MSPM0L130x microcontrollers (MCUs) are part of the MSP highly-integrated, ultra-low-power 32-bit MSPM0 MCU family based on the enhanced Arm Cortex-M0+ core platform operating at up to 32-MHz frequency. These cost-optimized MCUs offer high-performance analog peripheral integration, support extended temperature ranges from -40°C to 125°C, and operate with supply voltages ranging from 1.62 V to 3.6 V. The MSPM0L130x devices provide up to 64KB embedded flash program memory with up to 4KB SRAM. These MCUs incorporate a high-speed on-chip oscillator with an accuracy up to ±1.2%, eliminating the need for an external crystal. Additional features include a 3-channel DMA, 16- and 32-bit CRC accelerator, and a variety of high-performance analog peripherals such as one 12-bit 1.68-MSPS ADC with configurable internal voltage reference, one high-speed comparator with built-in reference DAC, two zero-drift zero-crossover operational amplifiers with programmable gain, one general-purpose amplifier, and an on-chip temperature sensor. These devices also offer intelligent digital peripherals such as four 16-bit general purpose timers, one windowed watchdog timer, and a variety of communication peripherals including two UARTs, one SPI, and two I2Cs. These communication peripherals offer protocol support for LIN, IrDA, DALI, Manchester, Smart Card, SMBus, and PMBus. The TI MSPM0 family of low-power MCUs consists of devices with varying degrees of analog and digital integration allowing for customers find the MCU that meets their project's needs. The architecture combined with extensive low-power modes are optimized to achieve extended battery life in portable measurement applications. MSPM0L130x MCUs are supported by an extensive hardware and software ecosystem with reference designs and code examples to get the design started quickly. Development kits include a LaunchPad development kit available for purchase and design files for a target-socket board. TI also provides a free MSP Software Development Kit (SDK), which is available as a component of Code Composer Studio IDE desktop and cloud version within the TI Resource Explorer. MSPM0 MCUs are also supported by extensive online collateral, training with MSP Academy, and online support through the TI E2E support forums. For complete module descriptions, see the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . System-level ESD protection must be applied in compliance with the device-level ESD specification to prevent electrical overstress or disturbing of data or code memory. See MSP430™ System-Level ESD Considerations for more information; the principles in this application note are applicable to MSPM0 MCUs. MSPM0L130x microcontrollers (MCUs) are part of the MSP highly-integrated, ultra-low-power 32-bit MSPM0 MCU family based on the enhanced Arm Cortex-M0+ core platform operating at up to 32-MHz frequency. These cost-optimized MCUs offer high-performance analog peripheral integration, support extended temperature ranges from -40°C to 125°C, and operate with supply voltages ranging from 1.62 V to 3.6 V. The MSPM0L130x devices provide up to 64KB embedded flash program memory with up to 4KB SRAM. These MCUs incorporate a high-speed on-chip oscillator with an accuracy up to ±1.2%, eliminating the need for an external crystal. Additional features include a 3-channel DMA, 16- and 32-bit CRC accelerator, and a variety of high-performance analog peripherals such as one 12-bit 1.68-MSPS ADC with configurable internal voltage reference, one high-speed comparator with built-in reference DAC, two zero-drift zero-crossover operational amplifiers with programmable gain, one general-purpose amplifier, and an on-chip temperature sensor. These devices also offer intelligent digital peripherals such as four 16-bit general purpose timers, one windowed watchdog timer, and a variety of communication peripherals including two UARTs, one SPI, and two I2Cs. These communication peripherals offer protocol support for LIN, IrDA, DALI, Manchester, Smart Card, SMBus, and PMBus. The TI MSPM0 family of low-power MCUs consists of devices with varying degrees of analog and digital integration allowing for customers find the MCU that meets their project's needs. The architecture combined with extensive low-power modes are optimized to achieve extended battery life in portable measurement applications. MSPM0L130x MCUs are supported by an extensive hardware and software ecosystem with reference designs and code examples to get the design started quickly. Development kits include a LaunchPad development kit available for purchase and design files for a target-socket board. TI also provides a free MSP Software Development Kit (SDK), which is available as a component of Code Composer Studio IDE desktop and cloud version within the TI Resource Explorer. MSPM0 MCUs are also supported by extensive online collateral, training with MSP Academy, and online support through the TI E2E support forums. For complete module descriptions, see the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . System-level ESD protection must be applied in compliance with the device-level ESD specification to prevent electrical overstress or disturbing of data or code memory. See MSP430™ System-Level ESD Considerations for more information; the principles in this application note are applicable to MSPM0 MCUs. MSPM0L130x microcontrollers (MCUs) are part of the MSP highly-integrated, ultra-low-power 32-bit MSPM0 MCU family based on the enhanced Arm Cortex-M0+ core platform operating at up to 32-MHz frequency. These cost-optimized MCUs offer high-performance analog peripheral integration, support extended temperature ranges from -40°C to 125°C, and operate with supply voltages ranging from 1.62 V to 3.6 V.32-bit MSPM0 MCU familyArmCortexThe MSPM0L130x devices provide up to 64KB embedded flash program memory with up to 4KB SRAM. These MCUs incorporate a high-speed on-chip oscillator with an accuracy up to ±1.2%, eliminating the need for an external crystal. Additional features include a 3-channel DMA, 16- and 32-bit CRC accelerator, and a variety of high-performance analog peripherals such as one 12-bit 1.68-MSPS ADC with configurable internal voltage reference, one high-speed comparator with built-in reference DAC, two zero-drift zero-crossover operational amplifiers with programmable gain, one general-purpose amplifier, and an on-chip temperature sensor. These devices also offer intelligent digital peripherals such as four 16-bit general purpose timers, one windowed watchdog timer, and a variety of communication peripherals including two UARTs, one SPI, and two I2Cs. These communication peripherals offer protocol support for LIN, IrDA, DALI, Manchester, Smart Card, SMBus, and PMBus.2The TI MSPM0 family of low-power MCUs consists of devices with varying degrees of analog and digital integration allowing for customers find the MCU that meets their project's needs. The architecture combined with extensive low-power modes are optimized to achieve extended battery life in portable measurement applications.MSPM0L130x MCUs are supported by an extensive hardware and software ecosystem with reference designs and code examples to get the design started quickly. Development kits include a LaunchPad development kit available for purchase and design files for a target-socket board. TI also provides a free MSP Software Development Kit (SDK), which is available as a component of Code Composer Studio IDE desktop and cloud version within the TI Resource Explorer. MSPM0 MCUs are also supported by extensive online collateral, training with MSP Academy, and online support through the TI E2E support forums.LaunchPad Code Composer Studio IDECode Composer StudioTI Resource ExplorerMSP Academy TI E2E support forumsTI E2EFor complete module descriptions, see the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual System-level ESD protection must be applied in compliance with the device-level ESD specification to prevent electrical overstress or disturbing of data or code memory. See MSP430™ System-Level ESD Considerations for more information; the principles in this application note are applicable to MSPM0 MCUs. System-level ESD protection must be applied in compliance with the device-level ESD specification to prevent electrical overstress or disturbing of data or code memory. See MSP430™ System-Level ESD Considerations for more information; the principles in this application note are applicable to MSPM0 MCUs.MSP430™ System-Level ESD Considerations Functional Block Diagram MSPM0L130x Functional Block Diagram Functional Block Diagram MSPM0L130x Functional Block Diagram MSPM0L130x Functional Block Diagram MSPM0L130x Functional Block Diagram MSPM0L130x Functional Block Diagram Table of Contents yes 2 Table of Contents yes 2 yes 2 yes2 Device Comparison Device Comparison DEVICE NAME #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/GUID-D866DC36-46EA-49E7-83E5-B28D78EA2E6B #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC FLASH / SRAM (KB) QUAL#GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/QUAL_NOTE ADC CH. COMP OPA GPAMP UART/I2C/SPI TIMG GPIOs 5-V TOL. IO PACKAGE [PACKAGE SIZE] #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/LI_JYL_KYV_WLB M0L1306QRHBQ1 64 / 4 Q 10 1 2 1 2 / 2 / 1 4 28 2 32 VQFN[5 mm × 5 mm] #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/WETTABLE_FLANK_NOTE M0L1305QRHBQ1 32 / 4 M0L1304QRHBQ1 16 / 2 M0L1306QDGS32Q1 64 / 4 Q 10 1 2 1 2 / 2 / 1 4 28 2 32 VSSOP[8.1 mm × 4.9 mm] M0L1305QDGS32Q1 32 / 4 M0L1304QDGS32Q1 16 / 2 M0L1306QDGS28Q1 64 / 4 Q 10 1 2 1 2 / 2 / 1 4 24 2 28 VSSOP[7.1 mm × 4.9 mm] M0L1305QDGS28Q1 32 / 4 M0L1304QDGS28Q1 16 / 2 M0L1306QRGEQ1 64 / 4 Q 9 1 2 1 2 / 2 / 1 4 20 2 24 VQFN[4 mm × 4 mm]#GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/WETTABLE_FLANK_NOTE M0L1305QRGEQ1 32 / 4 M0L1304QRGEQ1 16 / 2 M0L1306QDGS20Q1 64 / 4 Q 8 1 2 1 2 / 2 / 1 4 17 2 20 VSSOP[5.1 mm × 4.9 mm] M0L1305QDGS20Q1 32 / 4 M0L1304QDGS20Q1 16 / 2 M0L1306QDYYQ1 64 / 4 Q 6 1 2 1 2 / 2 / 1 4 13 2 16 SOT[4.2 mm × 2 mm] M0L1305QDYYQ1 32 / 4 M0L1304QDYYQ1 16 / 2 For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in , or see the TI website. For more information about the device name, see . Device qualifications: Q = –40°C to 125°C The package size (length × width) is a nominal value and includes pins, where applicable. For the package dimensions with tolerances, see the Mechanical Data in . The 24 and 32-pin VQFN package is available with wettable flanks. Device Comparison Device Comparison DEVICE NAME #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/GUID-D866DC36-46EA-49E7-83E5-B28D78EA2E6B #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC FLASH / SRAM (KB) QUAL#GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/QUAL_NOTE ADC CH. COMP OPA GPAMP UART/I2C/SPI TIMG GPIOs 5-V TOL. IO PACKAGE [PACKAGE SIZE] #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/LI_JYL_KYV_WLB M0L1306QRHBQ1 64 / 4 Q 10 1 2 1 2 / 2 / 1 4 28 2 32 VQFN[5 mm × 5 mm] #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/WETTABLE_FLANK_NOTE M0L1305QRHBQ1 32 / 4 M0L1304QRHBQ1 16 / 2 M0L1306QDGS32Q1 64 / 4 Q 10 1 2 1 2 / 2 / 1 4 28 2 32 VSSOP[8.1 mm × 4.9 mm] M0L1305QDGS32Q1 32 / 4 M0L1304QDGS32Q1 16 / 2 M0L1306QDGS28Q1 64 / 4 Q 10 1 2 1 2 / 2 / 1 4 24 2 28 VSSOP[7.1 mm × 4.9 mm] M0L1305QDGS28Q1 32 / 4 M0L1304QDGS28Q1 16 / 2 M0L1306QRGEQ1 64 / 4 Q 9 1 2 1 2 / 2 / 1 4 20 2 24 VQFN[4 mm × 4 mm]#GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/WETTABLE_FLANK_NOTE M0L1305QRGEQ1 32 / 4 M0L1304QRGEQ1 16 / 2 M0L1306QDGS20Q1 64 / 4 Q 8 1 2 1 2 / 2 / 1 4 17 2 20 VSSOP[5.1 mm × 4.9 mm] M0L1305QDGS20Q1 32 / 4 M0L1304QDGS20Q1 16 / 2 M0L1306QDYYQ1 64 / 4 Q 6 1 2 1 2 / 2 / 1 4 13 2 16 SOT[4.2 mm × 2 mm] M0L1305QDYYQ1 32 / 4 M0L1304QDYYQ1 16 / 2 For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in , or see the TI website. For more information about the device name, see . Device qualifications: Q = –40°C to 125°C The package size (length × width) is a nominal value and includes pins, where applicable. For the package dimensions with tolerances, see the Mechanical Data in . The 24 and 32-pin VQFN package is available with wettable flanks. Device Comparison DEVICE NAME #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/GUID-D866DC36-46EA-49E7-83E5-B28D78EA2E6B #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC FLASH / SRAM (KB) QUAL#GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/QUAL_NOTE ADC CH. COMP OPA GPAMP UART/I2C/SPI TIMG GPIOs 5-V TOL. IO PACKAGE [PACKAGE SIZE] #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/LI_JYL_KYV_WLB M0L1306QRHBQ1 64 / 4 Q 10 1 2 1 2 / 2 / 1 4 28 2 32 VQFN[5 mm × 5 mm] #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/WETTABLE_FLANK_NOTE M0L1305QRHBQ1 32 / 4 M0L1304QRHBQ1 16 / 2 M0L1306QDGS32Q1 64 / 4 Q 10 1 2 1 2 / 2 / 1 4 28 2 32 VSSOP[8.1 mm × 4.9 mm] M0L1305QDGS32Q1 32 / 4 M0L1304QDGS32Q1 16 / 2 M0L1306QDGS28Q1 64 / 4 Q 10 1 2 1 2 / 2 / 1 4 24 2 28 VSSOP[7.1 mm × 4.9 mm] M0L1305QDGS28Q1 32 / 4 M0L1304QDGS28Q1 16 / 2 M0L1306QRGEQ1 64 / 4 Q 9 1 2 1 2 / 2 / 1 4 20 2 24 VQFN[4 mm × 4 mm]#GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/WETTABLE_FLANK_NOTE M0L1305QRGEQ1 32 / 4 M0L1304QRGEQ1 16 / 2 M0L1306QDGS20Q1 64 / 4 Q 8 1 2 1 2 / 2 / 1 4 17 2 20 VSSOP[5.1 mm × 4.9 mm] M0L1305QDGS20Q1 32 / 4 M0L1304QDGS20Q1 16 / 2 M0L1306QDYYQ1 64 / 4 Q 6 1 2 1 2 / 2 / 1 4 13 2 16 SOT[4.2 mm × 2 mm] M0L1305QDYYQ1 32 / 4 M0L1304QDYYQ1 16 / 2 For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in , or see the TI website. For more information about the device name, see . Device qualifications: Q = –40°C to 125°C The package size (length × width) is a nominal value and includes pins, where applicable. For the package dimensions with tolerances, see the Mechanical Data in . The 24 and 32-pin VQFN package is available with wettable flanks. Device Comparison DEVICE NAME #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/GUID-D866DC36-46EA-49E7-83E5-B28D78EA2E6B #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC FLASH / SRAM (KB) QUAL#GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/QUAL_NOTE ADC CH. COMP OPA GPAMP UART/I2C/SPI TIMG GPIOs 5-V TOL. IO PACKAGE [PACKAGE SIZE] #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/LI_JYL_KYV_WLB M0L1306QRHBQ1 64 / 4 Q 10 1 2 1 2 / 2 / 1 4 28 2 32 VQFN[5 mm × 5 mm] #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/WETTABLE_FLANK_NOTE M0L1305QRHBQ1 32 / 4 M0L1304QRHBQ1 16 / 2 M0L1306QDGS32Q1 64 / 4 Q 10 1 2 1 2 / 2 / 1 4 28 2 32 VSSOP[8.1 mm × 4.9 mm] M0L1305QDGS32Q1 32 / 4 M0L1304QDGS32Q1 16 / 2 M0L1306QDGS28Q1 64 / 4 Q 10 1 2 1 2 / 2 / 1 4 24 2 28 VSSOP[7.1 mm × 4.9 mm] M0L1305QDGS28Q1 32 / 4 M0L1304QDGS28Q1 16 / 2 M0L1306QRGEQ1 64 / 4 Q 9 1 2 1 2 / 2 / 1 4 20 2 24 VQFN[4 mm × 4 mm]#GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/WETTABLE_FLANK_NOTE M0L1305QRGEQ1 32 / 4 M0L1304QRGEQ1 16 / 2 M0L1306QDGS20Q1 64 / 4 Q 8 1 2 1 2 / 2 / 1 4 17 2 20 VSSOP[5.1 mm × 4.9 mm] M0L1305QDGS20Q1 32 / 4 M0L1304QDGS20Q1 16 / 2 M0L1306QDYYQ1 64 / 4 Q 6 1 2 1 2 / 2 / 1 4 13 2 16 SOT[4.2 mm × 2 mm] M0L1305QDYYQ1 32 / 4 M0L1304QDYYQ1 16 / 2 Device Comparison DEVICE NAME #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/GUID-D866DC36-46EA-49E7-83E5-B28D78EA2E6B #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC FLASH / SRAM (KB) QUAL#GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/QUAL_NOTE ADC CH. COMP OPA GPAMP UART/I2C/SPI TIMG GPIOs 5-V TOL. IO PACKAGE [PACKAGE SIZE] #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/LI_JYL_KYV_WLB M0L1306QRHBQ1 64 / 4 Q 10 1 2 1 2 / 2 / 1 4 28 2 32 VQFN[5 mm × 5 mm] #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/WETTABLE_FLANK_NOTE M0L1305QRHBQ1 32 / 4 M0L1304QRHBQ1 16 / 2 M0L1306QDGS32Q1 64 / 4 Q 10 1 2 1 2 / 2 / 1 4 28 2 32 VSSOP[8.1 mm × 4.9 mm] M0L1305QDGS32Q1 32 / 4 M0L1304QDGS32Q1 16 / 2 M0L1306QDGS28Q1 64 / 4 Q 10 1 2 1 2 / 2 / 1 4 24 2 28 VSSOP[7.1 mm × 4.9 mm] M0L1305QDGS28Q1 32 / 4 M0L1304QDGS28Q1 16 / 2 M0L1306QRGEQ1 64 / 4 Q 9 1 2 1 2 / 2 / 1 4 20 2 24 VQFN[4 mm × 4 mm]#GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/WETTABLE_FLANK_NOTE M0L1305QRGEQ1 32 / 4 M0L1304QRGEQ1 16 / 2 M0L1306QDGS20Q1 64 / 4 Q 8 1 2 1 2 / 2 / 1 4 17 2 20 VSSOP[5.1 mm × 4.9 mm] M0L1305QDGS20Q1 32 / 4 M0L1304QDGS20Q1 16 / 2 M0L1306QDYYQ1 64 / 4 Q 6 1 2 1 2 / 2 / 1 4 13 2 16 SOT[4.2 mm × 2 mm] M0L1305QDYYQ1 32 / 4 M0L1304QDYYQ1 16 / 2 DEVICE NAME #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/GUID-D866DC36-46EA-49E7-83E5-B28D78EA2E6B #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC FLASH / SRAM (KB) QUAL#GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/QUAL_NOTE ADC CH. COMP OPA GPAMP UART/I2C/SPI TIMG GPIOs 5-V TOL. IO PACKAGE [PACKAGE SIZE] #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/LI_JYL_KYV_WLB DEVICE NAME #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/GUID-D866DC36-46EA-49E7-83E5-B28D78EA2E6B #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC FLASH / SRAM (KB) QUAL#GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/QUAL_NOTE ADC CH. COMP OPA GPAMP UART/I2C/SPI TIMG GPIOs 5-V TOL. IO PACKAGE [PACKAGE SIZE] #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/LI_JYL_KYV_WLB DEVICE NAME #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/GUID-D866DC36-46EA-49E7-83E5-B28D78EA2E6B #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/GUID-D866DC36-46EA-49E7-83E5-B28D78EA2E6B#GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACCFLASH / SRAM (KB)QUAL#GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/QUAL_NOTE #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/QUAL_NOTEADC CH.COMPOPAGPAMPUART/I2C/SPITIMGGPIOs5-V TOL. IOPACKAGE [PACKAGE SIZE] #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/LI_JYL_KYV_WLB #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/LI_JYL_KYV_WLB M0L1306QRHBQ1 64 / 4 Q 10 1 2 1 2 / 2 / 1 4 28 2 32 VQFN[5 mm × 5 mm] #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/WETTABLE_FLANK_NOTE M0L1305QRHBQ1 32 / 4 M0L1304QRHBQ1 16 / 2 M0L1306QDGS32Q1 64 / 4 Q 10 1 2 1 2 / 2 / 1 4 28 2 32 VSSOP[8.1 mm × 4.9 mm] M0L1305QDGS32Q1 32 / 4 M0L1304QDGS32Q1 16 / 2 M0L1306QDGS28Q1 64 / 4 Q 10 1 2 1 2 / 2 / 1 4 24 2 28 VSSOP[7.1 mm × 4.9 mm] M0L1305QDGS28Q1 32 / 4 M0L1304QDGS28Q1 16 / 2 M0L1306QRGEQ1 64 / 4 Q 9 1 2 1 2 / 2 / 1 4 20 2 24 VQFN[4 mm × 4 mm]#GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/WETTABLE_FLANK_NOTE M0L1305QRGEQ1 32 / 4 M0L1304QRGEQ1 16 / 2 M0L1306QDGS20Q1 64 / 4 Q 8 1 2 1 2 / 2 / 1 4 17 2 20 VSSOP[5.1 mm × 4.9 mm] M0L1305QDGS20Q1 32 / 4 M0L1304QDGS20Q1 16 / 2 M0L1306QDYYQ1 64 / 4 Q 6 1 2 1 2 / 2 / 1 4 13 2 16 SOT[4.2 mm × 2 mm] M0L1305QDYYQ1 32 / 4 M0L1304QDYYQ1 16 / 2 M0L1306QRHBQ1 64 / 4 Q 10 1 2 1 2 / 2 / 1 4 28 2 32 VQFN[5 mm × 5 mm] #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/WETTABLE_FLANK_NOTE M0L1306QRHBQ164 / 4Q101212 / 2 / 1428232 VQFN[5 mm × 5 mm] #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/WETTABLE_FLANK_NOTE #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/WETTABLE_FLANK_NOTE M0L1305QRHBQ1 32 / 4 M0L1305QRHBQ132 / 4 M0L1304QRHBQ1 16 / 2 M0L1304QRHBQ116 / 2 M0L1306QDGS32Q1 64 / 4 Q 10 1 2 1 2 / 2 / 1 4 28 2 32 VSSOP[8.1 mm × 4.9 mm] M0L1306QDGS32Q164 / 4Q101212 / 2 / 1428232 VSSOP[8.1 mm × 4.9 mm] M0L1305QDGS32Q1 32 / 4 M0L1305QDGS32Q132 / 4 M0L1304QDGS32Q1 16 / 2 M0L1304QDGS32Q116 / 2 M0L1306QDGS28Q1 64 / 4 Q 10 1 2 1 2 / 2 / 1 4 24 2 28 VSSOP[7.1 mm × 4.9 mm] M0L1306QDGS28Q164 / 4Q101212 / 2 / 1424228 VSSOP[7.1 mm × 4.9 mm] M0L1305QDGS28Q1 32 / 4 M0L1305QDGS28Q132 / 4 M0L1304QDGS28Q1 16 / 2 M0L1304QDGS28Q116 / 2 M0L1306QRGEQ1 64 / 4 Q 9 1 2 1 2 / 2 / 1 4 20 2 24 VQFN[4 mm × 4 mm]#GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/WETTABLE_FLANK_NOTE M0L1306QRGEQ1 64 / 4 64 / 4Q91212 / 2 / 1420224 VQFN[4 mm × 4 mm]#GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/WETTABLE_FLANK_NOTE #GUID-C1DADA5B-9E8C-44EF-A7C5-E24BA0020449/WETTABLE_FLANK_NOTE M0L1305QRGEQ1 32 / 4 M0L1305QRGEQ1 32 / 4 32 / 4 M0L1304QRGEQ1 16 / 2 M0L1304QRGEQ1 16 / 2 16 / 2 M0L1306QDGS20Q1 64 / 4 Q 8 1 2 1 2 / 2 / 1 4 17 2 20 VSSOP[5.1 mm × 4.9 mm] M0L1306QDGS20Q164 / 4Q81212 / 2 / 1417220 VSSOP[5.1 mm × 4.9 mm] M0L1305QDGS20Q1 32 / 4 M0L1305QDGS20Q132 / 4 M0L1304QDGS20Q1 16 / 2 M0L1304QDGS20Q116 / 2 M0L1306QDYYQ1 64 / 4 Q 6 1 2 1 2 / 2 / 1 4 13 2 16 SOT[4.2 mm × 2 mm] M0L1306QDYYQ164 / 4Q61212 / 2 / 1413216 SOT[4.2 mm × 2 mm] M0L1305QDYYQ1 32 / 4 M0L1305QDYYQ132 / 4 M0L1304QDYYQ1 16 / 2 M0L1304QDYYQ116 / 2 For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in , or see the TI website. For more information about the device name, see . Device qualifications: Q = –40°C to 125°C The package size (length × width) is a nominal value and includes pins, where applicable. For the package dimensions with tolerances, see the Mechanical Data in . The 24 and 32-pin VQFN package is available with wettable flanks. For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in , or see the TI website.Package Option AddendumTI websiteFor more information about the device name, see .Device qualifications: Q = –40°C to 125°C Q = –40°C to 125°C Q = –40°C to 125°CThe package size (length × width) is a nominal value and includes pins, where applicable. For the package dimensions with tolerances, see the Mechanical Data in .Mechanical DataThe 24 and 32-pin VQFN package is available with wettable flanks. Pin Configuration and Functions Pin Diagrams Pin Diagram Color Coding 32-Pin RHB (VQFN) (Top View) - MSPM0L130x 28-Pin DGS28 (VSSOP) (Top View) - MSPM0L130x 24-Pin (VQFN) (Top View) -MSPM0L130x 32-Pin DGS32 (VSSOP) (Top View) - MSPM0L130x 20-Pin DGS20 (VSSOP) (Top View) - MSPM0L130x 16-Pin DYY (SOT) (Top View) - MSPM0L130x Pin Attributes The following table describes the functions available on every pin for each device package. Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) which allows users to configure the desired Pin Function using the PINCM.PF control bits. Pin Attributes PINCMx PIN NAME PIN FUNCTION PIN NUMBER I/O STRUCTURE ANALOG DIGITAL #GUID-F607BEFA-DC51-4A50-87E6-B32520DEC1E0/PIN_ATTR_NOTE_IO 32 VQFN 32 VSSOP 28 VSSOP 24 VQFN 20 VSSOP 16 SOT N/A N/A VDD 4 7 7 3 6 5 Power N/A N/A VSS 5 8 8 4 7 6 Power N/A N/A VCORE 32 3 3 23 3 2 Power 1 PA0 UART1_TX [1] / I2C0_SDA [2] / TIMG1_C0 [3] / SPI0_CS1 [4] (Default BSL I2C_SDA) 1 4 4 24 4 3 5-V tolerant Open-Drain 2 PA1 UART1_RX [1] / I2C0_SCL [2] / TIMG1_C1 [3] (Default BSL I2C_SCL) 2 5 5 1 5 4 5-V tolerant Open-Drain N/A N/A NRST 3 6 6 2 Reset#GUID-F607BEFA-DC51-4A50-87E6-B32520DEC1E0/GUID-C018AFE4-DE14-4A92-AD78-BDA7F2CD490A 3 PA2 ROSC TIMG1_C1 [1] / SPI0_CS0 [2] 6 9 9 5 8 7 Standard 4 PA3 TIMG2_C0 [1] / SPI0_CS1 [2] / UART1_CTS [3] / COMP0_OUT [4] 7 10 10 6 – – Standard 5 PA4 TIMG2_C1 [1] / SPI0_POCI [2] / UART1_RTS [3] 8 11 11 7 9 – Standard 6 PA5 TIMG0_C0 [1] / SPI0_PICO [2] 9 12 12 – – – High-Speed 7 PA6 TIMG0_C1 [1] / SPI0_SCK [2] 10 13 13 – 10 8 Standard 8 PA7 COMP0_OUT [1] / CLK_OUT [2] / TIMG1_C0 [3] 11 14 – – – – Standard 9 PA8 UART0_TX [1] / SPI0_CS0 [2] / UART1_RTS [3] / TIMG2_C0 [4] 12 15 – – – – Standard 10 PA9 UART0_RX [1] / SPI0_PICO [2] / UART1_CTS [3] / TIMG2_C1 [4] 13 16 14 8 – – Standard 11 PA10 UART1_TX [1] / SPI0_POCI [2] / I2C0_SDA [3] / TIMG4_C0 [4] 14 17 15 9 – – High-Speed 12 PA11 UART1_RX [1] / SPI0_SCK [2] / I2C0_SCL [3] / TIMG4_C1 [4] / COMP0_OUT [5] 15 18 16 10 11 – Standard 13 PA12 UART0_CTS [1] / TIMG0_C0 [2] 16 19 – – – – Standard 14 PA13 UART0_RTS [1] / TIMG0_C1 [2] / UART1_RX [3] 17 20 – – – – Standard 15 PA14 UART1_CTS [1] / CLK_OUT [2] / UART1_TX [3] / TIMG1_C0 [4] 18 21 17 – – – Standard 16 PA15 A9 UART1_RTS [1] / I2C1_SCL [2] / SPI0_CS2 [3] / TIMG4_C1 [4] 19 22 18 11 – – Standard 17 PA16 A8 / OPA1_OUT COMP0_OUT [1] / I2C1_SDA [2] / SPI0_POCI [3] / TIMG0_C0 [4] 20 23 19 12 12 – Standard 18 PA17 OPA1_IN1- UART0_TX [1] / I2C1_SCL [2] / SPI0_SCK [3] / TIMG4_C0 [4] / SPI0_CS1 [5] 21 24 20 13 13 9 Standard with wake N/A OPA1_IN0- N/A N/A OPA1_IN0- – – – – 13 – Analog 19 PA18 A7 / OPA1_IN0+ / GPAMP_IN- UART0_RX [1] / SPI0_PICO [2] / I2C1_SDA [3] / TIMG4_C1 [4] (BSL Invoke) 22 25 21 14 14 10 Standard with wake 20 PA19 SWDIO [1] / I2C1_SDA [2] / SPI0_POCI [3] 23 26 22 15 15 11 High-Speed 21 PA20 A6 / COMP0_IN1+ SWCLK [1] / I2C1_SCL [2] / TIMG4_C0 [3] 24 27 23 16 16 12 Standard 22 PA21 A5 / VREF- TIMG2_C0 [1] / UART0_CTS [2] / UART0_TX [3] 25 28 24 17 – – Standard 23 PA22 A4 / GPAMP_OUT / OPA0_OUT UART0_RX [1] / TIMG2_C1 [2] / UART0_RTS [3] / CLK_OUT [4] / UART1_RX [5] (Default BSL UART_RX) 26 29 25 18 17 13 Standard 24 PA23 VREF+ / COMP0_IN1- UART0_TX [1] / SPI0_CS3 [2] / TIMG0_C0 [3] / UART0_CTS [4] / UART1_TX [5] (Default BSL UART_TX) 27 30 26 19 18 14 Standard 25 PA24 A3 / OPA0_IN1- / OPA0_IN0- SPI0_CS2 [1] / TIMG0_C1 [2] / UART0_RTS [3] 28 31 27 20 19 15 Standard N/A N/A OPA0_IN0- – – – – 19 – Analog 26 PA25 A2 / OPA0_IN0+ TIMG4_C1 [1] / UART0_TX [2] / SPI0_PICO [3] 29 32 28 21 20 16 Standard 27 PA26 A1 / GPAMP_IN+ / COMP0_IN0+ TIMG1_C0 [1] / UART0_RX [2] / SPI0_POCI [3] 30 1 1 22 1 1 Standard 28 PA27 A0 / COMP0_IN0- TIMG1_C1 [1] / SPI0_CS3 [2] 31 2 2 – 2 – Standard PINCM.PF and PINCM.PC in IOMUX must be set to 0 for analog functions (for example, OPA inputs or outputs or COMP inputs). Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) which lets software configure the desired Pin Function using the PINCM.PF control bits. Reset PIN is muxed with PA1 for 16-pin and 20-pin devices. Digital IO Features by IO Type IO STRUCTURE INVERSION CONTROL DRIVE STRENGTH CONTROL HYSTERESIS CONTROL PULLUP RESISTOR PULLDOWN RESISTOR WAKEUP LOGIC Standard drive Y Y Y Standard drive with wake Y Y Y Y High speed Y Y Y Y 5-V tolerant open drain Y Y Y Y Signal Descriptions Signal Descriptions FUNCTION SIGNAL NAME PIN NO.#GUID-3211147C-D305-4A41-84DB-091604D3C64A/SLASE5491385467 PIN TYPE #GUID-3211147C-D305-4A41-84DB-091604D3C64A/SLAS5525442 DESCRIPTION 32 VQFN 32 VSSOP 28 VSSOP 24 VQFN 20 VSSOP 16 SOT ADC A0 31 2 2 – 2 – I ADC0 analog input 0 A1 30 1 1 22 1 1 I ADC0 analog input 1 A2 29 32 28 21 20 16 I ADC0 analog input 2 A3 28 31 27 20 19 15 I ADC0 analog input 3 A4 26 29 25 18 17 13 I ADC0 analog input 4 A5 25 28 24 17 – – I ADC0 analog input 5 A6 24 27 23 16 16 12 I ADC0 analog input 6 A7 22 25 21 14 14 10 I ADC0 analog input 7 A8 20 23 19 12 12 – I ADC0 analog input 8 A9 19 22 18 11 – – I ADC0 analog input 9 BSL BSL_invoke 22 25 21 14 14 10 I Input pin used to invoke bootloader BSL (I2C) BSLSCL 2 5 5 1 5 4 I/O Default I2C BSL clock BSLSDA 1 4 4 24 4 3 I/O Default I2C BSL data BSL (UART) BSLRX 26 29 25 18 17 13 I Default UART BSL receive BSLTX 27 30 26 19 18 14 O Default UART BSL transmit Clock CLK_OUT 11 1826 14 16172129 17 25 8918 17 13 O Configurable clock output ROSC 6 9 9 5 8 7 I External resistor used for improving oscillator accuracy Comparator COMP0_IN0- 31 2 2 – 2 – I Comparator 0 inverting input 0 COMP0_IN0+ 30 1 1 22 1 1 I Comparator 0 non-inverting input 0 COMP0_IN1- 27 30 26 19 18 14 I Comparator 0 inverting input 1 COMP0_IN1+ 24 27 23 16 16 12 I Comparator 0 non-inverting input 1 COMP0_OUT 7 11 1520 10141823 101619 61012 11 12 – O Comparator 0 output Debug SWCLK 24 27 23 16 16 12 I Serial wire debug input clock SWDIO 23 26 22 15 15 11 I/O Serial wire debug data input/output General-Purpose Amplifier GPAMP_IN+ 30 1 1 22 1 1 I GPAMP non-inverting terminal input GPAMP_OUT 26 29 25 14 17 13 O GPAMP output GPAMP_IN- 22 25 21 18 14 10 I GPAMP inverting terminal input GPIO PA0 1 4 4 24 4 3 I/O General-purpose digital I/O with wake up from SHUTDOWN PA1 2 5 5 1 5 4 I/O General-purpose digital I/O with wake up from SHUTDOWN PA2 6 9 9 5 8 7 I/O General-purpose digital I/O PA3 7 10 10 6 – – I/O General-purpose digital I/O PA4 8 11 11 7 9 – I/O General-purpose digital I/O PA5 9 12 12 – – – I/O General-purpose digital I/O PA6 10 13 13 – 10 8 I/O General-purpose digital I/O PA7 11 14 – – – – I/O General-purpose digital I/O PA8 12 15 – – – – I/O General-purpose digital I/O PA9 13 16 14 8 – – I/O General-purpose digital I/O PA10 14 17 15 9 – – I/O General-purpose digital I/O PA11 15 18 16 10 11 – I/O General-purpose digital I/O PA12 16 19 – – – – I/O General-purpose digital I/O PA13 17 20 – – – – I/O General-purpose digital I/O PA14 18 21 17 – – – I/O General-purpose digital I/O PA15 19 22 18 11 – – I/O General-purpose digital I/O PA16 20 23 19 12 12 – I/O General-purpose digital I/O PA17 21 24 20 13 13 9 I/O General-purpose digital I/O with wake up from SHUTDOWN PA18 22 25 21 14 14 10 I/O General-purpose digital I/O with wake up from SHUTDOWN PA19 23 26 22 15 15 11 I/O General-purpose digital I/O PA20 24 27 23 16 16 12 I/O General-purpose digital I/O PA21 25 28 24 17 – – I/O General-purpose digital I/O PA22 26 29 25 18 17 13 I/O General-purpose digital I/O PA23 27 30 26 19 18 14 I/O General-purpose digital I/O PA24 28 31 27 20 19 15 I/O General-purpose digital I/O PA25 29 32 28 21 20 16 I/O General-purpose digital I/O PA26 30 1 1 22 1 1 I/O General-purpose digital I/O PA27 31 2 2 – 2 – I/O General-purpose digital I/O I2C I2C0_SCL 2 15 5 18 5 16 110 5 11 4 I/O I2C0 serial clock I2C0_SDA 1 14 4 17 4 15 249 4 3 I/O I2C0 serial data I2C1_SCL 1921 24 1122 2427 1820 23 7111316 13 16 912 I/O I2C1 serial clock I2C1_SDA 2022 23 1023 2526 1921 22 6121415 1214 15 1011 I/O I2C1 serial data Operational Amplifier with Chopping (Zero-Drift Op-Amp) OPA0_IN0+ 29 32 28 21 20 16 I OPA0 non-inverting terminal input 0 OPA0_IN0- 28 31 27 20 19 15 I OPA0 inverting terminal input 0 OPA0_IN1- 28 31 27 20 19 15 I OPA0 inverting terminal input 1 OPA0_OUT 26 29 25 18 17 13 O OPA0 output OPA1_IN0+ 22 25 21 14 14 10 I OPA1 non-inverting terminal input 0 OPA1_IN0- 21 24 20 13 13 9 I OPA1 inverting terminal input 0 OPA1_IN1- 21 24 20 13 13 9 I OPA1 inverting terminal input 1 OPA1_OUT 20 23 19 12 12 – O OPA1 output Power VSS 5 8 8 4 7 6 P Ground supply VDD 4 7 7 3 6 5 P Power supply VCORE 32 3 3 23 3 2 P Regulated core power supply output QFN Pad Pad – – Pad – – P QFN package exposed thermal pad. TI recommends connection to VSS. SPI SPI0_CS0 6 12 9 15 9 5 8 7 I/O SPI0 chip-select 0 SPI0_CS1 1 721 4 1024 4 1020 24613 413 39 I/O SPI0 chip-select 1 SPI0_CS2 19 28 22 31 18 27 1120 19 15 I/O SPI0 chip-select 2 SPI0_CS3 2731 30 2 226 19 218 14 I/O SPI0 chip-select 3 SPI0_SCK 10 15 21 13 1824 13 16 20 1013 10 11 13 8 9 I/O SPI0 clock signal input – SPI peripheral mode Clock signal output – SPI controller mode SPI0_POCI 8 14202330 11 1723261 111 1519 22 79121522 191215 111 I/O SPI0 controller in/peripheral out SPI0_PICO 9 13 2229 12162532 12 14 2128 81421 1420 1016 I/O SPI0 controller out/peripheral in System NRST 3 6 6 2 5 4 I Reset input active low Timer TIMG0_C0 9 16 2027 12192330 12 1926 1219 1218 14 I/O General purpose timer 0 CCR0 capture input/ compare output TIMG0_C1 10 17 28 132031 13 27 20 10 19 8 15 I/O General purpose timer 0 CCR1 capture input/ compare output TIMG1_C0 1 111830 414211 1417 2422 14 13 I/O General purpose timer 1 CCR0 capture input/ compare output TIMG1_C1 2 6 31 592 25 9 15 25 8 4 7 I/O General purpose timer 1 CCR1 capture input/ compare output TIMG2_C0 7 12 25 101528 10 24 617 – – I/O General purpose timer 2 CCR0 capture input/ compare output TIMG2_C1 8 13 26 111629 11 14 25 7818 9 17 13 I/O General purpose timer 2 CCR1 capture input/ compare output TIMG4_C0 14 2124 172427 15 2023 1316 912 I/O General purpose timer 4 CCR0 capture input/ compare output TIMG4_C1 151922 29 18222532 161821 28 91316 11 14 20 10 16 I/O General purpose timer 4 CCR1 capture input/ compare output UART UART0_TX 12 21 252729 1524283032 20 242628 13171921 13 1820 9 1416 O UART0 transmit data UART0_RX 13 22 2630 1625291 11421 25 8141822 114 17 110 13 I UART0 receive data UART0_CTS 16 25 27 192830 24 26 1719 18 14 I UART0 "clear to send" flow control input UART0_RTS 17 26 28 202931 25 27 1820 17 19 13 15 O UART0 "request to send" flow control output UART1_TX 1 141827 4172130 4 151726 24919 418 314 O UART1 transmit data UART1_RX 2 151726 5182029 5 1625 11018 5 1117 413 I UART1 receive data UART1_CTS 7 13 18 101621 10 14 17 68 – – I UART1 "clear to send" flow control input UART1_RTS 8 12 19 111522 11 18 711 9 – O UART1 "request to send" flow control output Voltage Reference#GUID-3211147C-D305-4A41-84DB-091604D3C64A/EXT_REF VREF+ 27 30 26 19 18 14 I Voltage reference power supply - external reference input VREF- 25 28 24 17 – – I Voltage reference ground supply - external reference input – = not available I = input, O = output, I/O = input or output, P = power When using VREF+ and VREF- to bring in an external voltage reference for analog peripherals such as the ADC, a decoupling capacitor must be placed on VREF+ to VREF-/GND with a capacitance based on the external reference source Connections for Unused Pins #GUID-487452B3-7761-41B1-A78A-1FEF5D273407/GUID-550E8E14-19E0-4BDA-B278-915026A9F746 lists the correct termination of unused pins. Connection of Unused Pins PIN #GUID-487452B3-7761-41B1-A78A-1FEF5D273407/LI_CVM_21L_SQB POTENTIAL COMMENT PAx Open Set corresponding pin functions to GPIO (PINCMx.PF = 0x1) and configure unused pins to output low or input with internal pullup or pulldown resistor. NRST VCC NRST is an active-low reset signal; the pin must be pulled high to VCC or the device cannot start. For more information, see . Any unused pin with a function that is shared with general-purpose I/O must follow the "PAx" unused pin connection guidelines. Pin Configuration and Functions Pin Diagrams Pin Diagram Color Coding 32-Pin RHB (VQFN) (Top View) - MSPM0L130x 28-Pin DGS28 (VSSOP) (Top View) - MSPM0L130x 24-Pin (VQFN) (Top View) -MSPM0L130x 32-Pin DGS32 (VSSOP) (Top View) - MSPM0L130x 20-Pin DGS20 (VSSOP) (Top View) - MSPM0L130x 16-Pin DYY (SOT) (Top View) - MSPM0L130x Pin Diagrams Pin Diagram Color Coding 32-Pin RHB (VQFN) (Top View) - MSPM0L130x 28-Pin DGS28 (VSSOP) (Top View) - MSPM0L130x 24-Pin (VQFN) (Top View) -MSPM0L130x 32-Pin DGS32 (VSSOP) (Top View) - MSPM0L130x 20-Pin DGS20 (VSSOP) (Top View) - MSPM0L130x 16-Pin DYY (SOT) (Top View) - MSPM0L130x Pin Diagram Color Coding 32-Pin RHB (VQFN) (Top View) - MSPM0L130x 28-Pin DGS28 (VSSOP) (Top View) - MSPM0L130x 24-Pin (VQFN) (Top View) -MSPM0L130x 32-Pin DGS32 (VSSOP) (Top View) - MSPM0L130x 20-Pin DGS20 (VSSOP) (Top View) - MSPM0L130x 16-Pin DYY (SOT) (Top View) - MSPM0L130x Pin Diagram Color Coding Pin Diagram Color Coding 32-Pin RHB (VQFN) (Top View) - MSPM0L130x 28-Pin DGS28 (VSSOP) (Top View) - MSPM0L130x 24-Pin (VQFN) (Top View) -MSPM0L130x 32-Pin DGS32 (VSSOP) (Top View) - MSPM0L130x 20-Pin DGS20 (VSSOP) (Top View) - MSPM0L130x 16-Pin DYY (SOT) (Top View) - MSPM0L130x 32-Pin RHB (VQFN) (Top View) - MSPM0L130x 28-Pin DGS28 (VSSOP) (Top View) - MSPM0L130x 24-Pin (VQFN) (Top View) -MSPM0L130x 32-Pin DGS32 (VSSOP) (Top View) - MSPM0L130x 20-Pin DGS20 (VSSOP) (Top View) - MSPM0L130x 16-Pin DYY (SOT) (Top View) - MSPM0L130x 32-Pin RHB (VQFN) (Top View) - MSPM0L130x 28-Pin DGS28 (VSSOP) (Top View) - MSPM0L130x 24-Pin (VQFN) (Top View) -MSPM0L130x 32-Pin DGS32 (VSSOP) (Top View) - MSPM0L130x 20-Pin DGS20 (VSSOP) (Top View) - MSPM0L130x 16-Pin DYY (SOT) (Top View) - MSPM0L130x 32-Pin RHB (VQFN) (Top View) - MSPM0L130x 28-Pin DGS28 (VSSOP) (Top View) - MSPM0L130x 32-Pin RHB (VQFN) (Top View) - MSPM0L130x 32-Pin RHB (VQFN) (Top View) - MSPM0L130x 32-Pin RHB (VQFN) (Top View) - MSPM0L130x 28-Pin DGS28 (VSSOP) (Top View) - MSPM0L130x 28-Pin DGS28 (VSSOP) (Top View) - MSPM0L130x 28-Pin DGS28 (VSSOP) (Top View) - MSPM0L130x 24-Pin (VQFN) (Top View) -MSPM0L130x 32-Pin DGS32 (VSSOP) (Top View) - MSPM0L130x 24-Pin (VQFN) (Top View) -MSPM0L130x 24-Pin (VQFN) (Top View) -MSPM0L130x 24-Pin (VQFN) (Top View) -MSPM0L130x 32-Pin DGS32 (VSSOP) (Top View) - MSPM0L130x 32-Pin DGS32 (VSSOP) (Top View) - MSPM0L130x 32-Pin DGS32 (VSSOP) (Top View) - MSPM0L130x 20-Pin DGS20 (VSSOP) (Top View) - MSPM0L130x 16-Pin DYY (SOT) (Top View) - MSPM0L130x 20-Pin DGS20 (VSSOP) (Top View) - MSPM0L130x 20-Pin DGS20 (VSSOP) (Top View) - MSPM0L130x 20-Pin DGS20 (VSSOP) (Top View) - MSPM0L130x 16-Pin DYY (SOT) (Top View) - MSPM0L130x 16-Pin DYY (SOT) (Top View) - MSPM0L130x 16-Pin DYY (SOT) (Top View) - MSPM0L130x Pin Attributes The following table describes the functions available on every pin for each device package. Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) which allows users to configure the desired Pin Function using the PINCM.PF control bits. Pin Attributes PINCMx PIN NAME PIN FUNCTION PIN NUMBER I/O STRUCTURE ANALOG DIGITAL #GUID-F607BEFA-DC51-4A50-87E6-B32520DEC1E0/PIN_ATTR_NOTE_IO 32 VQFN 32 VSSOP 28 VSSOP 24 VQFN 20 VSSOP 16 SOT N/A N/A VDD 4 7 7 3 6 5 Power N/A N/A VSS 5 8 8 4 7 6 Power N/A N/A VCORE 32 3 3 23 3 2 Power 1 PA0 UART1_TX [1] / I2C0_SDA [2] / TIMG1_C0 [3] / SPI0_CS1 [4] (Default BSL I2C_SDA) 1 4 4 24 4 3 5-V tolerant Open-Drain 2 PA1 UART1_RX [1] / I2C0_SCL [2] / TIMG1_C1 [3] (Default BSL I2C_SCL) 2 5 5 1 5 4 5-V tolerant Open-Drain N/A N/A NRST 3 6 6 2 Reset#GUID-F607BEFA-DC51-4A50-87E6-B32520DEC1E0/GUID-C018AFE4-DE14-4A92-AD78-BDA7F2CD490A 3 PA2 ROSC TIMG1_C1 [1] / SPI0_CS0 [2] 6 9 9 5 8 7 Standard 4 PA3 TIMG2_C0 [1] / SPI0_CS1 [2] / UART1_CTS [3] / COMP0_OUT [4] 7 10 10 6 – – Standard 5 PA4 TIMG2_C1 [1] / SPI0_POCI [2] / UART1_RTS [3] 8 11 11 7 9 – Standard 6 PA5 TIMG0_C0 [1] / SPI0_PICO [2] 9 12 12 – – – High-Speed 7 PA6 TIMG0_C1 [1] / SPI0_SCK [2] 10 13 13 – 10 8 Standard 8 PA7 COMP0_OUT [1] / CLK_OUT [2] / TIMG1_C0 [3] 11 14 – – – – Standard 9 PA8 UART0_TX [1] / SPI0_CS0 [2] / UART1_RTS [3] / TIMG2_C0 [4] 12 15 – – – – Standard 10 PA9 UART0_RX [1] / SPI0_PICO [2] / UART1_CTS [3] / TIMG2_C1 [4] 13 16 14 8 – – Standard 11 PA10 UART1_TX [1] / SPI0_POCI [2] / I2C0_SDA [3] / TIMG4_C0 [4] 14 17 15 9 – – High-Speed 12 PA11 UART1_RX [1] / SPI0_SCK [2] / I2C0_SCL [3] / TIMG4_C1 [4] / COMP0_OUT [5] 15 18 16 10 11 – Standard 13 PA12 UART0_CTS [1] / TIMG0_C0 [2] 16 19 – – – – Standard 14 PA13 UART0_RTS [1] / TIMG0_C1 [2] / UART1_RX [3] 17 20 – – – – Standard 15 PA14 UART1_CTS [1] / CLK_OUT [2] / UART1_TX [3] / TIMG1_C0 [4] 18 21 17 – – – Standard 16 PA15 A9 UART1_RTS [1] / I2C1_SCL [2] / SPI0_CS2 [3] / TIMG4_C1 [4] 19 22 18 11 – – Standard 17 PA16 A8 / OPA1_OUT COMP0_OUT [1] / I2C1_SDA [2] / SPI0_POCI [3] / TIMG0_C0 [4] 20 23 19 12 12 – Standard 18 PA17 OPA1_IN1- UART0_TX [1] / I2C1_SCL [2] / SPI0_SCK [3] / TIMG4_C0 [4] / SPI0_CS1 [5] 21 24 20 13 13 9 Standard with wake N/A OPA1_IN0- N/A N/A OPA1_IN0- – – – – 13 – Analog 19 PA18 A7 / OPA1_IN0+ / GPAMP_IN- UART0_RX [1] / SPI0_PICO [2] / I2C1_SDA [3] / TIMG4_C1 [4] (BSL Invoke) 22 25 21 14 14 10 Standard with wake 20 PA19 SWDIO [1] / I2C1_SDA [2] / SPI0_POCI [3] 23 26 22 15 15 11 High-Speed 21 PA20 A6 / COMP0_IN1+ SWCLK [1] / I2C1_SCL [2] / TIMG4_C0 [3] 24 27 23 16 16 12 Standard 22 PA21 A5 / VREF- TIMG2_C0 [1] / UART0_CTS [2] / UART0_TX [3] 25 28 24 17 – – Standard 23 PA22 A4 / GPAMP_OUT / OPA0_OUT UART0_RX [1] / TIMG2_C1 [2] / UART0_RTS [3] / CLK_OUT [4] / UART1_RX [5] (Default BSL UART_RX) 26 29 25 18 17 13 Standard 24 PA23 VREF+ / COMP0_IN1- UART0_TX [1] / SPI0_CS3 [2] / TIMG0_C0 [3] / UART0_CTS [4] / UART1_TX [5] (Default BSL UART_TX) 27 30 26 19 18 14 Standard 25 PA24 A3 / OPA0_IN1- / OPA0_IN0- SPI0_CS2 [1] / TIMG0_C1 [2] / UART0_RTS [3] 28 31 27 20 19 15 Standard N/A N/A OPA0_IN0- – – – – 19 – Analog 26 PA25 A2 / OPA0_IN0+ TIMG4_C1 [1] / UART0_TX [2] / SPI0_PICO [3] 29 32 28 21 20 16 Standard 27 PA26 A1 / GPAMP_IN+ / COMP0_IN0+ TIMG1_C0 [1] / UART0_RX [2] / SPI0_POCI [3] 30 1 1 22 1 1 Standard 28 PA27 A0 / COMP0_IN0- TIMG1_C1 [1] / SPI0_CS3 [2] 31 2 2 – 2 – Standard PINCM.PF and PINCM.PC in IOMUX must be set to 0 for analog functions (for example, OPA inputs or outputs or COMP inputs). Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) which lets software configure the desired Pin Function using the PINCM.PF control bits. Reset PIN is muxed with PA1 for 16-pin and 20-pin devices. Digital IO Features by IO Type IO STRUCTURE INVERSION CONTROL DRIVE STRENGTH CONTROL HYSTERESIS CONTROL PULLUP RESISTOR PULLDOWN RESISTOR WAKEUP LOGIC Standard drive Y Y Y Standard drive with wake Y Y Y Y High speed Y Y Y Y 5-V tolerant open drain Y Y Y Y Pin Attributes The following table describes the functions available on every pin for each device package. Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) which allows users to configure the desired Pin Function using the PINCM.PF control bits. Pin Attributes PINCMx PIN NAME PIN FUNCTION PIN NUMBER I/O STRUCTURE ANALOG DIGITAL #GUID-F607BEFA-DC51-4A50-87E6-B32520DEC1E0/PIN_ATTR_NOTE_IO 32 VQFN 32 VSSOP 28 VSSOP 24 VQFN 20 VSSOP 16 SOT N/A N/A VDD 4 7 7 3 6 5 Power N/A N/A VSS 5 8 8 4 7 6 Power N/A N/A VCORE 32 3 3 23 3 2 Power 1 PA0 UART1_TX [1] / I2C0_SDA [2] / TIMG1_C0 [3] / SPI0_CS1 [4] (Default BSL I2C_SDA) 1 4 4 24 4 3 5-V tolerant Open-Drain 2 PA1 UART1_RX [1] / I2C0_SCL [2] / TIMG1_C1 [3] (Default BSL I2C_SCL) 2 5 5 1 5 4 5-V tolerant Open-Drain N/A N/A NRST 3 6 6 2 Reset#GUID-F607BEFA-DC51-4A50-87E6-B32520DEC1E0/GUID-C018AFE4-DE14-4A92-AD78-BDA7F2CD490A 3 PA2 ROSC TIMG1_C1 [1] / SPI0_CS0 [2] 6 9 9 5 8 7 Standard 4 PA3 TIMG2_C0 [1] / SPI0_CS1 [2] / UART1_CTS [3] / COMP0_OUT [4] 7 10 10 6 – – Standard 5 PA4 TIMG2_C1 [1] / SPI0_POCI [2] / UART1_RTS [3] 8 11 11 7 9 – Standard 6 PA5 TIMG0_C0 [1] / SPI0_PICO [2] 9 12 12 – – – High-Speed 7 PA6 TIMG0_C1 [1] / SPI0_SCK [2] 10 13 13 – 10 8 Standard 8 PA7 COMP0_OUT [1] / CLK_OUT [2] / TIMG1_C0 [3] 11 14 – – – – Standard 9 PA8 UART0_TX [1] / SPI0_CS0 [2] / UART1_RTS [3] / TIMG2_C0 [4] 12 15 – – – – Standard 10 PA9 UART0_RX [1] / SPI0_PICO [2] / UART1_CTS [3] / TIMG2_C1 [4] 13 16 14 8 – – Standard 11 PA10 UART1_TX [1] / SPI0_POCI [2] / I2C0_SDA [3] / TIMG4_C0 [4] 14 17 15 9 – – High-Speed 12 PA11 UART1_RX [1] / SPI0_SCK [2] / I2C0_SCL [3] / TIMG4_C1 [4] / COMP0_OUT [5] 15 18 16 10 11 – Standard 13 PA12 UART0_CTS [1] / TIMG0_C0 [2] 16 19 – – – – Standard 14 PA13 UART0_RTS [1] / TIMG0_C1 [2] / UART1_RX [3] 17 20 – – – – Standard 15 PA14 UART1_CTS [1] / CLK_OUT [2] / UART1_TX [3] / TIMG1_C0 [4] 18 21 17 – – – Standard 16 PA15 A9 UART1_RTS [1] / I2C1_SCL [2] / SPI0_CS2 [3] / TIMG4_C1 [4] 19 22 18 11 – – Standard 17 PA16 A8 / OPA1_OUT COMP0_OUT [1] / I2C1_SDA [2] / SPI0_POCI [3] / TIMG0_C0 [4] 20 23 19 12 12 – Standard 18 PA17 OPA1_IN1- UART0_TX [1] / I2C1_SCL [2] / SPI0_SCK [3] / TIMG4_C0 [4] / SPI0_CS1 [5] 21 24 20 13 13 9 Standard with wake N/A OPA1_IN0- N/A N/A OPA1_IN0- – – – – 13 – Analog 19 PA18 A7 / OPA1_IN0+ / GPAMP_IN- UART0_RX [1] / SPI0_PICO [2] / I2C1_SDA [3] / TIMG4_C1 [4] (BSL Invoke) 22 25 21 14 14 10 Standard with wake 20 PA19 SWDIO [1] / I2C1_SDA [2] / SPI0_POCI [3] 23 26 22 15 15 11 High-Speed 21 PA20 A6 / COMP0_IN1+ SWCLK [1] / I2C1_SCL [2] / TIMG4_C0 [3] 24 27 23 16 16 12 Standard 22 PA21 A5 / VREF- TIMG2_C0 [1] / UART0_CTS [2] / UART0_TX [3] 25 28 24 17 – – Standard 23 PA22 A4 / GPAMP_OUT / OPA0_OUT UART0_RX [1] / TIMG2_C1 [2] / UART0_RTS [3] / CLK_OUT [4] / UART1_RX [5] (Default BSL UART_RX) 26 29 25 18 17 13 Standard 24 PA23 VREF+ / COMP0_IN1- UART0_TX [1] / SPI0_CS3 [2] / TIMG0_C0 [3] / UART0_CTS [4] / UART1_TX [5] (Default BSL UART_TX) 27 30 26 19 18 14 Standard 25 PA24 A3 / OPA0_IN1- / OPA0_IN0- SPI0_CS2 [1] / TIMG0_C1 [2] / UART0_RTS [3] 28 31 27 20 19 15 Standard N/A N/A OPA0_IN0- – – – – 19 – Analog 26 PA25 A2 / OPA0_IN0+ TIMG4_C1 [1] / UART0_TX [2] / SPI0_PICO [3] 29 32 28 21 20 16 Standard 27 PA26 A1 / GPAMP_IN+ / COMP0_IN0+ TIMG1_C0 [1] / UART0_RX [2] / SPI0_POCI [3] 30 1 1 22 1 1 Standard 28 PA27 A0 / COMP0_IN0- TIMG1_C1 [1] / SPI0_CS3 [2] 31 2 2 – 2 – Standard PINCM.PF and PINCM.PC in IOMUX must be set to 0 for analog functions (for example, OPA inputs or outputs or COMP inputs). Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) which lets software configure the desired Pin Function using the PINCM.PF control bits. Reset PIN is muxed with PA1 for 16-pin and 20-pin devices. Digital IO Features by IO Type IO STRUCTURE INVERSION CONTROL DRIVE STRENGTH CONTROL HYSTERESIS CONTROL PULLUP RESISTOR PULLDOWN RESISTOR WAKEUP LOGIC Standard drive Y Y Y Standard drive with wake Y Y Y Y High speed Y Y Y Y 5-V tolerant open drain Y Y Y Y The following table describes the functions available on every pin for each device package. Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) which allows users to configure the desired Pin Function using the PINCM.PF control bits. Pin Attributes PINCMx PIN NAME PIN FUNCTION PIN NUMBER I/O STRUCTURE ANALOG DIGITAL #GUID-F607BEFA-DC51-4A50-87E6-B32520DEC1E0/PIN_ATTR_NOTE_IO 32 VQFN 32 VSSOP 28 VSSOP 24 VQFN 20 VSSOP 16 SOT N/A N/A VDD 4 7 7 3 6 5 Power N/A N/A VSS 5 8 8 4 7 6 Power N/A N/A VCORE 32 3 3 23 3 2 Power 1 PA0 UART1_TX [1] / I2C0_SDA [2] / TIMG1_C0 [3] / SPI0_CS1 [4] (Default BSL I2C_SDA) 1 4 4 24 4 3 5-V tolerant Open-Drain 2 PA1 UART1_RX [1] / I2C0_SCL [2] / TIMG1_C1 [3] (Default BSL I2C_SCL) 2 5 5 1 5 4 5-V tolerant Open-Drain N/A N/A NRST 3 6 6 2 Reset#GUID-F607BEFA-DC51-4A50-87E6-B32520DEC1E0/GUID-C018AFE4-DE14-4A92-AD78-BDA7F2CD490A 3 PA2 ROSC TIMG1_C1 [1] / SPI0_CS0 [2] 6 9 9 5 8 7 Standard 4 PA3 TIMG2_C0 [1] / SPI0_CS1 [2] / UART1_CTS [3] / COMP0_OUT [4] 7 10 10 6 – – Standard 5 PA4 TIMG2_C1 [1] / SPI0_POCI [2] / UART1_RTS [3] 8 11 11 7 9 – Standard 6 PA5 TIMG0_C0 [1] / SPI0_PICO [2] 9 12 12 – – – High-Speed 7 PA6 TIMG0_C1 [1] / SPI0_SCK [2] 10 13 13 – 10 8 Standard 8 PA7 COMP0_OUT [1] / CLK_OUT [2] / TIMG1_C0 [3] 11 14 – – – – Standard 9 PA8 UART0_TX [1] / SPI0_CS0 [2] / UART1_RTS [3] / TIMG2_C0 [4] 12 15 – – – – Standard 10 PA9 UART0_RX [1] / SPI0_PICO [2] / UART1_CTS [3] / TIMG2_C1 [4] 13 16 14 8 – – Standard 11 PA10 UART1_TX [1] / SPI0_POCI [2] / I2C0_SDA [3] / TIMG4_C0 [4] 14 17 15 9 – – High-Speed 12 PA11 UART1_RX [1] / SPI0_SCK [2] / I2C0_SCL [3] / TIMG4_C1 [4] / COMP0_OUT [5] 15 18 16 10 11 – Standard 13 PA12 UART0_CTS [1] / TIMG0_C0 [2] 16 19 – – – – Standard 14 PA13 UART0_RTS [1] / TIMG0_C1 [2] / UART1_RX [3] 17 20 – – – – Standard 15 PA14 UART1_CTS [1] / CLK_OUT [2] / UART1_TX [3] / TIMG1_C0 [4] 18 21 17 – – – Standard 16 PA15 A9 UART1_RTS [1] / I2C1_SCL [2] / SPI0_CS2 [3] / TIMG4_C1 [4] 19 22 18 11 – – Standard 17 PA16 A8 / OPA1_OUT COMP0_OUT [1] / I2C1_SDA [2] / SPI0_POCI [3] / TIMG0_C0 [4] 20 23 19 12 12 – Standard 18 PA17 OPA1_IN1- UART0_TX [1] / I2C1_SCL [2] / SPI0_SCK [3] / TIMG4_C0 [4] / SPI0_CS1 [5] 21 24 20 13 13 9 Standard with wake N/A OPA1_IN0- N/A N/A OPA1_IN0- – – – – 13 – Analog 19 PA18 A7 / OPA1_IN0+ / GPAMP_IN- UART0_RX [1] / SPI0_PICO [2] / I2C1_SDA [3] / TIMG4_C1 [4] (BSL Invoke) 22 25 21 14 14 10 Standard with wake 20 PA19 SWDIO [1] / I2C1_SDA [2] / SPI0_POCI [3] 23 26 22 15 15 11 High-Speed 21 PA20 A6 / COMP0_IN1+ SWCLK [1] / I2C1_SCL [2] / TIMG4_C0 [3] 24 27 23 16 16 12 Standard 22 PA21 A5 / VREF- TIMG2_C0 [1] / UART0_CTS [2] / UART0_TX [3] 25 28 24 17 – – Standard 23 PA22 A4 / GPAMP_OUT / OPA0_OUT UART0_RX [1] / TIMG2_C1 [2] / UART0_RTS [3] / CLK_OUT [4] / UART1_RX [5] (Default BSL UART_RX) 26 29 25 18 17 13 Standard 24 PA23 VREF+ / COMP0_IN1- UART0_TX [1] / SPI0_CS3 [2] / TIMG0_C0 [3] / UART0_CTS [4] / UART1_TX [5] (Default BSL UART_TX) 27 30 26 19 18 14 Standard 25 PA24 A3 / OPA0_IN1- / OPA0_IN0- SPI0_CS2 [1] / TIMG0_C1 [2] / UART0_RTS [3] 28 31 27 20 19 15 Standard N/A N/A OPA0_IN0- – – – – 19 – Analog 26 PA25 A2 / OPA0_IN0+ TIMG4_C1 [1] / UART0_TX [2] / SPI0_PICO [3] 29 32 28 21 20 16 Standard 27 PA26 A1 / GPAMP_IN+ / COMP0_IN0+ TIMG1_C0 [1] / UART0_RX [2] / SPI0_POCI [3] 30 1 1 22 1 1 Standard 28 PA27 A0 / COMP0_IN0- TIMG1_C1 [1] / SPI0_CS3 [2] 31 2 2 – 2 – Standard PINCM.PF and PINCM.PC in IOMUX must be set to 0 for analog functions (for example, OPA inputs or outputs or COMP inputs). Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) which lets software configure the desired Pin Function using the PINCM.PF control bits. Reset PIN is muxed with PA1 for 16-pin and 20-pin devices. The following table describes the functions available on every pin for each device package.Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) which allows users to configure the desired Pin Function using the PINCM.PF control bits.Pin Function Pin Attributes PINCMx PIN NAME PIN FUNCTION PIN NUMBER I/O STRUCTURE ANALOG DIGITAL #GUID-F607BEFA-DC51-4A50-87E6-B32520DEC1E0/PIN_ATTR_NOTE_IO 32 VQFN 32 VSSOP 28 VSSOP 24 VQFN 20 VSSOP 16 SOT N/A N/A VDD 4 7 7 3 6 5 Power N/A N/A VSS 5 8 8 4 7 6 Power N/A N/A VCORE 32 3 3 23 3 2 Power 1 PA0 UART1_TX [1] / I2C0_SDA [2] / TIMG1_C0 [3] / SPI0_CS1 [4] (Default BSL I2C_SDA) 1 4 4 24 4 3 5-V tolerant Open-Drain 2 PA1 UART1_RX [1] / I2C0_SCL [2] / TIMG1_C1 [3] (Default BSL I2C_SCL) 2 5 5 1 5 4 5-V tolerant Open-Drain N/A N/A NRST 3 6 6 2 Reset#GUID-F607BEFA-DC51-4A50-87E6-B32520DEC1E0/GUID-C018AFE4-DE14-4A92-AD78-BDA7F2CD490A 3 PA2 ROSC TIMG1_C1 [1] / SPI0_CS0 [2] 6 9 9 5 8 7 Standard 4 PA3 TIMG2_C0 [1] / SPI0_CS1 [2] / UART1_CTS [3] / COMP0_OUT [4] 7 10 10 6 – – Standard 5 PA4 TIMG2_C1 [1] / SPI0_POCI [2] / UART1_RTS [3] 8 11 11 7 9 – Standard 6 PA5 TIMG0_C0 [1] / SPI0_PICO [2] 9 12 12 – – – High-Speed 7 PA6 TIMG0_C1 [1] / SPI0_SCK [2] 10 13 13 – 10 8 Standard 8 PA7 COMP0_OUT [1] / CLK_OUT [2] / TIMG1_C0 [3] 11 14 – – – – Standard 9 PA8 UART0_TX [1] / SPI0_CS0 [2] / UART1_RTS [3] / TIMG2_C0 [4] 12 15 – – – – Standard 10 PA9 UART0_RX [1] / SPI0_PICO [2] / UART1_CTS [3] / TIMG2_C1 [4] 13 16 14 8 – – Standard 11 PA10 UART1_TX [1] / SPI0_POCI [2] / I2C0_SDA [3] / TIMG4_C0 [4] 14 17 15 9 – – High-Speed 12 PA11 UART1_RX [1] / SPI0_SCK [2] / I2C0_SCL [3] / TIMG4_C1 [4] / COMP0_OUT [5] 15 18 16 10 11 – Standard 13 PA12 UART0_CTS [1] / TIMG0_C0 [2] 16 19 – – – – Standard 14 PA13 UART0_RTS [1] / TIMG0_C1 [2] / UART1_RX [3] 17 20 – – – – Standard 15 PA14 UART1_CTS [1] / CLK_OUT [2] / UART1_TX [3] / TIMG1_C0 [4] 18 21 17 – – – Standard 16 PA15 A9 UART1_RTS [1] / I2C1_SCL [2] / SPI0_CS2 [3] / TIMG4_C1 [4] 19 22 18 11 – – Standard 17 PA16 A8 / OPA1_OUT COMP0_OUT [1] / I2C1_SDA [2] / SPI0_POCI [3] / TIMG0_C0 [4] 20 23 19 12 12 – Standard 18 PA17 OPA1_IN1- UART0_TX [1] / I2C1_SCL [2] / SPI0_SCK [3] / TIMG4_C0 [4] / SPI0_CS1 [5] 21 24 20 13 13 9 Standard with wake N/A OPA1_IN0- N/A N/A OPA1_IN0- – – – – 13 – Analog 19 PA18 A7 / OPA1_IN0+ / GPAMP_IN- UART0_RX [1] / SPI0_PICO [2] / I2C1_SDA [3] / TIMG4_C1 [4] (BSL Invoke) 22 25 21 14 14 10 Standard with wake 20 PA19 SWDIO [1] / I2C1_SDA [2] / SPI0_POCI [3] 23 26 22 15 15 11 High-Speed 21 PA20 A6 / COMP0_IN1+ SWCLK [1] / I2C1_SCL [2] / TIMG4_C0 [3] 24 27 23 16 16 12 Standard 22 PA21 A5 / VREF- TIMG2_C0 [1] / UART0_CTS [2] / UART0_TX [3] 25 28 24 17 – – Standard 23 PA22 A4 / GPAMP_OUT / OPA0_OUT UART0_RX [1] / TIMG2_C1 [2] / UART0_RTS [3] / CLK_OUT [4] / UART1_RX [5] (Default BSL UART_RX) 26 29 25 18 17 13 Standard 24 PA23 VREF+ / COMP0_IN1- UART0_TX [1] / SPI0_CS3 [2] / TIMG0_C0 [3] / UART0_CTS [4] / UART1_TX [5] (Default BSL UART_TX) 27 30 26 19 18 14 Standard 25 PA24 A3 / OPA0_IN1- / OPA0_IN0- SPI0_CS2 [1] / TIMG0_C1 [2] / UART0_RTS [3] 28 31 27 20 19 15 Standard N/A N/A OPA0_IN0- – – – – 19 – Analog 26 PA25 A2 / OPA0_IN0+ TIMG4_C1 [1] / UART0_TX [2] / SPI0_PICO [3] 29 32 28 21 20 16 Standard 27 PA26 A1 / GPAMP_IN+ / COMP0_IN0+ TIMG1_C0 [1] / UART0_RX [2] / SPI0_POCI [3] 30 1 1 22 1 1 Standard 28 PA27 A0 / COMP0_IN0- TIMG1_C1 [1] / SPI0_CS3 [2] 31 2 2 – 2 – Standard Pin Attributes PINCMx PIN NAME PIN FUNCTION PIN NUMBER I/O STRUCTURE ANALOG DIGITAL #GUID-F607BEFA-DC51-4A50-87E6-B32520DEC1E0/PIN_ATTR_NOTE_IO 32 VQFN 32 VSSOP 28 VSSOP 24 VQFN 20 VSSOP 16 SOT N/A N/A VDD 4 7 7 3 6 5 Power N/A N/A VSS 5 8 8 4 7 6 Power N/A N/A VCORE 32 3 3 23 3 2 Power 1 PA0 UART1_TX [1] / I2C0_SDA [2] / TIMG1_C0 [3] / SPI0_CS1 [4] (Default BSL I2C_SDA) 1 4 4 24 4 3 5-V tolerant Open-Drain 2 PA1 UART1_RX [1] / I2C0_SCL [2] / TIMG1_C1 [3] (Default BSL I2C_SCL) 2 5 5 1 5 4 5-V tolerant Open-Drain N/A N/A NRST 3 6 6 2 Reset#GUID-F607BEFA-DC51-4A50-87E6-B32520DEC1E0/GUID-C018AFE4-DE14-4A92-AD78-BDA7F2CD490A 3 PA2 ROSC TIMG1_C1 [1] / SPI0_CS0 [2] 6 9 9 5 8 7 Standard 4 PA3 TIMG2_C0 [1] / SPI0_CS1 [2] / UART1_CTS [3] / COMP0_OUT [4] 7 10 10 6 – – Standard 5 PA4 TIMG2_C1 [1] / SPI0_POCI [2] / UART1_RTS [3] 8 11 11 7 9 – Standard 6 PA5 TIMG0_C0 [1] / SPI0_PICO [2] 9 12 12 – – – High-Speed 7 PA6 TIMG0_C1 [1] / SPI0_SCK [2] 10 13 13 – 10 8 Standard 8 PA7 COMP0_OUT [1] / CLK_OUT [2] / TIMG1_C0 [3] 11 14 – – – – Standard 9 PA8 UART0_TX [1] / SPI0_CS0 [2] / UART1_RTS [3] / TIMG2_C0 [4] 12 15 – – – – Standard 10 PA9 UART0_RX [1] / SPI0_PICO [2] / UART1_CTS [3] / TIMG2_C1 [4] 13 16 14 8 – – Standard 11 PA10 UART1_TX [1] / SPI0_POCI [2] / I2C0_SDA [3] / TIMG4_C0 [4] 14 17 15 9 – – High-Speed 12 PA11 UART1_RX [1] / SPI0_SCK [2] / I2C0_SCL [3] / TIMG4_C1 [4] / COMP0_OUT [5] 15 18 16 10 11 – Standard 13 PA12 UART0_CTS [1] / TIMG0_C0 [2] 16 19 – – – – Standard 14 PA13 UART0_RTS [1] / TIMG0_C1 [2] / UART1_RX [3] 17 20 – – – – Standard 15 PA14 UART1_CTS [1] / CLK_OUT [2] / UART1_TX [3] / TIMG1_C0 [4] 18 21 17 – – – Standard 16 PA15 A9 UART1_RTS [1] / I2C1_SCL [2] / SPI0_CS2 [3] / TIMG4_C1 [4] 19 22 18 11 – – Standard 17 PA16 A8 / OPA1_OUT COMP0_OUT [1] / I2C1_SDA [2] / SPI0_POCI [3] / TIMG0_C0 [4] 20 23 19 12 12 – Standard 18 PA17 OPA1_IN1- UART0_TX [1] / I2C1_SCL [2] / SPI0_SCK [3] / TIMG4_C0 [4] / SPI0_CS1 [5] 21 24 20 13 13 9 Standard with wake N/A OPA1_IN0- N/A N/A OPA1_IN0- – – – – 13 – Analog 19 PA18 A7 / OPA1_IN0+ / GPAMP_IN- UART0_RX [1] / SPI0_PICO [2] / I2C1_SDA [3] / TIMG4_C1 [4] (BSL Invoke) 22 25 21 14 14 10 Standard with wake 20 PA19 SWDIO [1] / I2C1_SDA [2] / SPI0_POCI [3] 23 26 22 15 15 11 High-Speed 21 PA20 A6 / COMP0_IN1+ SWCLK [1] / I2C1_SCL [2] / TIMG4_C0 [3] 24 27 23 16 16 12 Standard 22 PA21 A5 / VREF- TIMG2_C0 [1] / UART0_CTS [2] / UART0_TX [3] 25 28 24 17 – – Standard 23 PA22 A4 / GPAMP_OUT / OPA0_OUT UART0_RX [1] / TIMG2_C1 [2] / UART0_RTS [3] / CLK_OUT [4] / UART1_RX [5] (Default BSL UART_RX) 26 29 25 18 17 13 Standard 24 PA23 VREF+ / COMP0_IN1- UART0_TX [1] / SPI0_CS3 [2] / TIMG0_C0 [3] / UART0_CTS [4] / UART1_TX [5] (Default BSL UART_TX) 27 30 26 19 18 14 Standard 25 PA24 A3 / OPA0_IN1- / OPA0_IN0- SPI0_CS2 [1] / TIMG0_C1 [2] / UART0_RTS [3] 28 31 27 20 19 15 Standard N/A N/A OPA0_IN0- – – – – 19 – Analog 26 PA25 A2 / OPA0_IN0+ TIMG4_C1 [1] / UART0_TX [2] / SPI0_PICO [3] 29 32 28 21 20 16 Standard 27 PA26 A1 / GPAMP_IN+ / COMP0_IN0+ TIMG1_C0 [1] / UART0_RX [2] / SPI0_POCI [3] 30 1 1 22 1 1 Standard 28 PA27 A0 / COMP0_IN0- TIMG1_C1 [1] / SPI0_CS3 [2] 31 2 2 – 2 – Standard PINCMx PIN NAME PIN FUNCTION PIN NUMBER I/O STRUCTURE ANALOG DIGITAL #GUID-F607BEFA-DC51-4A50-87E6-B32520DEC1E0/PIN_ATTR_NOTE_IO 32 VQFN 32 VSSOP 28 VSSOP 24 VQFN 20 VSSOP 16 SOT PINCMx PIN NAME PIN FUNCTION PIN NUMBER I/O STRUCTURE PINCMxPIN NAMEPIN FUNCTIONPIN NUMBERI/O STRUCTURE ANALOG DIGITAL #GUID-F607BEFA-DC51-4A50-87E6-B32520DEC1E0/PIN_ATTR_NOTE_IO 32 VQFN 32 VSSOP 28 VSSOP 24 VQFN 20 VSSOP 16 SOT ANALOGDIGITAL #GUID-F607BEFA-DC51-4A50-87E6-B32520DEC1E0/PIN_ATTR_NOTE_IO #GUID-F607BEFA-DC51-4A50-87E6-B32520DEC1E0/PIN_ATTR_NOTE_IO32 VQFN 32 VSSOP 28 VSSOP 24 VQFN20 VSSOP16 SOT N/A N/A VDD 4 7 7 3 6 5 Power N/A N/A VSS 5 8 8 4 7 6 Power N/A N/A VCORE 32 3 3 23 3 2 Power 1 PA0 UART1_TX [1] / I2C0_SDA [2] / TIMG1_C0 [3] / SPI0_CS1 [4] (Default BSL I2C_SDA) 1 4 4 24 4 3 5-V tolerant Open-Drain 2 PA1 UART1_RX [1] / I2C0_SCL [2] / TIMG1_C1 [3] (Default BSL I2C_SCL) 2 5 5 1 5 4 5-V tolerant Open-Drain N/A N/A NRST 3 6 6 2 Reset#GUID-F607BEFA-DC51-4A50-87E6-B32520DEC1E0/GUID-C018AFE4-DE14-4A92-AD78-BDA7F2CD490A 3 PA2 ROSC TIMG1_C1 [1] / SPI0_CS0 [2] 6 9 9 5 8 7 Standard 4 PA3 TIMG2_C0 [1] / SPI0_CS1 [2] / UART1_CTS [3] / COMP0_OUT [4] 7 10 10 6 – – Standard 5 PA4 TIMG2_C1 [1] / SPI0_POCI [2] / UART1_RTS [3] 8 11 11 7 9 – Standard 6 PA5 TIMG0_C0 [1] / SPI0_PICO [2] 9 12 12 – – – High-Speed 7 PA6 TIMG0_C1 [1] / SPI0_SCK [2] 10 13 13 – 10 8 Standard 8 PA7 COMP0_OUT [1] / CLK_OUT [2] / TIMG1_C0 [3] 11 14 – – – – Standard 9 PA8 UART0_TX [1] / SPI0_CS0 [2] / UART1_RTS [3] / TIMG2_C0 [4] 12 15 – – – – Standard 10 PA9 UART0_RX [1] / SPI0_PICO [2] / UART1_CTS [3] / TIMG2_C1 [4] 13 16 14 8 – – Standard 11 PA10 UART1_TX [1] / SPI0_POCI [2] / I2C0_SDA [3] / TIMG4_C0 [4] 14 17 15 9 – – High-Speed 12 PA11 UART1_RX [1] / SPI0_SCK [2] / I2C0_SCL [3] / TIMG4_C1 [4] / COMP0_OUT [5] 15 18 16 10 11 – Standard 13 PA12 UART0_CTS [1] / TIMG0_C0 [2] 16 19 – – – – Standard 14 PA13 UART0_RTS [1] / TIMG0_C1 [2] / UART1_RX [3] 17 20 – – – – Standard 15 PA14 UART1_CTS [1] / CLK_OUT [2] / UART1_TX [3] / TIMG1_C0 [4] 18 21 17 – – – Standard 16 PA15 A9 UART1_RTS [1] / I2C1_SCL [2] / SPI0_CS2 [3] / TIMG4_C1 [4] 19 22 18 11 – – Standard 17 PA16 A8 / OPA1_OUT COMP0_OUT [1] / I2C1_SDA [2] / SPI0_POCI [3] / TIMG0_C0 [4] 20 23 19 12 12 – Standard 18 PA17 OPA1_IN1- UART0_TX [1] / I2C1_SCL [2] / SPI0_SCK [3] / TIMG4_C0 [4] / SPI0_CS1 [5] 21 24 20 13 13 9 Standard with wake N/A OPA1_IN0- N/A N/A OPA1_IN0- – – – – 13 – Analog 19 PA18 A7 / OPA1_IN0+ / GPAMP_IN- UART0_RX [1] / SPI0_PICO [2] / I2C1_SDA [3] / TIMG4_C1 [4] (BSL Invoke) 22 25 21 14 14 10 Standard with wake 20 PA19 SWDIO [1] / I2C1_SDA [2] / SPI0_POCI [3] 23 26 22 15 15 11 High-Speed 21 PA20 A6 / COMP0_IN1+ SWCLK [1] / I2C1_SCL [2] / TIMG4_C0 [3] 24 27 23 16 16 12 Standard 22 PA21 A5 / VREF- TIMG2_C0 [1] / UART0_CTS [2] / UART0_TX [3] 25 28 24 17 – – Standard 23 PA22 A4 / GPAMP_OUT / OPA0_OUT UART0_RX [1] / TIMG2_C1 [2] / UART0_RTS [3] / CLK_OUT [4] / UART1_RX [5] (Default BSL UART_RX) 26 29 25 18 17 13 Standard 24 PA23 VREF+ / COMP0_IN1- UART0_TX [1] / SPI0_CS3 [2] / TIMG0_C0 [3] / UART0_CTS [4] / UART1_TX [5] (Default BSL UART_TX) 27 30 26 19 18 14 Standard 25 PA24 A3 / OPA0_IN1- / OPA0_IN0- SPI0_CS2 [1] / TIMG0_C1 [2] / UART0_RTS [3] 28 31 27 20 19 15 Standard N/A N/A OPA0_IN0- – – – – 19 – Analog 26 PA25 A2 / OPA0_IN0+ TIMG4_C1 [1] / UART0_TX [2] / SPI0_PICO [3] 29 32 28 21 20 16 Standard 27 PA26 A1 / GPAMP_IN+ / COMP0_IN0+ TIMG1_C0 [1] / UART0_RX [2] / SPI0_POCI [3] 30 1 1 22 1 1 Standard 28 PA27 A0 / COMP0_IN0- TIMG1_C1 [1] / SPI0_CS3 [2] 31 2 2 – 2 – Standard N/A N/A VDD 4 7 7 3 6 5 Power N/AN/AVDD477365Power N/A N/A VSS 5 8 8 4 7 6 Power N/AN/AVSS588476Power N/A N/A VCORE 32 3 3 23 3 2 Power N/AN/AVCORE32332332Power 1 PA0 UART1_TX [1] / I2C0_SDA [2] / TIMG1_C0 [3] / SPI0_CS1 [4] (Default BSL I2C_SDA) 1 4 4 24 4 3 5-V tolerant Open-Drain 1PA0UART1_TX [1] / I2C0_SDA [2] / TIMG1_C0 [3] / SPI0_CS1 [4] (Default BSL I2C_SDA) [1][2][3][4](Default BSL I2C_SDA)14424435-V tolerant Open-Drain 2 PA1 UART1_RX [1] / I2C0_SCL [2] / TIMG1_C1 [3] (Default BSL I2C_SCL) 2 5 5 1 5 4 5-V tolerant Open-Drain 2PA1UART1_RX [1] / I2C0_SCL [2] / TIMG1_C1 [3] (Default BSL I2C_SCL) [1][2][3](Default BSL I2C_SCL)2551545-V tolerant Open-Drain N/A N/A NRST 3 6 6 2 Reset#GUID-F607BEFA-DC51-4A50-87E6-B32520DEC1E0/GUID-C018AFE4-DE14-4A92-AD78-BDA7F2CD490A N/AN/ANRST3662Reset#GUID-F607BEFA-DC51-4A50-87E6-B32520DEC1E0/GUID-C018AFE4-DE14-4A92-AD78-BDA7F2CD490A #GUID-F607BEFA-DC51-4A50-87E6-B32520DEC1E0/GUID-C018AFE4-DE14-4A92-AD78-BDA7F2CD490A 3 PA2 ROSC TIMG1_C1 [1] / SPI0_CS0 [2] 6 9 9 5 8 7 Standard 3PA2ROSCTIMG1_C1 [1] / SPI0_CS0 [2] [1][2]699587Standard 4 PA3 TIMG2_C0 [1] / SPI0_CS1 [2] / UART1_CTS [3] / COMP0_OUT [4] 7 10 10 6 – – Standard 4PA3TIMG2_C0 [1] / SPI0_CS1 [2] / UART1_CTS [3] / COMP0_OUT [4] [1][2][3][4]710106––Standard 5 PA4 TIMG2_C1 [1] / SPI0_POCI [2] / UART1_RTS [3] 8 11 11 7 9 – Standard 5PA4 TIMG2_C1 [1] / SPI0_POCI [2] / UART1_RTS [3] [1][2][3]8111179–Standard 6 PA5 TIMG0_C0 [1] / SPI0_PICO [2] 9 12 12 – – – High-Speed 6PA5 TIMG0_C0 [1] / SPI0_PICO [2] [1][2]91212–––High-Speed 7 PA6 TIMG0_C1 [1] / SPI0_SCK [2] 10 13 13 – 10 8 Standard 7PA6 TIMG0_C1 [1] / SPI0_SCK [2] [1][2]101313–108Standard 8 PA7 COMP0_OUT [1] / CLK_OUT [2] / TIMG1_C0 [3] 11 14 – – – – Standard 8PA7 COMP0_OUT [1] / CLK_OUT [2] / TIMG1_C0 [3] [1][2][3]1114––––Standard 9 PA8 UART0_TX [1] / SPI0_CS0 [2] / UART1_RTS [3] / TIMG2_C0 [4] 12 15 – – – – Standard 9PA8 UART0_TX [1] / SPI0_CS0 [2] / UART1_RTS [3] / TIMG2_C0 [4] [1][2][3][4]1215––––Standard 10 PA9 UART0_RX [1] / SPI0_PICO [2] / UART1_CTS [3] / TIMG2_C1 [4] 13 16 14 8 – – Standard 10PA9 UART0_RX [1] / SPI0_PICO [2] / UART1_CTS [3] / TIMG2_C1 [4] [1][2][3][4]1316148––Standard 11 PA10 UART1_TX [1] / SPI0_POCI [2] / I2C0_SDA [3] / TIMG4_C0 [4] 14 17 15 9 – – High-Speed 11PA10 UART1_TX [1] / SPI0_POCI [2] / I2C0_SDA [3] / TIMG4_C0 [4] [1][2][3][4]1417159––High-Speed 12 PA11 UART1_RX [1] / SPI0_SCK [2] / I2C0_SCL [3] / TIMG4_C1 [4] / COMP0_OUT [5] 15 18 16 10 11 – Standard 12PA11 UART1_RX [1] / SPI0_SCK [2] / I2C0_SCL [3] / TIMG4_C1 [4] / COMP0_OUT [5] [1][2][3][4][5]1518161011–Standard 13 PA12 UART0_CTS [1] / TIMG0_C0 [2] 16 19 – – – – Standard 13PA12 UART0_CTS [1] / TIMG0_C0 [2] [1][2]1619––––Standard 14 PA13 UART0_RTS [1] / TIMG0_C1 [2] / UART1_RX [3] 17 20 – – – – Standard 14PA13 UART0_RTS [1] / TIMG0_C1 [2] / UART1_RX [3] [1][2][3]1720––––Standard 15 PA14 UART1_CTS [1] / CLK_OUT [2] / UART1_TX [3] / TIMG1_C0 [4] 18 21 17 – – – Standard 15PA14 UART1_CTS [1] / CLK_OUT [2] / UART1_TX [3] / TIMG1_C0 [4] [1][2][3][4]182117–––Standard 16 PA15 A9 UART1_RTS [1] / I2C1_SCL [2] / SPI0_CS2 [3] / TIMG4_C1 [4] 19 22 18 11 – – Standard 16PA15A9 UART1_RTS [1] / I2C1_SCL [2] / SPI0_CS2 [3] / TIMG4_C1 [4] [1][2][3][4]19221811––Standard 17 PA16 A8 / OPA1_OUT COMP0_OUT [1] / I2C1_SDA [2] / SPI0_POCI [3] / TIMG0_C0 [4] 20 23 19 12 12 – Standard 17PA16A8 / OPA1_OUT COMP0_OUT [1] / I2C1_SDA [2] / SPI0_POCI [3] / TIMG0_C0 [4] [1][2][3][4]2023191212–Standard 18 PA17 OPA1_IN1- UART0_TX [1] / I2C1_SCL [2] / SPI0_SCK [3] / TIMG4_C0 [4] / SPI0_CS1 [5] 21 24 20 13 13 9 Standard with wake 18PA17OPA1_IN1- UART0_TX [1] / I2C1_SCL [2] / SPI0_SCK [3] / TIMG4_C0 [4] / SPI0_CS1 [5] [1][2][3][4][5]21 24201313 9Standard with wake N/A OPA1_IN0- N/AOPA1_IN0- N/A N/A OPA1_IN0- – – – – 13 – Analog N/AN/AOPA1_IN0-––––13 –Analog 19 PA18 A7 / OPA1_IN0+ / GPAMP_IN- UART0_RX [1] / SPI0_PICO [2] / I2C1_SDA [3] / TIMG4_C1 [4] (BSL Invoke) 22 25 21 14 14 10 Standard with wake 19PA18A7 / OPA1_IN0+ / GPAMP_IN- UART0_RX [1] / SPI0_PICO [2] / I2C1_SDA [3] / TIMG4_C1 [4] (BSL Invoke) [1][2][3][4](BSL Invoke)222521141410Standard with wake 20 PA19 SWDIO [1] / I2C1_SDA [2] / SPI0_POCI [3] 23 26 22 15 15 11 High-Speed 20PA19 SWDIO [1] / I2C1_SDA [2] / SPI0_POCI [3] [1][2][3]232622151511High-Speed 21 PA20 A6 / COMP0_IN1+ SWCLK [1] / I2C1_SCL [2] / TIMG4_C0 [3] 24 27 23 16 16 12 Standard 21PA20A6 / COMP0_IN1+ SWCLK [1] / I2C1_SCL [2] / TIMG4_C0 [3] [1][2][3]242723161612Standard 22 PA21 A5 / VREF- TIMG2_C0 [1] / UART0_CTS [2] / UART0_TX [3] 25 28 24 17 – – Standard 22PA21A5 / VREF- TIMG2_C0 [1] / UART0_CTS [2] / UART0_TX [3] [1][2][3]25282417––Standard 23 PA22 A4 / GPAMP_OUT / OPA0_OUT UART0_RX [1] / TIMG2_C1 [2] / UART0_RTS [3] / CLK_OUT [4] / UART1_RX [5] (Default BSL UART_RX) 26 29 25 18 17 13 Standard 23PA22A4 / GPAMP_OUT / OPA0_OUT UART0_RX [1] / TIMG2_C1 [2] / UART0_RTS [3] / CLK_OUT [4] / UART1_RX [5] (Default BSL UART_RX) [1][2][3][4][5](Default BSL UART_RX)262925181713Standard 24 PA23 VREF+ / COMP0_IN1- UART0_TX [1] / SPI0_CS3 [2] / TIMG0_C0 [3] / UART0_CTS [4] / UART1_TX [5] (Default BSL UART_TX) 27 30 26 19 18 14 Standard 24PA23VREF+ / COMP0_IN1- UART0_TX [1] / SPI0_CS3 [2] / TIMG0_C0 [3] / UART0_CTS [4] / UART1_TX [5] (Default BSL UART_TX) [1][2][3][4][5](Default BSL UART_TX)273026191814Standard 25 PA24 A3 / OPA0_IN1- / OPA0_IN0- SPI0_CS2 [1] / TIMG0_C1 [2] / UART0_RTS [3] 28 31 27 20 19 15 Standard 25PA24A3 / OPA0_IN1- / OPA0_IN0- SPI0_CS2 [1] / TIMG0_C1 [2] / UART0_RTS [3] [1][2][3]283127201915Standard N/A N/A OPA0_IN0- – – – – 19 – Analog N/AN/AOPA0_IN0-––––19–Analog 26 PA25 A2 / OPA0_IN0+ TIMG4_C1 [1] / UART0_TX [2] / SPI0_PICO [3] 29 32 28 21 20 16 Standard 26PA25A2 / OPA0_IN0+ TIMG4_C1 [1] / UART0_TX [2] / SPI0_PICO [3] [1][2][3]293228212016Standard 27 PA26 A1 / GPAMP_IN+ / COMP0_IN0+ TIMG1_C0 [1] / UART0_RX [2] / SPI0_POCI [3] 30 1 1 22 1 1 Standard 27PA26A1 / GPAMP_IN+ / COMP0_IN0+ TIMG1_C0 [1] / UART0_RX [2] / SPI0_POCI [3] [1][2][3]30112211Standard 28 PA27 A0 / COMP0_IN0- TIMG1_C1 [1] / SPI0_CS3 [2] 31 2 2 – 2 – Standard 28PA27A0 / COMP0_IN0- TIMG1_C1 [1] / SPI0_CS3 [2] [1][2]3122–2–Standard PINCM.PF and PINCM.PC in IOMUX must be set to 0 for analog functions (for example, OPA inputs or outputs or COMP inputs). Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) which lets software configure the desired Pin Function using the PINCM.PF control bits. Reset PIN is muxed with PA1 for 16-pin and 20-pin devices. PINCM.PF and PINCM.PC in IOMUX must be set to 0 for analog functions (for example, OPA inputs or outputs or COMP inputs). Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) which lets software configure the desired Pin Function using the PINCM.PF control bits.IOMUXPin Function Reset PIN is muxed with PA1 for 16-pin and 20-pin devices. Digital IO Features by IO Type IO STRUCTURE INVERSION CONTROL DRIVE STRENGTH CONTROL HYSTERESIS CONTROL PULLUP RESISTOR PULLDOWN RESISTOR WAKEUP LOGIC Standard drive Y Y Y Standard drive with wake Y Y Y Y High speed Y Y Y Y 5-V tolerant open drain Y Y Y Y Digital IO Features by IO Type IO STRUCTURE INVERSION CONTROL DRIVE STRENGTH CONTROL HYSTERESIS CONTROL PULLUP RESISTOR PULLDOWN RESISTOR WAKEUP LOGIC Standard drive Y Y Y Standard drive with wake Y Y Y Y High speed Y Y Y Y 5-V tolerant open drain Y Y Y Y IO STRUCTURE INVERSION CONTROL DRIVE STRENGTH CONTROL HYSTERESIS CONTROL PULLUP RESISTOR PULLDOWN RESISTOR WAKEUP LOGIC IO STRUCTURE INVERSION CONTROL DRIVE STRENGTH CONTROL HYSTERESIS CONTROL PULLUP RESISTOR PULLDOWN RESISTOR WAKEUP LOGIC IO STRUCTUREINVERSION CONTROLDRIVE STRENGTH CONTROLHYSTERESIS CONTROLPULLUP RESISTORPULLDOWN RESISTORWAKEUP LOGIC Standard drive Y Y Y Standard drive with wake Y Y Y Y High speed Y Y Y Y 5-V tolerant open drain Y Y Y Y Standard drive Y Y Y Standard driveYYY Standard drive with wake Y Y Y Y Standard drive with wakeYYYY High speed Y Y Y Y High speedYYYY 5-V tolerant open drain Y Y Y Y 5-V tolerant open drainYYYY Signal Descriptions Signal Descriptions FUNCTION SIGNAL NAME PIN NO.#GUID-3211147C-D305-4A41-84DB-091604D3C64A/SLASE5491385467 PIN TYPE #GUID-3211147C-D305-4A41-84DB-091604D3C64A/SLAS5525442 DESCRIPTION 32 VQFN 32 VSSOP 28 VSSOP 24 VQFN 20 VSSOP 16 SOT ADC A0 31 2 2 – 2 – I ADC0 analog input 0 A1 30 1 1 22 1 1 I ADC0 analog input 1 A2 29 32 28 21 20 16 I ADC0 analog input 2 A3 28 31 27 20 19 15 I ADC0 analog input 3 A4 26 29 25 18 17 13 I ADC0 analog input 4 A5 25 28 24 17 – – I ADC0 analog input 5 A6 24 27 23 16 16 12 I ADC0 analog input 6 A7 22 25 21 14 14 10 I ADC0 analog input 7 A8 20 23 19 12 12 – I ADC0 analog input 8 A9 19 22 18 11 – – I ADC0 analog input 9 BSL BSL_invoke 22 25 21 14 14 10 I Input pin used to invoke bootloader BSL (I2C) BSLSCL 2 5 5 1 5 4 I/O Default I2C BSL clock BSLSDA 1 4 4 24 4 3 I/O Default I2C BSL data BSL (UART) BSLRX 26 29 25 18 17 13 I Default UART BSL receive BSLTX 27 30 26 19 18 14 O Default UART BSL transmit Clock CLK_OUT 11 1826 14 16172129 17 25 8918 17 13 O Configurable clock output ROSC 6 9 9 5 8 7 I External resistor used for improving oscillator accuracy Comparator COMP0_IN0- 31 2 2 – 2 – I Comparator 0 inverting input 0 COMP0_IN0+ 30 1 1 22 1 1 I Comparator 0 non-inverting input 0 COMP0_IN1- 27 30 26 19 18 14 I Comparator 0 inverting input 1 COMP0_IN1+ 24 27 23 16 16 12 I Comparator 0 non-inverting input 1 COMP0_OUT 7 11 1520 10141823 101619 61012 11 12 – O Comparator 0 output Debug SWCLK 24 27 23 16 16 12 I Serial wire debug input clock SWDIO 23 26 22 15 15 11 I/O Serial wire debug data input/output General-Purpose Amplifier GPAMP_IN+ 30 1 1 22 1 1 I GPAMP non-inverting terminal input GPAMP_OUT 26 29 25 14 17 13 O GPAMP output GPAMP_IN- 22 25 21 18 14 10 I GPAMP inverting terminal input GPIO PA0 1 4 4 24 4 3 I/O General-purpose digital I/O with wake up from SHUTDOWN PA1 2 5 5 1 5 4 I/O General-purpose digital I/O with wake up from SHUTDOWN PA2 6 9 9 5 8 7 I/O General-purpose digital I/O PA3 7 10 10 6 – – I/O General-purpose digital I/O PA4 8 11 11 7 9 – I/O General-purpose digital I/O PA5 9 12 12 – – – I/O General-purpose digital I/O PA6 10 13 13 – 10 8 I/O General-purpose digital I/O PA7 11 14 – – – – I/O General-purpose digital I/O PA8 12 15 – – – – I/O General-purpose digital I/O PA9 13 16 14 8 – – I/O General-purpose digital I/O PA10 14 17 15 9 – – I/O General-purpose digital I/O PA11 15 18 16 10 11 – I/O General-purpose digital I/O PA12 16 19 – – – – I/O General-purpose digital I/O PA13 17 20 – – – – I/O General-purpose digital I/O PA14 18 21 17 – – – I/O General-purpose digital I/O PA15 19 22 18 11 – – I/O General-purpose digital I/O PA16 20 23 19 12 12 – I/O General-purpose digital I/O PA17 21 24 20 13 13 9 I/O General-purpose digital I/O with wake up from SHUTDOWN PA18 22 25 21 14 14 10 I/O General-purpose digital I/O with wake up from SHUTDOWN PA19 23 26 22 15 15 11 I/O General-purpose digital I/O PA20 24 27 23 16 16 12 I/O General-purpose digital I/O PA21 25 28 24 17 – – I/O General-purpose digital I/O PA22 26 29 25 18 17 13 I/O General-purpose digital I/O PA23 27 30 26 19 18 14 I/O General-purpose digital I/O PA24 28 31 27 20 19 15 I/O General-purpose digital I/O PA25 29 32 28 21 20 16 I/O General-purpose digital I/O PA26 30 1 1 22 1 1 I/O General-purpose digital I/O PA27 31 2 2 – 2 – I/O General-purpose digital I/O I2C I2C0_SCL 2 15 5 18 5 16 110 5 11 4 I/O I2C0 serial clock I2C0_SDA 1 14 4 17 4 15 249 4 3 I/O I2C0 serial data I2C1_SCL 1921 24 1122 2427 1820 23 7111316 13 16 912 I/O I2C1 serial clock I2C1_SDA 2022 23 1023 2526 1921 22 6121415 1214 15 1011 I/O I2C1 serial data Operational Amplifier with Chopping (Zero-Drift Op-Amp) OPA0_IN0+ 29 32 28 21 20 16 I OPA0 non-inverting terminal input 0 OPA0_IN0- 28 31 27 20 19 15 I OPA0 inverting terminal input 0 OPA0_IN1- 28 31 27 20 19 15 I OPA0 inverting terminal input 1 OPA0_OUT 26 29 25 18 17 13 O OPA0 output OPA1_IN0+ 22 25 21 14 14 10 I OPA1 non-inverting terminal input 0 OPA1_IN0- 21 24 20 13 13 9 I OPA1 inverting terminal input 0 OPA1_IN1- 21 24 20 13 13 9 I OPA1 inverting terminal input 1 OPA1_OUT 20 23 19 12 12 – O OPA1 output Power VSS 5 8 8 4 7 6 P Ground supply VDD 4 7 7 3 6 5 P Power supply VCORE 32 3 3 23 3 2 P Regulated core power supply output QFN Pad Pad – – Pad – – P QFN package exposed thermal pad. TI recommends connection to VSS. SPI SPI0_CS0 6 12 9 15 9 5 8 7 I/O SPI0 chip-select 0 SPI0_CS1 1 721 4 1024 4 1020 24613 413 39 I/O SPI0 chip-select 1 SPI0_CS2 19 28 22 31 18 27 1120 19 15 I/O SPI0 chip-select 2 SPI0_CS3 2731 30 2 226 19 218 14 I/O SPI0 chip-select 3 SPI0_SCK 10 15 21 13 1824 13 16 20 1013 10 11 13 8 9 I/O SPI0 clock signal input – SPI peripheral mode Clock signal output – SPI controller mode SPI0_POCI 8 14202330 11 1723261 111 1519 22 79121522 191215 111 I/O SPI0 controller in/peripheral out SPI0_PICO 9 13 2229 12162532 12 14 2128 81421 1420 1016 I/O SPI0 controller out/peripheral in System NRST 3 6 6 2 5 4 I Reset input active low Timer TIMG0_C0 9 16 2027 12192330 12 1926 1219 1218 14 I/O General purpose timer 0 CCR0 capture input/ compare output TIMG0_C1 10 17 28 132031 13 27 20 10 19 8 15 I/O General purpose timer 0 CCR1 capture input/ compare output TIMG1_C0 1 111830 414211 1417 2422 14 13 I/O General purpose timer 1 CCR0 capture input/ compare output TIMG1_C1 2 6 31 592 25 9 15 25 8 4 7 I/O General purpose timer 1 CCR1 capture input/ compare output TIMG2_C0 7 12 25 101528 10 24 617 – – I/O General purpose timer 2 CCR0 capture input/ compare output TIMG2_C1 8 13 26 111629 11 14 25 7818 9 17 13 I/O General purpose timer 2 CCR1 capture input/ compare output TIMG4_C0 14 2124 172427 15 2023 1316 912 I/O General purpose timer 4 CCR0 capture input/ compare output TIMG4_C1 151922 29 18222532 161821 28 91316 11 14 20 10 16 I/O General purpose timer 4 CCR1 capture input/ compare output UART UART0_TX 12 21 252729 1524283032 20 242628 13171921 13 1820 9 1416 O UART0 transmit data UART0_RX 13 22 2630 1625291 11421 25 8141822 114 17 110 13 I UART0 receive data UART0_CTS 16 25 27 192830 24 26 1719 18 14 I UART0 "clear to send" flow control input UART0_RTS 17 26 28 202931 25 27 1820 17 19 13 15 O UART0 "request to send" flow control output UART1_TX 1 141827 4172130 4 151726 24919 418 314 O UART1 transmit data UART1_RX 2 151726 5182029 5 1625 11018 5 1117 413 I UART1 receive data UART1_CTS 7 13 18 101621 10 14 17 68 – – I UART1 "clear to send" flow control input UART1_RTS 8 12 19 111522 11 18 711 9 – O UART1 "request to send" flow control output Voltage Reference#GUID-3211147C-D305-4A41-84DB-091604D3C64A/EXT_REF VREF+ 27 30 26 19 18 14 I Voltage reference power supply - external reference input VREF- 25 28 24 17 – – I Voltage reference ground supply - external reference input – = not available I = input, O = output, I/O = input or output, P = power When using VREF+ and VREF- to bring in an external voltage reference for analog peripherals such as the ADC, a decoupling capacitor must be placed on VREF+ to VREF-/GND with a capacitance based on the external reference source Signal Descriptions Signal Descriptions FUNCTION SIGNAL NAME PIN NO.#GUID-3211147C-D305-4A41-84DB-091604D3C64A/SLASE5491385467 PIN TYPE #GUID-3211147C-D305-4A41-84DB-091604D3C64A/SLAS5525442 DESCRIPTION 32 VQFN 32 VSSOP 28 VSSOP 24 VQFN 20 VSSOP 16 SOT ADC A0 31 2 2 – 2 – I ADC0 analog input 0 A1 30 1 1 22 1 1 I ADC0 analog input 1 A2 29 32 28 21 20 16 I ADC0 analog input 2 A3 28 31 27 20 19 15 I ADC0 analog input 3 A4 26 29 25 18 17 13 I ADC0 analog input 4 A5 25 28 24 17 – – I ADC0 analog input 5 A6 24 27 23 16 16 12 I ADC0 analog input 6 A7 22 25 21 14 14 10 I ADC0 analog input 7 A8 20 23 19 12 12 – I ADC0 analog input 8 A9 19 22 18 11 – – I ADC0 analog input 9 BSL BSL_invoke 22 25 21 14 14 10 I Input pin used to invoke bootloader BSL (I2C) BSLSCL 2 5 5 1 5 4 I/O Default I2C BSL clock BSLSDA 1 4 4 24 4 3 I/O Default I2C BSL data BSL (UART) BSLRX 26 29 25 18 17 13 I Default UART BSL receive BSLTX 27 30 26 19 18 14 O Default UART BSL transmit Clock CLK_OUT 11 1826 14 16172129 17 25 8918 17 13 O Configurable clock output ROSC 6 9 9 5 8 7 I External resistor used for improving oscillator accuracy Comparator COMP0_IN0- 31 2 2 – 2 – I Comparator 0 inverting input 0 COMP0_IN0+ 30 1 1 22 1 1 I Comparator 0 non-inverting input 0 COMP0_IN1- 27 30 26 19 18 14 I Comparator 0 inverting input 1 COMP0_IN1+ 24 27 23 16 16 12 I Comparator 0 non-inverting input 1 COMP0_OUT 7 11 1520 10141823 101619 61012 11 12 – O Comparator 0 output Debug SWCLK 24 27 23 16 16 12 I Serial wire debug input clock SWDIO 23 26 22 15 15 11 I/O Serial wire debug data input/output General-Purpose Amplifier GPAMP_IN+ 30 1 1 22 1 1 I GPAMP non-inverting terminal input GPAMP_OUT 26 29 25 14 17 13 O GPAMP output GPAMP_IN- 22 25 21 18 14 10 I GPAMP inverting terminal input GPIO PA0 1 4 4 24 4 3 I/O General-purpose digital I/O with wake up from SHUTDOWN PA1 2 5 5 1 5 4 I/O General-purpose digital I/O with wake up from SHUTDOWN PA2 6 9 9 5 8 7 I/O General-purpose digital I/O PA3 7 10 10 6 – – I/O General-purpose digital I/O PA4 8 11 11 7 9 – I/O General-purpose digital I/O PA5 9 12 12 – – – I/O General-purpose digital I/O PA6 10 13 13 – 10 8 I/O General-purpose digital I/O PA7 11 14 – – – – I/O General-purpose digital I/O PA8 12 15 – – – – I/O General-purpose digital I/O PA9 13 16 14 8 – – I/O General-purpose digital I/O PA10 14 17 15 9 – – I/O General-purpose digital I/O PA11 15 18 16 10 11 – I/O General-purpose digital I/O PA12 16 19 – – – – I/O General-purpose digital I/O PA13 17 20 – – – – I/O General-purpose digital I/O PA14 18 21 17 – – – I/O General-purpose digital I/O PA15 19 22 18 11 – – I/O General-purpose digital I/O PA16 20 23 19 12 12 – I/O General-purpose digital I/O PA17 21 24 20 13 13 9 I/O General-purpose digital I/O with wake up from SHUTDOWN PA18 22 25 21 14 14 10 I/O General-purpose digital I/O with wake up from SHUTDOWN PA19 23 26 22 15 15 11 I/O General-purpose digital I/O PA20 24 27 23 16 16 12 I/O General-purpose digital I/O PA21 25 28 24 17 – – I/O General-purpose digital I/O PA22 26 29 25 18 17 13 I/O General-purpose digital I/O PA23 27 30 26 19 18 14 I/O General-purpose digital I/O PA24 28 31 27 20 19 15 I/O General-purpose digital I/O PA25 29 32 28 21 20 16 I/O General-purpose digital I/O PA26 30 1 1 22 1 1 I/O General-purpose digital I/O PA27 31 2 2 – 2 – I/O General-purpose digital I/O I2C I2C0_SCL 2 15 5 18 5 16 110 5 11 4 I/O I2C0 serial clock I2C0_SDA 1 14 4 17 4 15 249 4 3 I/O I2C0 serial data I2C1_SCL 1921 24 1122 2427 1820 23 7111316 13 16 912 I/O I2C1 serial clock I2C1_SDA 2022 23 1023 2526 1921 22 6121415 1214 15 1011 I/O I2C1 serial data Operational Amplifier with Chopping (Zero-Drift Op-Amp) OPA0_IN0+ 29 32 28 21 20 16 I OPA0 non-inverting terminal input 0 OPA0_IN0- 28 31 27 20 19 15 I OPA0 inverting terminal input 0 OPA0_IN1- 28 31 27 20 19 15 I OPA0 inverting terminal input 1 OPA0_OUT 26 29 25 18 17 13 O OPA0 output OPA1_IN0+ 22 25 21 14 14 10 I OPA1 non-inverting terminal input 0 OPA1_IN0- 21 24 20 13 13 9 I OPA1 inverting terminal input 0 OPA1_IN1- 21 24 20 13 13 9 I OPA1 inverting terminal input 1 OPA1_OUT 20 23 19 12 12 – O OPA1 output Power VSS 5 8 8 4 7 6 P Ground supply VDD 4 7 7 3 6 5 P Power supply VCORE 32 3 3 23 3 2 P Regulated core power supply output QFN Pad Pad – – Pad – – P QFN package exposed thermal pad. TI recommends connection to VSS. SPI SPI0_CS0 6 12 9 15 9 5 8 7 I/O SPI0 chip-select 0 SPI0_CS1 1 721 4 1024 4 1020 24613 413 39 I/O SPI0 chip-select 1 SPI0_CS2 19 28 22 31 18 27 1120 19 15 I/O SPI0 chip-select 2 SPI0_CS3 2731 30 2 226 19 218 14 I/O SPI0 chip-select 3 SPI0_SCK 10 15 21 13 1824 13 16 20 1013 10 11 13 8 9 I/O SPI0 clock signal input – SPI peripheral mode Clock signal output – SPI controller mode SPI0_POCI 8 14202330 11 1723261 111 1519 22 79121522 191215 111 I/O SPI0 controller in/peripheral out SPI0_PICO 9 13 2229 12162532 12 14 2128 81421 1420 1016 I/O SPI0 controller out/peripheral in System NRST 3 6 6 2 5 4 I Reset input active low Timer TIMG0_C0 9 16 2027 12192330 12 1926 1219 1218 14 I/O General purpose timer 0 CCR0 capture input/ compare output TIMG0_C1 10 17 28 132031 13 27 20 10 19 8 15 I/O General purpose timer 0 CCR1 capture input/ compare output TIMG1_C0 1 111830 414211 1417 2422 14 13 I/O General purpose timer 1 CCR0 capture input/ compare output TIMG1_C1 2 6 31 592 25 9 15 25 8 4 7 I/O General purpose timer 1 CCR1 capture input/ compare output TIMG2_C0 7 12 25 101528 10 24 617 – – I/O General purpose timer 2 CCR0 capture input/ compare output TIMG2_C1 8 13 26 111629 11 14 25 7818 9 17 13 I/O General purpose timer 2 CCR1 capture input/ compare output TIMG4_C0 14 2124 172427 15 2023 1316 912 I/O General purpose timer 4 CCR0 capture input/ compare output TIMG4_C1 151922 29 18222532 161821 28 91316 11 14 20 10 16 I/O General purpose timer 4 CCR1 capture input/ compare output UART UART0_TX 12 21 252729 1524283032 20 242628 13171921 13 1820 9 1416 O UART0 transmit data UART0_RX 13 22 2630 1625291 11421 25 8141822 114 17 110 13 I UART0 receive data UART0_CTS 16 25 27 192830 24 26 1719 18 14 I UART0 "clear to send" flow control input UART0_RTS 17 26 28 202931 25 27 1820 17 19 13 15 O UART0 "request to send" flow control output UART1_TX 1 141827 4172130 4 151726 24919 418 314 O UART1 transmit data UART1_RX 2 151726 5182029 5 1625 11018 5 1117 413 I UART1 receive data UART1_CTS 7 13 18 101621 10 14 17 68 – – I UART1 "clear to send" flow control input UART1_RTS 8 12 19 111522 11 18 711 9 – O UART1 "request to send" flow control output Voltage Reference#GUID-3211147C-D305-4A41-84DB-091604D3C64A/EXT_REF VREF+ 27 30 26 19 18 14 I Voltage reference power supply - external reference input VREF- 25 28 24 17 – – I Voltage reference ground supply - external reference input – = not available I = input, O = output, I/O = input or output, P = power When using VREF+ and VREF- to bring in an external voltage reference for analog peripherals such as the ADC, a decoupling capacitor must be placed on VREF+ to VREF-/GND with a capacitance based on the external reference source Signal Descriptions FUNCTION SIGNAL NAME PIN NO.#GUID-3211147C-D305-4A41-84DB-091604D3C64A/SLASE5491385467 PIN TYPE #GUID-3211147C-D305-4A41-84DB-091604D3C64A/SLAS5525442 DESCRIPTION 32 VQFN 32 VSSOP 28 VSSOP 24 VQFN 20 VSSOP 16 SOT ADC A0 31 2 2 – 2 – I ADC0 analog input 0 A1 30 1 1 22 1 1 I ADC0 analog input 1 A2 29 32 28 21 20 16 I ADC0 analog input 2 A3 28 31 27 20 19 15 I ADC0 analog input 3 A4 26 29 25 18 17 13 I ADC0 analog input 4 A5 25 28 24 17 – – I ADC0 analog input 5 A6 24 27 23 16 16 12 I ADC0 analog input 6 A7 22 25 21 14 14 10 I ADC0 analog input 7 A8 20 23 19 12 12 – I ADC0 analog input 8 A9 19 22 18 11 – – I ADC0 analog input 9 BSL BSL_invoke 22 25 21 14 14 10 I Input pin used to invoke bootloader BSL (I2C) BSLSCL 2 5 5 1 5 4 I/O Default I2C BSL clock BSLSDA 1 4 4 24 4 3 I/O Default I2C BSL data BSL (UART) BSLRX 26 29 25 18 17 13 I Default UART BSL receive BSLTX 27 30 26 19 18 14 O Default UART BSL transmit Clock CLK_OUT 11 1826 14 16172129 17 25 8918 17 13 O Configurable clock output ROSC 6 9 9 5 8 7 I External resistor used for improving oscillator accuracy Comparator COMP0_IN0- 31 2 2 – 2 – I Comparator 0 inverting input 0 COMP0_IN0+ 30 1 1 22 1 1 I Comparator 0 non-inverting input 0 COMP0_IN1- 27 30 26 19 18 14 I Comparator 0 inverting input 1 COMP0_IN1+ 24 27 23 16 16 12 I Comparator 0 non-inverting input 1 COMP0_OUT 7 11 1520 10141823 101619 61012 11 12 – O Comparator 0 output Debug SWCLK 24 27 23 16 16 12 I Serial wire debug input clock SWDIO 23 26 22 15 15 11 I/O Serial wire debug data input/output General-Purpose Amplifier GPAMP_IN+ 30 1 1 22 1 1 I GPAMP non-inverting terminal input GPAMP_OUT 26 29 25 14 17 13 O GPAMP output GPAMP_IN- 22 25 21 18 14 10 I GPAMP inverting terminal input GPIO PA0 1 4 4 24 4 3 I/O General-purpose digital I/O with wake up from SHUTDOWN PA1 2 5 5 1 5 4 I/O General-purpose digital I/O with wake up from SHUTDOWN PA2 6 9 9 5 8 7 I/O General-purpose digital I/O PA3 7 10 10 6 – – I/O General-purpose digital I/O PA4 8 11 11 7 9 – I/O General-purpose digital I/O PA5 9 12 12 – – – I/O General-purpose digital I/O PA6 10 13 13 – 10 8 I/O General-purpose digital I/O PA7 11 14 – – – – I/O General-purpose digital I/O PA8 12 15 – – – – I/O General-purpose digital I/O PA9 13 16 14 8 – – I/O General-purpose digital I/O PA10 14 17 15 9 – – I/O General-purpose digital I/O PA11 15 18 16 10 11 – I/O General-purpose digital I/O PA12 16 19 – – – – I/O General-purpose digital I/O PA13 17 20 – – – – I/O General-purpose digital I/O PA14 18 21 17 – – – I/O General-purpose digital I/O PA15 19 22 18 11 – – I/O General-purpose digital I/O PA16 20 23 19 12 12 – I/O General-purpose digital I/O PA17 21 24 20 13 13 9 I/O General-purpose digital I/O with wake up from SHUTDOWN PA18 22 25 21 14 14 10 I/O General-purpose digital I/O with wake up from SHUTDOWN PA19 23 26 22 15 15 11 I/O General-purpose digital I/O PA20 24 27 23 16 16 12 I/O General-purpose digital I/O PA21 25 28 24 17 – – I/O General-purpose digital I/O PA22 26 29 25 18 17 13 I/O General-purpose digital I/O PA23 27 30 26 19 18 14 I/O General-purpose digital I/O PA24 28 31 27 20 19 15 I/O General-purpose digital I/O PA25 29 32 28 21 20 16 I/O General-purpose digital I/O PA26 30 1 1 22 1 1 I/O General-purpose digital I/O PA27 31 2 2 – 2 – I/O General-purpose digital I/O I2C I2C0_SCL 2 15 5 18 5 16 110 5 11 4 I/O I2C0 serial clock I2C0_SDA 1 14 4 17 4 15 249 4 3 I/O I2C0 serial data I2C1_SCL 1921 24 1122 2427 1820 23 7111316 13 16 912 I/O I2C1 serial clock I2C1_SDA 2022 23 1023 2526 1921 22 6121415 1214 15 1011 I/O I2C1 serial data Operational Amplifier with Chopping (Zero-Drift Op-Amp) OPA0_IN0+ 29 32 28 21 20 16 I OPA0 non-inverting terminal input 0 OPA0_IN0- 28 31 27 20 19 15 I OPA0 inverting terminal input 0 OPA0_IN1- 28 31 27 20 19 15 I OPA0 inverting terminal input 1 OPA0_OUT 26 29 25 18 17 13 O OPA0 output OPA1_IN0+ 22 25 21 14 14 10 I OPA1 non-inverting terminal input 0 OPA1_IN0- 21 24 20 13 13 9 I OPA1 inverting terminal input 0 OPA1_IN1- 21 24 20 13 13 9 I OPA1 inverting terminal input 1 OPA1_OUT 20 23 19 12 12 – O OPA1 output Power VSS 5 8 8 4 7 6 P Ground supply VDD 4 7 7 3 6 5 P Power supply VCORE 32 3 3 23 3 2 P Regulated core power supply output QFN Pad Pad – – Pad – – P QFN package exposed thermal pad. TI recommends connection to VSS. SPI SPI0_CS0 6 12 9 15 9 5 8 7 I/O SPI0 chip-select 0 SPI0_CS1 1 721 4 1024 4 1020 24613 413 39 I/O SPI0 chip-select 1 SPI0_CS2 19 28 22 31 18 27 1120 19 15 I/O SPI0 chip-select 2 SPI0_CS3 2731 30 2 226 19 218 14 I/O SPI0 chip-select 3 SPI0_SCK 10 15 21 13 1824 13 16 20 1013 10 11 13 8 9 I/O SPI0 clock signal input – SPI peripheral mode Clock signal output – SPI controller mode SPI0_POCI 8 14202330 11 1723261 111 1519 22 79121522 191215 111 I/O SPI0 controller in/peripheral out SPI0_PICO 9 13 2229 12162532 12 14 2128 81421 1420 1016 I/O SPI0 controller out/peripheral in System NRST 3 6 6 2 5 4 I Reset input active low Timer TIMG0_C0 9 16 2027 12192330 12 1926 1219 1218 14 I/O General purpose timer 0 CCR0 capture input/ compare output TIMG0_C1 10 17 28 132031 13 27 20 10 19 8 15 I/O General purpose timer 0 CCR1 capture input/ compare output TIMG1_C0 1 111830 414211 1417 2422 14 13 I/O General purpose timer 1 CCR0 capture input/ compare output TIMG1_C1 2 6 31 592 25 9 15 25 8 4 7 I/O General purpose timer 1 CCR1 capture input/ compare output TIMG2_C0 7 12 25 101528 10 24 617 – – I/O General purpose timer 2 CCR0 capture input/ compare output TIMG2_C1 8 13 26 111629 11 14 25 7818 9 17 13 I/O General purpose timer 2 CCR1 capture input/ compare output TIMG4_C0 14 2124 172427 15 2023 1316 912 I/O General purpose timer 4 CCR0 capture input/ compare output TIMG4_C1 151922 29 18222532 161821 28 91316 11 14 20 10 16 I/O General purpose timer 4 CCR1 capture input/ compare output UART UART0_TX 12 21 252729 1524283032 20 242628 13171921 13 1820 9 1416 O UART0 transmit data UART0_RX 13 22 2630 1625291 11421 25 8141822 114 17 110 13 I UART0 receive data UART0_CTS 16 25 27 192830 24 26 1719 18 14 I UART0 "clear to send" flow control input UART0_RTS 17 26 28 202931 25 27 1820 17 19 13 15 O UART0 "request to send" flow control output UART1_TX 1 141827 4172130 4 151726 24919 418 314 O UART1 transmit data UART1_RX 2 151726 5182029 5 1625 11018 5 1117 413 I UART1 receive data UART1_CTS 7 13 18 101621 10 14 17 68 – – I UART1 "clear to send" flow control input UART1_RTS 8 12 19 111522 11 18 711 9 – O UART1 "request to send" flow control output Voltage Reference#GUID-3211147C-D305-4A41-84DB-091604D3C64A/EXT_REF VREF+ 27 30 26 19 18 14 I Voltage reference power supply - external reference input VREF- 25 28 24 17 – – I Voltage reference ground supply - external reference input – = not available I = input, O = output, I/O = input or output, P = power When using VREF+ and VREF- to bring in an external voltage reference for analog peripherals such as the ADC, a decoupling capacitor must be placed on VREF+ to VREF-/GND with a capacitance based on the external reference source Signal Descriptions FUNCTION SIGNAL NAME PIN NO.#GUID-3211147C-D305-4A41-84DB-091604D3C64A/SLASE5491385467 PIN TYPE #GUID-3211147C-D305-4A41-84DB-091604D3C64A/SLAS5525442 DESCRIPTION 32 VQFN 32 VSSOP 28 VSSOP 24 VQFN 20 VSSOP 16 SOT ADC A0 31 2 2 – 2 – I ADC0 analog input 0 A1 30 1 1 22 1 1 I ADC0 analog input 1 A2 29 32 28 21 20 16 I ADC0 analog input 2 A3 28 31 27 20 19 15 I ADC0 analog input 3 A4 26 29 25 18 17 13 I ADC0 analog input 4 A5 25 28 24 17 – – I ADC0 analog input 5 A6 24 27 23 16 16 12 I ADC0 analog input 6 A7 22 25 21 14 14 10 I ADC0 analog input 7 A8 20 23 19 12 12 – I ADC0 analog input 8 A9 19 22 18 11 – – I ADC0 analog input 9 BSL BSL_invoke 22 25 21 14 14 10 I Input pin used to invoke bootloader BSL (I2C) BSLSCL 2 5 5 1 5 4 I/O Default I2C BSL clock BSLSDA 1 4 4 24 4 3 I/O Default I2C BSL data BSL (UART) BSLRX 26 29 25 18 17 13 I Default UART BSL receive BSLTX 27 30 26 19 18 14 O Default UART BSL transmit Clock CLK_OUT 11 1826 14 16172129 17 25 8918 17 13 O Configurable clock output ROSC 6 9 9 5 8 7 I External resistor used for improving oscillator accuracy Comparator COMP0_IN0- 31 2 2 – 2 – I Comparator 0 inverting input 0 COMP0_IN0+ 30 1 1 22 1 1 I Comparator 0 non-inverting input 0 COMP0_IN1- 27 30 26 19 18 14 I Comparator 0 inverting input 1 COMP0_IN1+ 24 27 23 16 16 12 I Comparator 0 non-inverting input 1 COMP0_OUT 7 11 1520 10141823 101619 61012 11 12 – O Comparator 0 output Debug SWCLK 24 27 23 16 16 12 I Serial wire debug input clock SWDIO 23 26 22 15 15 11 I/O Serial wire debug data input/output General-Purpose Amplifier GPAMP_IN+ 30 1 1 22 1 1 I GPAMP non-inverting terminal input GPAMP_OUT 26 29 25 14 17 13 O GPAMP output GPAMP_IN- 22 25 21 18 14 10 I GPAMP inverting terminal input GPIO PA0 1 4 4 24 4 3 I/O General-purpose digital I/O with wake up from SHUTDOWN PA1 2 5 5 1 5 4 I/O General-purpose digital I/O with wake up from SHUTDOWN PA2 6 9 9 5 8 7 I/O General-purpose digital I/O PA3 7 10 10 6 – – I/O General-purpose digital I/O PA4 8 11 11 7 9 – I/O General-purpose digital I/O PA5 9 12 12 – – – I/O General-purpose digital I/O PA6 10 13 13 – 10 8 I/O General-purpose digital I/O PA7 11 14 – – – – I/O General-purpose digital I/O PA8 12 15 – – – – I/O General-purpose digital I/O PA9 13 16 14 8 – – I/O General-purpose digital I/O PA10 14 17 15 9 – – I/O General-purpose digital I/O PA11 15 18 16 10 11 – I/O General-purpose digital I/O PA12 16 19 – – – – I/O General-purpose digital I/O PA13 17 20 – – – – I/O General-purpose digital I/O PA14 18 21 17 – – – I/O General-purpose digital I/O PA15 19 22 18 11 – – I/O General-purpose digital I/O PA16 20 23 19 12 12 – I/O General-purpose digital I/O PA17 21 24 20 13 13 9 I/O General-purpose digital I/O with wake up from SHUTDOWN PA18 22 25 21 14 14 10 I/O General-purpose digital I/O with wake up from SHUTDOWN PA19 23 26 22 15 15 11 I/O General-purpose digital I/O PA20 24 27 23 16 16 12 I/O General-purpose digital I/O PA21 25 28 24 17 – – I/O General-purpose digital I/O PA22 26 29 25 18 17 13 I/O General-purpose digital I/O PA23 27 30 26 19 18 14 I/O General-purpose digital I/O PA24 28 31 27 20 19 15 I/O General-purpose digital I/O PA25 29 32 28 21 20 16 I/O General-purpose digital I/O PA26 30 1 1 22 1 1 I/O General-purpose digital I/O PA27 31 2 2 – 2 – I/O General-purpose digital I/O I2C I2C0_SCL 2 15 5 18 5 16 110 5 11 4 I/O I2C0 serial clock I2C0_SDA 1 14 4 17 4 15 249 4 3 I/O I2C0 serial data I2C1_SCL 1921 24 1122 2427 1820 23 7111316 13 16 912 I/O I2C1 serial clock I2C1_SDA 2022 23 1023 2526 1921 22 6121415 1214 15 1011 I/O I2C1 serial data Operational Amplifier with Chopping (Zero-Drift Op-Amp) OPA0_IN0+ 29 32 28 21 20 16 I OPA0 non-inverting terminal input 0 OPA0_IN0- 28 31 27 20 19 15 I OPA0 inverting terminal input 0 OPA0_IN1- 28 31 27 20 19 15 I OPA0 inverting terminal input 1 OPA0_OUT 26 29 25 18 17 13 O OPA0 output OPA1_IN0+ 22 25 21 14 14 10 I OPA1 non-inverting terminal input 0 OPA1_IN0- 21 24 20 13 13 9 I OPA1 inverting terminal input 0 OPA1_IN1- 21 24 20 13 13 9 I OPA1 inverting terminal input 1 OPA1_OUT 20 23 19 12 12 – O OPA1 output Power VSS 5 8 8 4 7 6 P Ground supply VDD 4 7 7 3 6 5 P Power supply VCORE 32 3 3 23 3 2 P Regulated core power supply output QFN Pad Pad – – Pad – – P QFN package exposed thermal pad. TI recommends connection to VSS. SPI SPI0_CS0 6 12 9 15 9 5 8 7 I/O SPI0 chip-select 0 SPI0_CS1 1 721 4 1024 4 1020 24613 413 39 I/O SPI0 chip-select 1 SPI0_CS2 19 28 22 31 18 27 1120 19 15 I/O SPI0 chip-select 2 SPI0_CS3 2731 30 2 226 19 218 14 I/O SPI0 chip-select 3 SPI0_SCK 10 15 21 13 1824 13 16 20 1013 10 11 13 8 9 I/O SPI0 clock signal input – SPI peripheral mode Clock signal output – SPI controller mode SPI0_POCI 8 14202330 11 1723261 111 1519 22 79121522 191215 111 I/O SPI0 controller in/peripheral out SPI0_PICO 9 13 2229 12162532 12 14 2128 81421 1420 1016 I/O SPI0 controller out/peripheral in System NRST 3 6 6 2 5 4 I Reset input active low Timer TIMG0_C0 9 16 2027 12192330 12 1926 1219 1218 14 I/O General purpose timer 0 CCR0 capture input/ compare output TIMG0_C1 10 17 28 132031 13 27 20 10 19 8 15 I/O General purpose timer 0 CCR1 capture input/ compare output TIMG1_C0 1 111830 414211 1417 2422 14 13 I/O General purpose timer 1 CCR0 capture input/ compare output TIMG1_C1 2 6 31 592 25 9 15 25 8 4 7 I/O General purpose timer 1 CCR1 capture input/ compare output TIMG2_C0 7 12 25 101528 10 24 617 – – I/O General purpose timer 2 CCR0 capture input/ compare output TIMG2_C1 8 13 26 111629 11 14 25 7818 9 17 13 I/O General purpose timer 2 CCR1 capture input/ compare output TIMG4_C0 14 2124 172427 15 2023 1316 912 I/O General purpose timer 4 CCR0 capture input/ compare output TIMG4_C1 151922 29 18222532 161821 28 91316 11 14 20 10 16 I/O General purpose timer 4 CCR1 capture input/ compare output UART UART0_TX 12 21 252729 1524283032 20 242628 13171921 13 1820 9 1416 O UART0 transmit data UART0_RX 13 22 2630 1625291 11421 25 8141822 114 17 110 13 I UART0 receive data UART0_CTS 16 25 27 192830 24 26 1719 18 14 I UART0 "clear to send" flow control input UART0_RTS 17 26 28 202931 25 27 1820 17 19 13 15 O UART0 "request to send" flow control output UART1_TX 1 141827 4172130 4 151726 24919 418 314 O UART1 transmit data UART1_RX 2 151726 5182029 5 1625 11018 5 1117 413 I UART1 receive data UART1_CTS 7 13 18 101621 10 14 17 68 – – I UART1 "clear to send" flow control input UART1_RTS 8 12 19 111522 11 18 711 9 – O UART1 "request to send" flow control output Voltage Reference#GUID-3211147C-D305-4A41-84DB-091604D3C64A/EXT_REF VREF+ 27 30 26 19 18 14 I Voltage reference power supply - external reference input VREF- 25 28 24 17 – – I Voltage reference ground supply - external reference input Signal Descriptions FUNCTION SIGNAL NAME PIN NO.#GUID-3211147C-D305-4A41-84DB-091604D3C64A/SLASE5491385467 PIN TYPE #GUID-3211147C-D305-4A41-84DB-091604D3C64A/SLAS5525442 DESCRIPTION 32 VQFN 32 VSSOP 28 VSSOP 24 VQFN 20 VSSOP 16 SOT ADC A0 31 2 2 – 2 – I ADC0 analog input 0 A1 30 1 1 22 1 1 I ADC0 analog input 1 A2 29 32 28 21 20 16 I ADC0 analog input 2 A3 28 31 27 20 19 15 I ADC0 analog input 3 A4 26 29 25 18 17 13 I ADC0 analog input 4 A5 25 28 24 17 – – I ADC0 analog input 5 A6 24 27 23 16 16 12 I ADC0 analog input 6 A7 22 25 21 14 14 10 I ADC0 analog input 7 A8 20 23 19 12 12 – I ADC0 analog input 8 A9 19 22 18 11 – – I ADC0 analog input 9 BSL BSL_invoke 22 25 21 14 14 10 I Input pin used to invoke bootloader BSL (I2C) BSLSCL 2 5 5 1 5 4 I/O Default I2C BSL clock BSLSDA 1 4 4 24 4 3 I/O Default I2C BSL data BSL (UART) BSLRX 26 29 25 18 17 13 I Default UART BSL receive BSLTX 27 30 26 19 18 14 O Default UART BSL transmit Clock CLK_OUT 11 1826 14 16172129 17 25 8918 17 13 O Configurable clock output ROSC 6 9 9 5 8 7 I External resistor used for improving oscillator accuracy Comparator COMP0_IN0- 31 2 2 – 2 – I Comparator 0 inverting input 0 COMP0_IN0+ 30 1 1 22 1 1 I Comparator 0 non-inverting input 0 COMP0_IN1- 27 30 26 19 18 14 I Comparator 0 inverting input 1 COMP0_IN1+ 24 27 23 16 16 12 I Comparator 0 non-inverting input 1 COMP0_OUT 7 11 1520 10141823 101619 61012 11 12 – O Comparator 0 output Debug SWCLK 24 27 23 16 16 12 I Serial wire debug input clock SWDIO 23 26 22 15 15 11 I/O Serial wire debug data input/output General-Purpose Amplifier GPAMP_IN+ 30 1 1 22 1 1 I GPAMP non-inverting terminal input GPAMP_OUT 26 29 25 14 17 13 O GPAMP output GPAMP_IN- 22 25 21 18 14 10 I GPAMP inverting terminal input GPIO PA0 1 4 4 24 4 3 I/O General-purpose digital I/O with wake up from SHUTDOWN PA1 2 5 5 1 5 4 I/O General-purpose digital I/O with wake up from SHUTDOWN PA2 6 9 9 5 8 7 I/O General-purpose digital I/O PA3 7 10 10 6 – – I/O General-purpose digital I/O PA4 8 11 11 7 9 – I/O General-purpose digital I/O PA5 9 12 12 – – – I/O General-purpose digital I/O PA6 10 13 13 – 10 8 I/O General-purpose digital I/O PA7 11 14 – – – – I/O General-purpose digital I/O PA8 12 15 – – – – I/O General-purpose digital I/O PA9 13 16 14 8 – – I/O General-purpose digital I/O PA10 14 17 15 9 – – I/O General-purpose digital I/O PA11 15 18 16 10 11 – I/O General-purpose digital I/O PA12 16 19 – – – – I/O General-purpose digital I/O PA13 17 20 – – – – I/O General-purpose digital I/O PA14 18 21 17 – – – I/O General-purpose digital I/O PA15 19 22 18 11 – – I/O General-purpose digital I/O PA16 20 23 19 12 12 – I/O General-purpose digital I/O PA17 21 24 20 13 13 9 I/O General-purpose digital I/O with wake up from SHUTDOWN PA18 22 25 21 14 14 10 I/O General-purpose digital I/O with wake up from SHUTDOWN PA19 23 26 22 15 15 11 I/O General-purpose digital I/O PA20 24 27 23 16 16 12 I/O General-purpose digital I/O PA21 25 28 24 17 – – I/O General-purpose digital I/O PA22 26 29 25 18 17 13 I/O General-purpose digital I/O PA23 27 30 26 19 18 14 I/O General-purpose digital I/O PA24 28 31 27 20 19 15 I/O General-purpose digital I/O PA25 29 32 28 21 20 16 I/O General-purpose digital I/O PA26 30 1 1 22 1 1 I/O General-purpose digital I/O PA27 31 2 2 – 2 – I/O General-purpose digital I/O I2C I2C0_SCL 2 15 5 18 5 16 110 5 11 4 I/O I2C0 serial clock I2C0_SDA 1 14 4 17 4 15 249 4 3 I/O I2C0 serial data I2C1_SCL 1921 24 1122 2427 1820 23 7111316 13 16 912 I/O I2C1 serial clock I2C1_SDA 2022 23 1023 2526 1921 22 6121415 1214 15 1011 I/O I2C1 serial data Operational Amplifier with Chopping (Zero-Drift Op-Amp) OPA0_IN0+ 29 32 28 21 20 16 I OPA0 non-inverting terminal input 0 OPA0_IN0- 28 31 27 20 19 15 I OPA0 inverting terminal input 0 OPA0_IN1- 28 31 27 20 19 15 I OPA0 inverting terminal input 1 OPA0_OUT 26 29 25 18 17 13 O OPA0 output OPA1_IN0+ 22 25 21 14 14 10 I OPA1 non-inverting terminal input 0 OPA1_IN0- 21 24 20 13 13 9 I OPA1 inverting terminal input 0 OPA1_IN1- 21 24 20 13 13 9 I OPA1 inverting terminal input 1 OPA1_OUT 20 23 19 12 12 – O OPA1 output Power VSS 5 8 8 4 7 6 P Ground supply VDD 4 7 7 3 6 5 P Power supply VCORE 32 3 3 23 3 2 P Regulated core power supply output QFN Pad Pad – – Pad – – P QFN package exposed thermal pad. TI recommends connection to VSS. SPI SPI0_CS0 6 12 9 15 9 5 8 7 I/O SPI0 chip-select 0 SPI0_CS1 1 721 4 1024 4 1020 24613 413 39 I/O SPI0 chip-select 1 SPI0_CS2 19 28 22 31 18 27 1120 19 15 I/O SPI0 chip-select 2 SPI0_CS3 2731 30 2 226 19 218 14 I/O SPI0 chip-select 3 SPI0_SCK 10 15 21 13 1824 13 16 20 1013 10 11 13 8 9 I/O SPI0 clock signal input – SPI peripheral mode Clock signal output – SPI controller mode SPI0_POCI 8 14202330 11 1723261 111 1519 22 79121522 191215 111 I/O SPI0 controller in/peripheral out SPI0_PICO 9 13 2229 12162532 12 14 2128 81421 1420 1016 I/O SPI0 controller out/peripheral in System NRST 3 6 6 2 5 4 I Reset input active low Timer TIMG0_C0 9 16 2027 12192330 12 1926 1219 1218 14 I/O General purpose timer 0 CCR0 capture input/ compare output TIMG0_C1 10 17 28 132031 13 27 20 10 19 8 15 I/O General purpose timer 0 CCR1 capture input/ compare output TIMG1_C0 1 111830 414211 1417 2422 14 13 I/O General purpose timer 1 CCR0 capture input/ compare output TIMG1_C1 2 6 31 592 25 9 15 25 8 4 7 I/O General purpose timer 1 CCR1 capture input/ compare output TIMG2_C0 7 12 25 101528 10 24 617 – – I/O General purpose timer 2 CCR0 capture input/ compare output TIMG2_C1 8 13 26 111629 11 14 25 7818 9 17 13 I/O General purpose timer 2 CCR1 capture input/ compare output TIMG4_C0 14 2124 172427 15 2023 1316 912 I/O General purpose timer 4 CCR0 capture input/ compare output TIMG4_C1 151922 29 18222532 161821 28 91316 11 14 20 10 16 I/O General purpose timer 4 CCR1 capture input/ compare output UART UART0_TX 12 21 252729 1524283032 20 242628 13171921 13 1820 9 1416 O UART0 transmit data UART0_RX 13 22 2630 1625291 11421 25 8141822 114 17 110 13 I UART0 receive data UART0_CTS 16 25 27 192830 24 26 1719 18 14 I UART0 "clear to send" flow control input UART0_RTS 17 26 28 202931 25 27 1820 17 19 13 15 O UART0 "request to send" flow control output UART1_TX 1 141827 4172130 4 151726 24919 418 314 O UART1 transmit data UART1_RX 2 151726 5182029 5 1625 11018 5 1117 413 I UART1 receive data UART1_CTS 7 13 18 101621 10 14 17 68 – – I UART1 "clear to send" flow control input UART1_RTS 8 12 19 111522 11 18 711 9 – O UART1 "request to send" flow control output Voltage Reference#GUID-3211147C-D305-4A41-84DB-091604D3C64A/EXT_REF VREF+ 27 30 26 19 18 14 I Voltage reference power supply - external reference input VREF- 25 28 24 17 – – I Voltage reference ground supply - external reference input FUNCTION SIGNAL NAME PIN NO.#GUID-3211147C-D305-4A41-84DB-091604D3C64A/SLASE5491385467 PIN TYPE #GUID-3211147C-D305-4A41-84DB-091604D3C64A/SLAS5525442 DESCRIPTION 32 VQFN 32 VSSOP 28 VSSOP 24 VQFN 20 VSSOP 16 SOT FUNCTION SIGNAL NAME PIN NO.#GUID-3211147C-D305-4A41-84DB-091604D3C64A/SLASE5491385467 PIN TYPE #GUID-3211147C-D305-4A41-84DB-091604D3C64A/SLAS5525442 DESCRIPTION FUNCTIONSIGNAL NAMEPIN NO.#GUID-3211147C-D305-4A41-84DB-091604D3C64A/SLASE5491385467 #GUID-3211147C-D305-4A41-84DB-091604D3C64A/SLASE5491385467PIN TYPE #GUID-3211147C-D305-4A41-84DB-091604D3C64A/SLAS5525442 #GUID-3211147C-D305-4A41-84DB-091604D3C64A/SLAS5525442DESCRIPTION 32 VQFN 32 VSSOP 28 VSSOP 24 VQFN 20 VSSOP 16 SOT 32 VQFN32 VSSOP28 VSSOP 24 VQFN20 VSSOP16 SOT ADC A0 31 2 2 – 2 – I ADC0 analog input 0 A1 30 1 1 22 1 1 I ADC0 analog input 1 A2 29 32 28 21 20 16 I ADC0 analog input 2 A3 28 31 27 20 19 15 I ADC0 analog input 3 A4 26 29 25 18 17 13 I ADC0 analog input 4 A5 25 28 24 17 – – I ADC0 analog input 5 A6 24 27 23 16 16 12 I ADC0 analog input 6 A7 22 25 21 14 14 10 I ADC0 analog input 7 A8 20 23 19 12 12 – I ADC0 analog input 8 A9 19 22 18 11 – – I ADC0 analog input 9 BSL BSL_invoke 22 25 21 14 14 10 I Input pin used to invoke bootloader BSL (I2C) BSLSCL 2 5 5 1 5 4 I/O Default I2C BSL clock BSLSDA 1 4 4 24 4 3 I/O Default I2C BSL data BSL (UART) BSLRX 26 29 25 18 17 13 I Default UART BSL receive BSLTX 27 30 26 19 18 14 O Default UART BSL transmit Clock CLK_OUT 11 1826 14 16172129 17 25 8918 17 13 O Configurable clock output ROSC 6 9 9 5 8 7 I External resistor used for improving oscillator accuracy Comparator COMP0_IN0- 31 2 2 – 2 – I Comparator 0 inverting input 0 COMP0_IN0+ 30 1 1 22 1 1 I Comparator 0 non-inverting input 0 COMP0_IN1- 27 30 26 19 18 14 I Comparator 0 inverting input 1 COMP0_IN1+ 24 27 23 16 16 12 I Comparator 0 non-inverting input 1 COMP0_OUT 7 11 1520 10141823 101619 61012 11 12 – O Comparator 0 output Debug SWCLK 24 27 23 16 16 12 I Serial wire debug input clock SWDIO 23 26 22 15 15 11 I/O Serial wire debug data input/output General-Purpose Amplifier GPAMP_IN+ 30 1 1 22 1 1 I GPAMP non-inverting terminal input GPAMP_OUT 26 29 25 14 17 13 O GPAMP output GPAMP_IN- 22 25 21 18 14 10 I GPAMP inverting terminal input GPIO PA0 1 4 4 24 4 3 I/O General-purpose digital I/O with wake up from SHUTDOWN PA1 2 5 5 1 5 4 I/O General-purpose digital I/O with wake up from SHUTDOWN PA2 6 9 9 5 8 7 I/O General-purpose digital I/O PA3 7 10 10 6 – – I/O General-purpose digital I/O PA4 8 11 11 7 9 – I/O General-purpose digital I/O PA5 9 12 12 – – – I/O General-purpose digital I/O PA6 10 13 13 – 10 8 I/O General-purpose digital I/O PA7 11 14 – – – – I/O General-purpose digital I/O PA8 12 15 – – – – I/O General-purpose digital I/O PA9 13 16 14 8 – – I/O General-purpose digital I/O PA10 14 17 15 9 – – I/O General-purpose digital I/O PA11 15 18 16 10 11 – I/O General-purpose digital I/O PA12 16 19 – – – – I/O General-purpose digital I/O PA13 17 20 – – – – I/O General-purpose digital I/O PA14 18 21 17 – – – I/O General-purpose digital I/O PA15 19 22 18 11 – – I/O General-purpose digital I/O PA16 20 23 19 12 12 – I/O General-purpose digital I/O PA17 21 24 20 13 13 9 I/O General-purpose digital I/O with wake up from SHUTDOWN PA18 22 25 21 14 14 10 I/O General-purpose digital I/O with wake up from SHUTDOWN PA19 23 26 22 15 15 11 I/O General-purpose digital I/O PA20 24 27 23 16 16 12 I/O General-purpose digital I/O PA21 25 28 24 17 – – I/O General-purpose digital I/O PA22 26 29 25 18 17 13 I/O General-purpose digital I/O PA23 27 30 26 19 18 14 I/O General-purpose digital I/O PA24 28 31 27 20 19 15 I/O General-purpose digital I/O PA25 29 32 28 21 20 16 I/O General-purpose digital I/O PA26 30 1 1 22 1 1 I/O General-purpose digital I/O PA27 31 2 2 – 2 – I/O General-purpose digital I/O I2C I2C0_SCL 2 15 5 18 5 16 110 5 11 4 I/O I2C0 serial clock I2C0_SDA 1 14 4 17 4 15 249 4 3 I/O I2C0 serial data I2C1_SCL 1921 24 1122 2427 1820 23 7111316 13 16 912 I/O I2C1 serial clock I2C1_SDA 2022 23 1023 2526 1921 22 6121415 1214 15 1011 I/O I2C1 serial data Operational Amplifier with Chopping (Zero-Drift Op-Amp) OPA0_IN0+ 29 32 28 21 20 16 I OPA0 non-inverting terminal input 0 OPA0_IN0- 28 31 27 20 19 15 I OPA0 inverting terminal input 0 OPA0_IN1- 28 31 27 20 19 15 I OPA0 inverting terminal input 1 OPA0_OUT 26 29 25 18 17 13 O OPA0 output OPA1_IN0+ 22 25 21 14 14 10 I OPA1 non-inverting terminal input 0 OPA1_IN0- 21 24 20 13 13 9 I OPA1 inverting terminal input 0 OPA1_IN1- 21 24 20 13 13 9 I OPA1 inverting terminal input 1 OPA1_OUT 20 23 19 12 12 – O OPA1 output Power VSS 5 8 8 4 7 6 P Ground supply VDD 4 7 7 3 6 5 P Power supply VCORE 32 3 3 23 3 2 P Regulated core power supply output QFN Pad Pad – – Pad – – P QFN package exposed thermal pad. TI recommends connection to VSS. SPI SPI0_CS0 6 12 9 15 9 5 8 7 I/O SPI0 chip-select 0 SPI0_CS1 1 721 4 1024 4 1020 24613 413 39 I/O SPI0 chip-select 1 SPI0_CS2 19 28 22 31 18 27 1120 19 15 I/O SPI0 chip-select 2 SPI0_CS3 2731 30 2 226 19 218 14 I/O SPI0 chip-select 3 SPI0_SCK 10 15 21 13 1824 13 16 20 1013 10 11 13 8 9 I/O SPI0 clock signal input – SPI peripheral mode Clock signal output – SPI controller mode SPI0_POCI 8 14202330 11 1723261 111 1519 22 79121522 191215 111 I/O SPI0 controller in/peripheral out SPI0_PICO 9 13 2229 12162532 12 14 2128 81421 1420 1016 I/O SPI0 controller out/peripheral in System NRST 3 6 6 2 5 4 I Reset input active low Timer TIMG0_C0 9 16 2027 12192330 12 1926 1219 1218 14 I/O General purpose timer 0 CCR0 capture input/ compare output TIMG0_C1 10 17 28 132031 13 27 20 10 19 8 15 I/O General purpose timer 0 CCR1 capture input/ compare output TIMG1_C0 1 111830 414211 1417 2422 14 13 I/O General purpose timer 1 CCR0 capture input/ compare output TIMG1_C1 2 6 31 592 25 9 15 25 8 4 7 I/O General purpose timer 1 CCR1 capture input/ compare output TIMG2_C0 7 12 25 101528 10 24 617 – – I/O General purpose timer 2 CCR0 capture input/ compare output TIMG2_C1 8 13 26 111629 11 14 25 7818 9 17 13 I/O General purpose timer 2 CCR1 capture input/ compare output TIMG4_C0 14 2124 172427 15 2023 1316 912 I/O General purpose timer 4 CCR0 capture input/ compare output TIMG4_C1 151922 29 18222532 161821 28 91316 11 14 20 10 16 I/O General purpose timer 4 CCR1 capture input/ compare output UART UART0_TX 12 21 252729 1524283032 20 242628 13171921 13 1820 9 1416 O UART0 transmit data UART0_RX 13 22 2630 1625291 11421 25 8141822 114 17 110 13 I UART0 receive data UART0_CTS 16 25 27 192830 24 26 1719 18 14 I UART0 "clear to send" flow control input UART0_RTS 17 26 28 202931 25 27 1820 17 19 13 15 O UART0 "request to send" flow control output UART1_TX 1 141827 4172130 4 151726 24919 418 314 O UART1 transmit data UART1_RX 2 151726 5182029 5 1625 11018 5 1117 413 I UART1 receive data UART1_CTS 7 13 18 101621 10 14 17 68 – – I UART1 "clear to send" flow control input UART1_RTS 8 12 19 111522 11 18 711 9 – O UART1 "request to send" flow control output Voltage Reference#GUID-3211147C-D305-4A41-84DB-091604D3C64A/EXT_REF VREF+ 27 30 26 19 18 14 I Voltage reference power supply - external reference input VREF- 25 28 24 17 – – I Voltage reference ground supply - external reference input ADC A0 31 2 2 – 2 – I ADC0 analog input 0 ADCA031 22 –2–IADC0 analog input 0 A1 30 1 1 22 1 1 I ADC0 analog input 1 A130 11 2211IADC0 analog input 1 A2 29 32 28 21 20 16 I ADC0 analog input 2 A229 3228 212016IADC0 analog input 2 A3 28 31 27 20 19 15 I ADC0 analog input 3 A328 3127 2019 15IADC0 analog input 3 A4 26 29 25 18 17 13 I ADC0 analog input 4 A426 2925 181713IADC0 analog input 4 A5 25 28 24 17 – – I ADC0 analog input 5 A525 2824 17––IADC0 analog input 5 A6 24 27 23 16 16 12 I ADC0 analog input 6 A624 2723 161612IADC0 analog input 6 A7 22 25 21 14 14 10 I ADC0 analog input 7 A722 2521 141410IADC0 analog input 7 A8 20 23 19 12 12 – I ADC0 analog input 8 A820 2319 1212–IADC0 analog input 8 A9 19 22 18 11 – – I ADC0 analog input 9 A919 2218 11––IADC0 analog input 9 BSL BSL_invoke 22 25 21 14 14 10 I Input pin used to invoke bootloader BSLBSL_invoke22 2521 141410IInput pin used to invoke bootloader BSL (I2C) BSLSCL 2 5 5 1 5 4 I/O Default I2C BSL clock BSL (I2C)2BSLSCL2 55 154I/ODefault I2C BSL clock2 BSLSDA 1 4 4 24 4 3 I/O Default I2C BSL data BSLSDA1 44 2443I/ODefault I2C BSL data2 BSL (UART) BSLRX 26 29 25 18 17 13 I Default UART BSL receive BSL (UART)BSLRX26 2925 181713IDefault UART BSL receive BSLTX 27 30 26 19 18 14 O Default UART BSL transmit BSLTX27 3026 191814ODefault UART BSL transmit Clock CLK_OUT 11 1826 14 16172129 17 25 8918 17 13 O Configurable clock output ClockCLK_OUT11 1826 14 1617212917 25 89181713OConfigurable clock output ROSC 6 9 9 5 8 7 I External resistor used for improving oscillator accuracy ROSC6 99 587IExternal resistor used for improving oscillator accuracy Comparator COMP0_IN0- 31 2 2 – 2 – I Comparator 0 inverting input 0 ComparatorCOMP0_IN0-31 22 –2–IComparator 0 inverting input 0 COMP0_IN0+ 30 1 1 22 1 1 I Comparator 0 non-inverting input 0 COMP0_IN0+30 11 2211IComparator 0 non-inverting input 0 COMP0_IN1- 27 30 26 19 18 14 I Comparator 0 inverting input 1 COMP0_IN1-27 3026 191814IComparator 0 inverting input 1 COMP0_IN1+ 24 27 23 16 16 12 I Comparator 0 non-inverting input 1 COMP0_IN1+24 2723 161612IComparator 0 non-inverting input 1 COMP0_OUT 7 11 1520 10141823 101619 61012 11 12 – O Comparator 0 output COMP0_OUT7 11 1520 10141823101619 6101211 12–OComparator 0 output Debug SWCLK 24 27 23 16 16 12 I Serial wire debug input clock DebugSWCLK24 2723 161612ISerial wire debug input clock SWDIO 23 26 22 15 15 11 I/O Serial wire debug data input/output SWDIO23 2622 151511I/OSerial wire debug data input/output General-Purpose Amplifier GPAMP_IN+ 30 1 1 22 1 1 I GPAMP non-inverting terminal input General-Purpose AmplifierGPAMP_IN+30 11 2211IGPAMP non-inverting terminal input GPAMP_OUT 26 29 25 14 17 13 O GPAMP output GPAMP_OUT26 2925 141713OGPAMP output GPAMP_IN- 22 25 21 18 14 10 I GPAMP inverting terminal input GPAMP_IN-22 2521 181410IGPAMP inverting terminal input GPIO PA0 1 4 4 24 4 3 I/O General-purpose digital I/O with wake up from SHUTDOWN GPIOPA01 44 2443I/OGeneral-purpose digital I/O with wake up from SHUTDOWN PA1 2 5 5 1 5 4 I/O General-purpose digital I/O with wake up from SHUTDOWN PA12 55 154I/OGeneral-purpose digital I/O with wake up from SHUTDOWN PA2 6 9 9 5 8 7 I/O General-purpose digital I/O PA26 99 587I/OGeneral-purpose digital I/O PA3 7 10 10 6 – – I/O General-purpose digital I/O PA37 1010 6––I/OGeneral-purpose digital I/O PA4 8 11 11 7 9 – I/O General-purpose digital I/O PA48 1111 79–I/OGeneral-purpose digital I/O PA5 9 12 12 – – – I/O General-purpose digital I/O PA59 1212 –––I/OGeneral-purpose digital I/O PA6 10 13 13 – 10 8 I/O General-purpose digital I/O PA610 1313 –108I/OGeneral-purpose digital I/O PA7 11 14 – – – – I/O General-purpose digital I/O PA711 14– –––I/OGeneral-purpose digital I/O PA8 12 15 – – – – I/O General-purpose digital I/O PA812 15– –––I/OGeneral-purpose digital I/O PA9 13 16 14 8 – – I/O General-purpose digital I/O PA913 1614 8––I/OGeneral-purpose digital I/O PA10 14 17 15 9 – – I/O General-purpose digital I/O PA1014 1715 9––I/OGeneral-purpose digital I/O PA11 15 18 16 10 11 – I/O General-purpose digital I/O PA1115 1816 1011–I/OGeneral-purpose digital I/O PA12 16 19 – – – – I/O General-purpose digital I/O PA1216 19– –––I/OGeneral-purpose digital I/O PA13 17 20 – – – – I/O General-purpose digital I/O PA1317 20– –––I/OGeneral-purpose digital I/O PA14 18 21 17 – – – I/O General-purpose digital I/O PA1418 2117 –––I/OGeneral-purpose digital I/O PA15 19 22 18 11 – – I/O General-purpose digital I/O PA1519 2218 11––I/OGeneral-purpose digital I/O PA16 20 23 19 12 12 – I/O General-purpose digital I/O PA1620 2319 1212–I/OGeneral-purpose digital I/O PA17 21 24 20 13 13 9 I/O General-purpose digital I/O with wake up from SHUTDOWN PA1721 2420 1313 9I/OGeneral-purpose digital I/O with wake up from SHUTDOWN PA18 22 25 21 14 14 10 I/O General-purpose digital I/O with wake up from SHUTDOWN PA1822 2521 141410I/OGeneral-purpose digital I/O with wake up from SHUTDOWN PA19 23 26 22 15 15 11 I/O General-purpose digital I/O PA1923 2622 151511I/OGeneral-purpose digital I/O PA20 24 27 23 16 16 12 I/O General-purpose digital I/O PA2024 2723 161612I/OGeneral-purpose digital I/O PA21 25 28 24 17 – – I/O General-purpose digital I/O PA2125 2824 17––I/OGeneral-purpose digital I/O PA22 26 29 25 18 17 13 I/O General-purpose digital I/O PA2226 2925 181713I/OGeneral-purpose digital I/O PA23 27 30 26 19 18 14 I/O General-purpose digital I/O PA2327 3026 191814I/OGeneral-purpose digital I/O PA24 28 31 27 20 19 15 I/O General-purpose digital I/O PA2428 3127 2019 15I/OGeneral-purpose digital I/O PA25 29 32 28 21 20 16 I/O General-purpose digital I/O PA2529 3228 212016I/OGeneral-purpose digital I/O PA26 30 1 1 22 1 1 I/O General-purpose digital I/O PA2630 11 2211I/OGeneral-purpose digital I/O PA27 31 2 2 – 2 – I/O General-purpose digital I/O PA2731 22 –2–I/OGeneral-purpose digital I/O I2C I2C0_SCL 2 15 5 18 5 16 110 5 11 4 I/O I2C0 serial clock I2C2I2C0_SCL2 15 5 185 16 1105 114I/OI2C0 serial clock I2C0_SDA 1 14 4 17 4 15 249 4 3 I/O I2C0 serial data I2C0_SDA1 14 4 174 15 24943I/OI2C0 serial data I2C1_SCL 1921 24 1122 2427 1820 23 7111316 13 16 912 I/O I2C1 serial clock I2C1_SCL1921 24 1122 24271820 23 711131613 16912I/OI2C1 serial clock I2C1_SDA 2022 23 1023 2526 1921 22 6121415 1214 15 1011 I/O I2C1 serial data I2C1_SDA2022 23 1023 25261921 2261214151214 151011I/OI2C1 serial data Operational Amplifier with Chopping (Zero-Drift Op-Amp) OPA0_IN0+ 29 32 28 21 20 16 I OPA0 non-inverting terminal input 0 Operational Amplifier with Chopping (Zero-Drift Op-Amp)OPA0_IN0+29 3228 212016IOPA0 non-inverting terminal input 0 OPA0_IN0- 28 31 27 20 19 15 I OPA0 inverting terminal input 0 OPA0_IN0-28 3127 201915IOPA0 inverting terminal input 0 OPA0_IN1- 28 31 27 20 19 15 I OPA0 inverting terminal input 1 OPA0_IN1-28 3127 2019 15IOPA0 inverting terminal input 1 OPA0_OUT 26 29 25 18 17 13 O OPA0 output OPA0_OUT26 2925 181713OOPA0 output OPA1_IN0+ 22 25 21 14 14 10 I OPA1 non-inverting terminal input 0 OPA1_IN0+22 2521 141410IOPA1 non-inverting terminal input 0 OPA1_IN0- 21 24 20 13 13 9 I OPA1 inverting terminal input 0 OPA1_IN0-21 2420 13139IOPA1 inverting terminal input 0 OPA1_IN1- 21 24 20 13 13 9 I OPA1 inverting terminal input 1 OPA1_IN1-21 2420 1313 9IOPA1 inverting terminal input 1 OPA1_OUT 20 23 19 12 12 – O OPA1 output OPA1_OUT20 2319 1212–OOPA1 output Power VSS 5 8 8 4 7 6 P Ground supply PowerVSS5 88 476PGround supply VDD 4 7 7 3 6 5 P Power supply VDD4 7 7 365PPower supply VCORE 32 3 3 23 3 2 P Regulated core power supply output VCORE32 33 2332PRegulated core power supply output QFN Pad Pad – – Pad – – P QFN package exposed thermal pad. TI recommends connection to VSS. QFN PadPad –– Pad––PQFN package exposed thermal pad. TI recommends connection to VSS.SS SPI SPI0_CS0 6 12 9 15 9 5 8 7 I/O SPI0 chip-select 0 SPISPI0_CS06 129 159 587I/OSPI0 chip-select 0 SPI0_CS1 1 721 4 1024 4 1020 24613 413 39 I/O SPI0 chip-select 1 SPI0_CS11 7214 10244 10202461341339I/OSPI0 chip-select 1 SPI0_CS2 19 28 22 31 18 27 1120 19 15 I/O SPI0 chip-select 2 SPI0_CS219 2822 3118 27112019 15I/OSPI0 chip-select 2 SPI0_CS3 2731 30 2 226 19 218 14 I/O SPI0 chip-select 3 SPI0_CS3273130 2226 1921814I/OSPI0 chip-select 3 SPI0_SCK 10 15 21 13 1824 13 16 20 1013 10 11 13 8 9 I/O SPI0 clock signal input – SPI peripheral mode Clock signal output – SPI controller mode SPI0_SCK10 15 2113 182413 16 20 101310 11 13 8 9I/OSPI0 clock signal input – SPI peripheral mode Clock signal output – SPI controller mode SPI0_POCI 8 14202330 11 1723261 111 1519 22 79121522 191215 111 I/O SPI0 controller in/peripheral out SPI0_POCI8 1420233011 1723261111 1519 22 79121522191215111I/OSPI0 controller in/peripheral out SPI0_PICO 9 13 2229 12162532 12 14 2128 81421 1420 1016 I/O SPI0 controller out/peripheral in SPI0_PICO9 13 22291216253212 14 2128 8142114201016I/OSPI0 controller out/peripheral in System NRST 3 6 6 2 5 4 I Reset input active low SystemNRST3 66 254IReset input active low Timer TIMG0_C0 9 16 2027 12192330 12 1926 1219 1218 14 I/O General purpose timer 0 CCR0 capture input/ compare output TimerTIMG0_C09 16 20271219233012 1926 1219121814I/OGeneral purpose timer 0 CCR0 capture input/ compare output TIMG0_C1 10 17 28 132031 13 27 20 10 19 8 15 I/O General purpose timer 0 CCR1 capture input/ compare output TIMG0_C110 17 2813203113 27 2010 19 8 15I/OGeneral purpose timer 0 CCR1 capture input/ compare output TIMG1_C0 1 111830 414211 1417 2422 14 13 I/O General purpose timer 1 CCR0 capture input/ compare output TIMG1_C01 1118304142111417 24221413I/OGeneral purpose timer 1 CCR0 capture input/ compare output TIMG1_C1 2 6 31 592 25 9 15 25 8 4 7 I/O General purpose timer 1 CCR1 capture input/ compare output TIMG1_C12 6 3159225 9 1525 84 7I/OGeneral purpose timer 1 CCR1 capture input/ compare output TIMG2_C0 7 12 25 101528 10 24 617 – – I/O General purpose timer 2 CCR0 capture input/ compare output TIMG2_C07 12 2510152810 24 617––I/OGeneral purpose timer 2 CCR0 capture input/ compare output TIMG2_C1 8 13 26 111629 11 14 25 7818 9 17 13 I/O General purpose timer 2 CCR1 capture input/ compare output TIMG2_C18 13 2611162911 14 25 78189 1713I/OGeneral purpose timer 2 CCR1 capture input/ compare output TIMG4_C0 14 2124 172427 15 2023 1316 912 I/O General purpose timer 4 CCR0 capture input/ compare output TIMG4_C014 212417242715 20231316912I/OGeneral purpose timer 4 CCR0 capture input/ compare output TIMG4_C1 151922 29 18222532 161821 28 91316 11 14 20 10 16 I/O General purpose timer 4 CCR1 capture input/ compare output TIMG4_C1151922 2918222532161821 28 9131611 14 2010 16I/OGeneral purpose timer 4 CCR1 capture input/ compare output UART UART0_TX 12 21 252729 1524283032 20 242628 13171921 13 1820 9 1416 O UART0 transmit data UARTUART0_TX12 21 252729152428303220 242628 1317192113 18209 1416OUART0 transmit data UART0_RX 13 22 2630 1625291 11421 25 8141822 114 17 110 13 I UART0 receive data UART0_RX13 22 2630162529111421 25 8141822114 17110 13IUART0 receive data UART0_CTS 16 25 27 192830 24 26 1719 18 14 I UART0 "clear to send" flow control input UART0_CTS16 25 2719283024 26 17191814IUART0 "clear to send" flow control input UART0_RTS 17 26 28 202931 25 27 1820 17 19 13 15 O UART0 "request to send" flow control output UART0_RTS17 26 2820293125 27 182017 19 13 15OUART0 "request to send" flow control output UART1_TX 1 141827 4172130 4 151726 24919 418 314 O UART1 transmit data UART1_TX1 14182741721304 151726 24919418314OUART1 transmit data UART1_RX 2 151726 5182029 5 1625 11018 5 1117 413 I UART1 receive data UART1_RX2 15172651820295 1625 110185 1117413IUART1 receive data UART1_CTS 7 13 18 101621 10 14 17 68 – – I UART1 "clear to send" flow control input UART1_CTS7 13 1810162110 14 17 68––IUART1 "clear to send" flow control input UART1_RTS 8 12 19 111522 11 18 711 9 – O UART1 "request to send" flow control output UART1_RTS8 12 1911152211 18 7119–OUART1 "request to send" flow control output Voltage Reference#GUID-3211147C-D305-4A41-84DB-091604D3C64A/EXT_REF VREF+ 27 30 26 19 18 14 I Voltage reference power supply - external reference input Voltage Reference#GUID-3211147C-D305-4A41-84DB-091604D3C64A/EXT_REF #GUID-3211147C-D305-4A41-84DB-091604D3C64A/EXT_REFVREF+27 3026 191814IVoltage reference power supply - external reference input VREF- 25 28 24 17 – – I Voltage reference ground supply - external reference input VREF-25 2824 17––IVoltage reference ground supply - external reference input – = not available I = input, O = output, I/O = input or output, P = power When using VREF+ and VREF- to bring in an external voltage reference for analog peripherals such as the ADC, a decoupling capacitor must be placed on VREF+ to VREF-/GND with a capacitance based on the external reference source – = not availableI = input, O = output, I/O = input or output, P = powerWhen using VREF+ and VREF- to bring in an external voltage reference for analog peripherals such as the ADC, a decoupling capacitor must be placed on VREF+ to VREF-/GND with a capacitance based on the external reference source Connections for Unused Pins #GUID-487452B3-7761-41B1-A78A-1FEF5D273407/GUID-550E8E14-19E0-4BDA-B278-915026A9F746 lists the correct termination of unused pins. Connection of Unused Pins PIN #GUID-487452B3-7761-41B1-A78A-1FEF5D273407/LI_CVM_21L_SQB POTENTIAL COMMENT PAx Open Set corresponding pin functions to GPIO (PINCMx.PF = 0x1) and configure unused pins to output low or input with internal pullup or pulldown resistor. NRST VCC NRST is an active-low reset signal; the pin must be pulled high to VCC or the device cannot start. For more information, see . Any unused pin with a function that is shared with general-purpose I/O must follow the "PAx" unused pin connection guidelines. Connections for Unused Pins #GUID-487452B3-7761-41B1-A78A-1FEF5D273407/GUID-550E8E14-19E0-4BDA-B278-915026A9F746 lists the correct termination of unused pins. Connection of Unused Pins PIN #GUID-487452B3-7761-41B1-A78A-1FEF5D273407/LI_CVM_21L_SQB POTENTIAL COMMENT PAx Open Set corresponding pin functions to GPIO (PINCMx.PF = 0x1) and configure unused pins to output low or input with internal pullup or pulldown resistor. NRST VCC NRST is an active-low reset signal; the pin must be pulled high to VCC or the device cannot start. For more information, see . Any unused pin with a function that is shared with general-purpose I/O must follow the "PAx" unused pin connection guidelines. #GUID-487452B3-7761-41B1-A78A-1FEF5D273407/GUID-550E8E14-19E0-4BDA-B278-915026A9F746 lists the correct termination of unused pins. Connection of Unused Pins PIN #GUID-487452B3-7761-41B1-A78A-1FEF5D273407/LI_CVM_21L_SQB POTENTIAL COMMENT PAx Open Set corresponding pin functions to GPIO (PINCMx.PF = 0x1) and configure unused pins to output low or input with internal pullup or pulldown resistor. NRST VCC NRST is an active-low reset signal; the pin must be pulled high to VCC or the device cannot start. For more information, see . Any unused pin with a function that is shared with general-purpose I/O must follow the "PAx" unused pin connection guidelines. #GUID-487452B3-7761-41B1-A78A-1FEF5D273407/GUID-550E8E14-19E0-4BDA-B278-915026A9F746 lists the correct termination of unused pins.#GUID-487452B3-7761-41B1-A78A-1FEF5D273407/GUID-550E8E14-19E0-4BDA-B278-915026A9F746 Connection of Unused Pins PIN #GUID-487452B3-7761-41B1-A78A-1FEF5D273407/LI_CVM_21L_SQB POTENTIAL COMMENT PAx Open Set corresponding pin functions to GPIO (PINCMx.PF = 0x1) and configure unused pins to output low or input with internal pullup or pulldown resistor. NRST VCC NRST is an active-low reset signal; the pin must be pulled high to VCC or the device cannot start. For more information, see . Connection of Unused Pins PIN #GUID-487452B3-7761-41B1-A78A-1FEF5D273407/LI_CVM_21L_SQB POTENTIAL COMMENT PAx Open Set corresponding pin functions to GPIO (PINCMx.PF = 0x1) and configure unused pins to output low or input with internal pullup or pulldown resistor. NRST VCC NRST is an active-low reset signal; the pin must be pulled high to VCC or the device cannot start. For more information, see . PIN #GUID-487452B3-7761-41B1-A78A-1FEF5D273407/LI_CVM_21L_SQB POTENTIAL COMMENT PIN #GUID-487452B3-7761-41B1-A78A-1FEF5D273407/LI_CVM_21L_SQB POTENTIAL COMMENT PIN #GUID-487452B3-7761-41B1-A78A-1FEF5D273407/LI_CVM_21L_SQB #GUID-487452B3-7761-41B1-A78A-1FEF5D273407/LI_CVM_21L_SQBPOTENTIALCOMMENT PAx Open Set corresponding pin functions to GPIO (PINCMx.PF = 0x1) and configure unused pins to output low or input with internal pullup or pulldown resistor. NRST VCC NRST is an active-low reset signal; the pin must be pulled high to VCC or the device cannot start. For more information, see . PAx Open Set corresponding pin functions to GPIO (PINCMx.PF = 0x1) and configure unused pins to output low or input with internal pullup or pulldown resistor. PAxOpenSet corresponding pin functions to GPIO (PINCMx.PF = 0x1) and configure unused pins to output low or input with internal pullup or pulldown resistor. NRST VCC NRST is an active-low reset signal; the pin must be pulled high to VCC or the device cannot start. For more information, see . NRSTVCCNRST is an active-low reset signal; the pin must be pulled high to VCC or the device cannot start. For more information, see . Any unused pin with a function that is shared with general-purpose I/O must follow the "PAx" unused pin connection guidelines. Any unused pin with a function that is shared with general-purpose I/O must follow the "PAx" unused pin connection guidelines. Specifications Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376819/A_LEGO_LORDBUSINESS_1_ABSMAX_FOOTER1_SF1 MIN MAX UNIT VDD Supply voltage At VDD pin, with respect to VSS –0.3 4.1 V VI Input voltage Applied to any 5-V tolerant open-drain pins –0.3 5.5 V VI Input voltage Applied to any common tolerance pins –0.3 VDD + 0.3 (4.1 MAX) V IVDD Current into VDD pin (source) -40℃ ≤ Tj ≤ 130℃ 80 mA -40℃ ≤ Tj ≤ 85℃ 100 mA IVSS Current out of VSS pin (sink) -40℃ ≤ Tj ≤ 130℃ 80 mA -40℃ ≤ Tj ≤ 85℃ 100 mA IIO Current for SDIO pin Current sunk or sourced by SDIO pin 6 mA Current for HSIO pin Current sunk or sourced by HSIO pin 6 mA Current for ODIO pin Current sunk by ODIO pin 20 mA ID Supported diode current Diode current at any device pin ±2 mA Tj Junction temperature -40 130 °C Tstg Storage temperature#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376819/SF0PLDJ1QO3B –40 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Higher temperatures may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per AEC-Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376820/SFXYZYKTFK_T ±2000 V Charged device model (CDM), per AEC-Q100-011 , All pins ±500 V Charged device model (CDM), per AEC-Q100-011 , Corner pins ±750 V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD Supply voltage #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFSZM16G67.F 1.62#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFJNPATJ6J3M 3.6 V VCORE Voltage on VCORE pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFOKMBJY110E_SF1 1.35 V CVDD Capacitor placed between VDD and VSS #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF8R4NLA4JN._SF1 10 uF CVCORE Capacitor placed between VCORE and VSS #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF8R4NLA4JN._SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFOKMBJY110E_SF1 470 nF TA Ambient temperature, Q version -40 125 °C TJ Max junction temperature, Q version 130 °C fMCLK MCLK, CPUCLK, ULPCLK frequency with 1 flash wait state #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF5LYWVWVU5N_SF1 32 MHz MCLK, CPUCLK, ULPCLK frequency with 0 flash wait states #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF5LYWVWVU5N_SF1 24 Connect CVDD and CVCORE between VDD/VSS and VCORE/VSS, respectively, as close to the device pins as possible. A low-ESR capacitor with at least the specified value and tolerance of ±20% or better is required for CVDD and CVCORE. The VCORE pin must only be connected to CVCORE. Do not supply any voltage or apply any external load to the VCORE pin. Wait states are managed automatically by the system controller (SYSCTL) and do not need to be configured by application software. There is no dependency on MCLK frequency with respect to VDD recommended operating range. Functionality is guaranteed down to VBOR0-(min). Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376825/A_LEGO_LORDBUSINESS_4_THERMAL_FOOTER1 PACKAGE VALUE UNIT RθJA Junction-to-ambient thermal resistance VQFN-32 (RHB) 36.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 28.5 °C/W RθJB Junction-to-board thermal resistance 17.2 °C/W ΨJT Junction-to-top characterization parameter 0.8 °C/W ΨJB Junction-to-board characterization parameter 17.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 6.9 °C/W RθJA Junction-to-ambient thermal resistance VSSOP-32 (DGS32) 72.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 28.3 °C/W RθJB Junction-to-board thermal resistance 37.2 °C/W ΨJT Junction-to-top characterization parameter 1.0 °C/W ΨJB Junction-to-board characterization parameter 37.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W RθJA Junction-to-ambient thermal resistance VSSOP-28 (DGS28) 78.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 38.6 °C/W RθJB Junction-to-board thermal resistance 41.3 °C/W ΨJT Junction-to-top characterization parameter 3.4 °C/W ΨJB Junction-to-board characterization parameter 41.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W RθJA Junction-to-ambient thermal resistance VQFN-24 (RGE) 44.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 38.1 °C/W RθJB Junction-to-board thermal resistance 21.9 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 21.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 7.1 °C/W RθJA Junction-to-ambient thermal resistance VSSOP-20 (DGS20) 91.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 29.3 °C/W RθJB Junction-to-board thermal resistance 48.3 °C/W ΨJT Junction-to-top characterization parameter 0.7 °C/W ΨJB Junction-to-board characterization parameter 47.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W RθJA Junction-to-ambient thermal resistance SOT-16 (DYY) 86.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 39.3 °C/W RθJB Junction-to-board thermal resistance 27.8 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 27.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Supply Current Characteristics RUN/SLEEP Modes VDD=3.3V. All inputs tied to 0V or VDD. Outputs do not source or sink any current. All peripherals are disabled. PARAMETER MCLK -40°C 25°C 85°C 105°C 125°C UNIT TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX RUN Mode IDDRUN MCLK=SYSOSC, CoreMark, execute from flash 32MHz 2.3 2.3 2.3 2.3 2.4 mA 4MHz 0.52 0.52 0.54 0.56 0.60 IDDRUN, per MHz MCLK=SYSOSC, While(1), execute from flash 32MHz 40 48 40 50 41 50 42 51 43 56 uA/Mhz MCLK=SYSOSC, CoreMark, execute from flash 32MHz 72 72 72 73 74 MCLK=SYSOSC, CoreMark, execute from flash 4MHz 130 130 135 140 150 SLEEP Mode IDDSLEEP MCLK=SYSOSC, CPU is halted 32MHz 967 1047 978 1066 1002 1192 1024 1301 1070 1416 uA 4MHz 356 416 363 441 389 577 411 689 458 809 STOP/STANDBY Modes VDD=3.3V unless otherwise noted. All inputs tied to 0V or VDD. Outputs do not source or sink any current. All peripherals not noted are disabled. PARAMETER ULPCLK -40°C 25°C 85°C 105°C 125°C UNIT TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX STOP Mode IDDSTOP0 SYSOSC=32MHz, USE4MHZSTOP=0, DISABLESTOP=0 4MHz 316 342 320 344 323 347 327 352 334 361 uA IDDSTOP1 SYSOSC=4MHz, USE4MHZSTOP=1, DISABLESTOP=0 4MHz 146 167 151 171 155 176 158 182 166 192 IDDSTOP2 SYSOSC off, DISABLESTOP=1, ULPCLK=LFCLK 32kHz 42 51 44 54 47 58 50 64 56 76 STANDBY Mode IDDSTBY0 STOPCLKSTBY=0, TIMG0 enabled 32kHz 1.2 1.3 1.3 1.7 2.7 6.2 4.7 12 11 25 uA IDDSTBY1 STOPCLKSTBY=1, TIMG0 enabled 0.9 1.0 1.0 1.4 2.4 5.9 4.4 12 11 25 STOPCLKSTBY=1, GPIOA enabled 0.9 1.0 1.0 1.4 2.4 5.9 4.4 12 10 25 SHUTDOWN Mode All inputs tied to 0V or VDD. Outputs do not source or sink any current. Core regulator is powered down. PARAMETER VDD -40°C 25°C 85°C 105°C 125°C UNIT TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX IDDSHDN Supply current in SHUTDOWN mode 3.3V 47 61 352 793 2020 nA Power Supply Sequencing POR and BOR over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT dVDD/dt VDD (supply voltage) slew rate Rising 1 V/us Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 0.01 Falling, STANDBY 0.1 V/ms VPOR+ Power-on reset voltage level Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 0.95 1.30 1.51 V VPOR- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 0.9 1.25 1.48 V VHYS, POR POR hysteresis #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 30 45 60 mV VBOR0+, COLD Brown-out reset voltage level 0 (default level) Cold start, rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 1.48 1.54 1.61 V VBOR0+ Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 1.55 1.59 1.62 VBOR0- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 1.54 1.58 1.61 VBOR0, STBY STANDBY mode #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 1.51 1.57 1.61 VBOR1+ Brown-out-reset voltage level 1 Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.13 2.18 2.23 V VBOR1- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.10 2.15 2.19 VBOR2+ Brown-out-reset voltage level 2 Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.73 2.77 2.82 V VBOR2- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.7 2.74 2.79 VBOR3+ Brown-out-reset voltage level 3 Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.88 2.97 3.04 V VBOR3- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.85 2.94 3.01 VHYS,BOR Brown-out reset hysteresis Level 0 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 15 21 mV Levels 1-3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 34 40 TPD, BOR BOR propagation delay RUN/SLEEP/STOP mode 10 us STANDBY mode 100 us \|dVDD/dt\| ≤ 3V/s Device operating in RUN, SLEEP, or STOP mode. Power Supply Ramp shows the relationships of POR-, POR+, BOR0-, and BOR0+ during powerup and powerdown. Power Cycle POR and BOR Conditions Flash Memory Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply VDDPGM/ERASE Program and erase supply voltage 1.62 3.6 V IDDERASE Supply current from VDD during erase operation Supply current delta 2 mA IDDPGM Supply current from VDD during program operation Supply current delta 2.5 mA Endurance NWEC(LOWER) Erase/program cycle endurance (lower 32kB flash) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER1 100 k cycles NWEC(UPPER) Erase/program cycle endurance (remaining flash) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER1 10 k cycles NE(MAX) Total erase operations before failure #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER2 802 k erase operations NW(MAX) Write operations per word line before sector erase #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER3 83 write operations Retention tRET_85 Flash memory data retention -40°C ≤Tj ≤ 85°C 60 years tRET_105 Flash memory data retention -40°C ≤Tj ≤ 105°C 11.4 years Program and Erase Timing tPROG (WORD, 64) Program time for flash word #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SF_BXS133C.K #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SFJ8_0982PVP 50 275 µs tPROG (SEC, 64) Program time for 1kB sector #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SFLOZC2V0Q1K #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SFJ8_0982PVP 6.4 ms tERASE (SEC) Sector erase time ≤2k erase/program cycles, Tj≥25°C 4 20 ms tERASE (SEC) Sector erase time ≤10k erase/program cycles, Tj≥25°C 20 150 ms tERASE (SEC) Sector erase time ≤10k erase/program cycles 20 200 ms tERASE (BANK) Bank erase time ≤10k erase/program cycles 22 220 ms The lower 32kB flash address space supports higher erase/program endurance to enable EEPROM emulation applications. On devices with <=32kB flash memory, the entire flash memory supports NWEC(LOWER) erase/program cycles. Total number of cumulative erase operations supported by the flash before failure. A sector erase or bank erase operation is considered to be one erase operation. Maximum number of write operations allowed per word line before the word line must be erased. If additional writes to the same word line are required, a sector erase is required once the maximum number of write operations per word line is reached. Program time is defined as the time from when the program command is triggered until the command completion interrupt flag is set in the flash controller. Sector program time is defined as the time from when the first word program command is triggered until the final word program command completes and the interrupt flag is set in the flash controller. This time includes the time needed for software to load each flash word (after the first flash word) into the flash controller during programming of the sector. Flash word size is 64 data bits (8 bytes). On devices with ECC, the total flash word size is 72 bits (64 data bits plus 8 ECC bits). Timing Characteristics VDD=3.3V, Ta=25 ℃ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Wakeup Timing tWAKE, SLEEP Wakeup time from SLEEP to RUN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 2 cycles tWAKE, STOP Wakeup time from STOP1 to RUN (SYSOSC enabled) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 14 us Wakeup time from STOP2 to RUN (SYSOSC disabled) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 13 us tWAKE, STBY Wakeup time from STANDBY to RUN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 15 us tWAKE, SHDN Wakeup time from SHUTDOWN to RUN Fast boot enabled 214 us tWAKE, SHDN Wakeup time from SHUTDOWN to RUN Fast boot disabled 230 us Asynchronous Fast Clock Request Timing tDELAY Delay time from edge of asynchronous request to first 32MHz MCLK edge Mode is SLEEP2 0.9 us Mode is STOP1 2.4 us Mode is STOP2 0.9 us Mode is STANDBY1 3.2 us Startup Timing tSTART, RESET Device cold start-up time from reset/power-up #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFQMUUIAC0BH_SF1 Fast boot enabled 241 us Fast boot disabled 284 us NRST Timing tRST, BOOTRST Minimum pulse length on NRST pin to generate BOOTRST ULPCLK≥4MHz 2 us ULPCLK=32kHz 100 us tRST, POR Minimum pulse length on NRST pin to generate POR 1 s The wake-up time is measured from the edge of an external signal (GPIO wake-up event) to the time that the first CPU instruction is executed, with the GPIO glitch filter disabled (FILTEREN=0x0) and fast wake enabled (FASTWAKEONLY=1) The start-up time is measured from the time that VDD crosses VBOR0+ (cold start-up) to the time that the first instruction of the user program is executed. Clock Specifications System Oscillator (SYSOSC) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSYSOSC Factory trimmed SYSOSC frequency SYSOSCCFG.FREQ=00 (BASE) 32 MHz SYSOSCCFG.FREQ=01 4 User trimmed SYSOSC frequency SYSOSCCFG.FREQ=10, SYSOSCTRIMUSER.FREQ=10 24 SYSOSCCFG.FREQ=10, SYSOSCTRIMUSER.FREQ=01 16 SYSOSC frequency accuracy when frequency correction loop (FCL) is enabled and an ideal ROSC resistor is assumed #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SF880TXESCLO SETUSEFCL=1, Ta = 25°C -0.41 0.58 % SETUSEFCL=1, -40°C ≤ Ta ≤ 85°C -0.80 0.93 SETUSEFCL=1, -40°C ≤ Ta ≤ 105°C -0.80 1.09 SETUSEFCL=1, -40°C ≤ Ta ≤ 125°C -0.80 1.30 SYSOSC accuracy when frequency correction loop (FCL) is enabled with ROSC resistor put at ROSC pin, for factory trimmed frequencies #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ SETUSEFCL=1, Ta = 25°C, ±0.1% ±25ppm ROSC –0.5 0.7 % SETUSEFCL=1, -40°C ≤ Ta ≤ 85°C, ±0.1% ±25ppm ROSC –1.1 1.2 SETUSEFCL=1, -40°C ≤ Ta ≤ 105°C, ±0.1% ±25ppm ROSC –1.1 1.4 SETUSEFCL=1, -40°C ≤ Ta ≤ 125°C, ±0.1% ±25ppm ROSC –1.1 1.7 SYSOSC accuracy when frequency correction loop (FCL) is disabled, 32MHz SETUSEFCL=0, SYSOSCCFG.FREQ=00, -40°C ≤ Ta ≤ 125°C –2.6 1.8 % fSYSOSC SYSOSC accuracy when frequency correction loop (FCL) is disabled, for factory trimmed frequencies, 4MHz SETUSEFCL=0, SYSOSCCFG.FREQ=01, -40°C ≤ Ta ≤ 125°C –2.7 2.3 % ROSC External resistor put between ROSC pin and VSS #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ SETUSEFCL=1 100 kΩ tsettle, SYSOSC Settling time to target accuracy #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SF0D42GVUNIM SETUSEFCL=1, ±0.1% 25ppm ROSC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ 30 us fsettle, SYSOSC fSYSOSC additional undershoot accuracy during tsettle #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SF0D42GVUNIM SETUSEFCL=1, ±0.1% 25ppm ROSC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ -11 % The SYSOSC frequency correction loop (FCL) enables high SYSOSC accuracy via an external reference resistor (ROSC) which must be connected between the device ROSC pin and VSS when using the FCL. Accuracies are shown for a ±0.1% ±25ppm ROSC; relaxed tolerance resistors may also be used (with reduced SYSOSC accuracy). See the SYSOSC section of the technical reference manual for details on computing SYSOSC accuracy for various ROSC accuracies. ROSC does not need to be populated if the FCL is not enabled. Represents the device accuracy only. The tolerance and temperature drift of the ROSC resistor used must be combined with this spec to determine final accuracy. Performance for a ±0.1% ±25ppm ROSC is given as a reference point. When SYSOSC is waking up (for example, when exiting a low power mode) and FCL is enabled, the SYSOSC will initially undershoot the target frequency fSYSOSC by an additional error of up to fsettle,SYSOSC for the time tsettle,SYSOSC, after which the target accuracy is achieved. Low Frequency Oscillator (LFOSC) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fLFOSC LFOSC frequency 32768 Hz LFOSC accuracy -40 ℃ ≤ Ta ≤ 125 ℃ –5 5 % -40 ℃ ≤ Ta ≤ 85 ℃ –3 3 % tstart, LFOSC LFOSC start-up time 1.7 ms Digital IO Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH High level input voltage ODIO #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SF72TYWLT.00 VDD ≥ 1.62V 0.7×VDD 5.5 V VDD ≥ 2.7V 2 5.5 V All I/O except ODIO & Reset VDD ≥ 1.62V 0.7×VDD VDD+0.3 V VIL Low level input voltage ODIO VDD ≥ 1.62V -0.3 0.3×VDD V VDD ≥ 2.7V -0.3 0.8 V All I/O except ODIO & Reset VDD ≥ 1.62V -0.3 0.3×VDD V VHYS Hysteresis ODIO 0.05×VDD V All I/O except ODIO 0.1×VDD V Ilkg High-Z leakage current SDIO#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SFX6NSJXZJ1U #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SFDQQ0PR40NZ ±50#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SFNV3RMBMORA nA RPU Pull up resistance All I/O except ODIO 40 kΩ RPD Pull down resistance 40 kΩ CI Input capacitance 5 pF VOH High level output voltage SDIO VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤25 °C VDD-0.4 V VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C VDD-0.45 HSIO VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mA-40 °C ≤Tj≤25 °C VDD-0.4 VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mA-40 °C ≤Tj≤130 °C VDD-0.4 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, DRV = 0, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤25 °C VDD-0.45 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C VDD-0.45 VOL Low level output voltage SDIO VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤25 °C 0.4 V VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C 0.45 HSIO VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mATj≤85 °C 0.4 VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mA-40 °C ≤Tj≤130 °C 0.45 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, DRV = 0, \|IIO\|,max = 1.5mATj≤85 °C 0.4 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, DRV = 0, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C 0.45 ODIO VDD ≥ 2.7V, IOL,max = 8mAVDD ≥ 1.71V, IOL,max = 4mA-40 °C ≤Tj≤25 °C 0.4 VDD ≥ 2.7V, IOL,max = 8mAVDD ≥ 1.71V, IOL,max = 4mA-40 °C ≤Tj≤130 °C 0.45 I/O Types: ODIO = 5V Tolerant Open-Drain , SDIO = Standard-Drive , HSIO = High-Speed The leakage current is measured with VSS or VDD applied to the corresponding pins, unless otherwise noted. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled. This value is for SDIO not muxed with any analog inputs. If the SDIO is muxed with analog inputs then the leakage can be as high as 100nA. Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fmax Port output frequency SDIO #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376799/SFHPZH8IHV7S VDD ≥ 1.71V, CL= 20pF 16 MHz VDD ≥ 2.7V, CL = 20pF 32 HSIO VDD ≥ 1.71V, DRV = 0, CL = 20pF 16 VDD ≥ 1.71V, DRV = 1, CL = 20pF 24 VDD ≥ 2.7V, DRV = 0, CL = 20pF 32 ODIO VDD ≥ 1.71V, FM+, CL = 20pF - 100pF 1 tr,tf Output rise/fall time All output ports except ODIO VDD ≥ 1.71V 0.3×fmax s tf Output fall time ODIO VDD ≥ 1.71V, FM+, CL = 20pF to 100pF 20×VDD/5.5 120 ns I/O Types: ODIO = 5V Tolerant Open-Drain , SDIO = Standard-Drive , HSIO = High-Speed Analog Mux VBOOST over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IVBST VBOOST current adder MCLK/ULPCLK is LFCLK 0.8 uA MCLK/ULPCLK is not LFCLK, SYSOSC frequency is 4MHz 8.5 tSTART,VBST VBOOST startup time 12 us ADC Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted), all TYP values are measured at 25℃ and all accuracy parameters are measured using 12-bit resolution mode (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vin(ADC) Analog input voltage range#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SF.FIOPY1XB3_SF2 Applies to all ADC analog input pins 0 VDD V VR+ Positive ADC reference voltage VR+ sourced from VDD VDD V VR+ sourced from external reference pin (VREF+) 1.4 VDD V VR+ sourced from internal reference (VREF) VREF V VR- Negative ADC reference voltage 0 V FS ADC sampling frequency RES = 0x0 (12-bit mode), External Reference 1.68 Msps I(ADC) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/TG47888388372_SF2 Operating supply currentinto VDD terminal FS = 1MSPS, Internal reference OFF, VR+ = VDD 454 600 μA FS = 200ksps, Internal reference ON, VR+ = VREF = 2.5V 300 435 CS/H ADC sample-and-hold capacitance 3.3 7 pF Rin ADC sampling switch resistance 0.5 1 kΩ ENOB Effective number of bits Internal reference, VR+ = VREF = 2.5V, Fin = 10KHz 10 10.2 bit External reference, Fin = 10KHz #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2 11 11.1 SNR Signal-to-noise ratio External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2 68 71 dB Internal reference, VR+ = VREF = 2.5V 63 65 PSRRDC Power supply rejection ratio, DC External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2, VDD = VDD(min) to VDD(max) 63 68 dB VDD = VDD(min) to VDD(max) Internal reference, VR+ = VREF = 2.5V 49 55 PSRRAC Power supply rejection ratio, AC External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2, ΔVDD = 0.1 V at 1 kHz 61 dB ΔVDD = 0.1 V at 1 kHzInternal reference, VR+ = VREF = 2.5V 49 Twakeup ADC Wakeup Time Assumes internal reference is active 1 us VSupplyMon Supply Monitor voltage divider (VDD/3) accuracy ADC input channel: Supply Monitor #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SF34MRTUPYCS_SF2 -1.5 +1.5 % ISupplyMon Supply Monitor voltage divider current consumption ADC input channel: Supply Monitor 10 uA The analog input voltage range must be within the selected ADC reference voltage range VR+ to VR– for valid conversion results. The internal reference (VREF) supply current is not included in current consumption parameter I(ADC). All external reference specifications are measured with VR+ = VREF+ = VDD = 3.3V and VR- = VREF- = VSS = 0V and external 1uF cap on VREF+ pin Analog power supply monitor. Analog input on channel 15 is disconnected and is internally connected to the voltage divider which is VDD/3. Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fADCCLK ADC clock frequency 4 32 MHz tADC trigger Software trigger minimum width 3 ADCCLK cycles tSample Sampling time without OPA 12-bit mode, RS = 50Ω, Cpext = 10pF 156 ns tSample_PGA Sampling time with OPA #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376828/SFDY6E128LC3_SF1 12-bit mode GBW = 0x1, PGA gain = x1 0.31 µs GBW = 0x1, PGA gain = x32 1.5 µs tSample_GPAMP Sampling time with GPAMP 12-bit mode 2.5 µs tSample_SupplyMon Sample time with Supply Monitor (VDD/3) 12-bit mode 3 µs Only applies for devices with OPA Linearity Parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted), all TYP values are measured at 25℃ and all linearity parameters are measured using 12-bit resolution mode (unless otherwise noted) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFQ2EE8MT8H7_SF2 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EI Integral linearity error (INL) External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -2.0 +2.0 LSB ED Differential linearity error (DNL)Guaranteed no missing codes External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -1.0 +1.0 LSB EO Offset error External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -3 3 mV Internal reference, VR+ = VREF = 2.5V -3 3 mV EG Gain error External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -3 3 LSB Total Unadjusted Error (TUE) can be calculated from EI , EO , and EG using the following formula: TUE = √( EI 2 + \|EO\|2 + EG 2 )Note: You must convert all of the errors into the same unit, usually LSB, for the above equation to be accurate All external reference specifications are measured with VR+ = VREF+ = VDD = 3.3V and VR- = VREF- = VSS = 0V and external 1uF cap on VREF+ pin Typical Connection Diagram ADC Input Network Refer to ADC Electrical Characteristics for the values of Rin and CS/H Refer to Digital IO Electrical Characteristics for the value of CI Cpar and Rpar represent the parasitic capacitance and resistance of the external ADC input circuitry Use the following equations to solve for the minimum sampling time (T) required for an ADC conversion: Tau = (Rpar + Rin) × CS/H + Rpar × (Cpar + CI) K= ln(2n/Settling error) – ln((Cpar + CI)/CS/H) T (Min sampling time) = K × Tau Temperature Sensor over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TSTRIM Factory trim temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376811/SF6JDHGGO20J ADC and VREF configuration: RES=0 (12-bit mode), VRSEL=2h (internal VREF), BUFCONFIG=1h (1.4V VREF), ADC tSample=12.5µs 27 30 33 ℃ TSc Temperature coefficient -1.84 -1.75 -1.66 mV/℃ tSET, TS Temperature sensor settling time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376811/SFS6639BTC85 2.5 10 us Higher absolute accuracy may be achieved through user calibration. This is the maximum time required for the temperature sensor to settle when measured by the ADC. It may be used to specify the minimum ADC sample time when measuring the temperature sensor. VREF Voltage Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDDmin Minimum supply voltage needed for VREF operation BUFCONFIG = 1 1.62 V BUFCONFIG = 0 2.7 VREF Voltage reference output voltage BUFCONFIG = 1 1.379 1.4 1.421 V BUFCONFIG = 0 2.462 2.5 2.538 Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IVREF VREF operating supply current BUFCONFIG = {0, 1}, No load 74 100 µA TCVREF Temperature coefficient of VREF #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376815/A_SF_TM_VREF_ELECTRICAL_CHARACTERISTICS_FOOTER1_SF1 BUFCONFIG = {0, 1} 200 ppm/°C TCdrift Long term VREF drift Time = 1000 hours, BUFCONFIG = {0, 1}, T = 25℃ 300 ppm PSRRDC VREF Power supply rejection ratio, DC VDD = 1.7 V to VDDmax, BUFCONFIG = 1 59 64 dB VDD = 2.7 V to VDDmax, BUFCONFIG = 0 49 53 Vnoise RMS noise at VREF output (0.1 Hz to 100 MHz) BUFFCONFIG = 1 500 µVrms BUFFCONFIG = 0 750 ADC FS Max supported ADC sampling frequency Using VREF as ADC reference 200 ksps Tstartup VREF startup time BUFCONFIG = {0, 1} , VDD = 2.8 V 15 us The temperature coefficient of the VREF output is the sum of TCVRBUF and the temperature coefficient of the internal bandgap reference. COMP Comparator Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Comparator Electrical Characteristics Vcm Common mode input range 0 VDD V Voffset Input offset voltage ±25 mV Vhys DC input hysteresis HYST=00h 0.4 mV HYST=01h 11 HYST=02h 20 HYST=03h 30 tPD_ls Propagation delay, response time Output Filter off, Overdrive = 100 mV, High Speed Mode 32 50 ns Output Filter off, Overdrive = 100 mV, Low Power Mode 5 µs ten Comparator enable time Startup time to reach propagation delay specification, High Speed Mode 10 µs Startup time to reach propagation delay specification, Low Power Mode 10 µs Icomp Comparator current consumption. Vcm = VDD/2, 100mV overdrive, DAC output as a voltage reference, VDD is reference for DAC, High Speed Mode 120 200 µA Vcm = VDD/2, 100mV overdrive, DAC output as a voltage reference, VDD is reference for DAC, Low Power Mode 0.8 2.7 µA Vcm = VDD/2, 100mV overdrive, comparator only. High Speed Mode 100 180 µA Vcm = VDD/2, 100mV overdrive, comparator only, Low Power Mode 0.7 2.1 µA 8-bit DAC Electrical Characteristics Vdac DAC output range 0 VDD V Vdac-code 8-bit DAC output voltage for a given code VIN = reference voltage into 8-bit DAC, code n = 0 to 255 VIN × (n+1) / 256 V INL Integral nonlinearity of 8-bit DAC -1 1 LSB DNL Differential nonlinearity of 8-bit DAC -1 1 LSB Gain error Gain error of 8-bit DAC Reference voltage = VDD -2 2 % of FSR Offset error Offset error of 8-bit DAC -5 5 mV tdac_settle 8-bit DAC settling time in static mode DACCODE0 = 0 → 255, DAC output accurate to 1 LSB 1.5 µs GPAMP Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCM Common mode voltage range RRI = 0x0 -0.1 VDD–1 V RRI = 0x1 1 VDD-0.2 RRI = 0x2 -0.1 VDD-0.2 Iq Quiescent current, per op-amp IO= 0 mA, RRI = 0x0 97 µA IO= 0 mA, RRI = 0x1 or 0x2 93 GBW Gain-bandwidth product CL = 200pF 0.32 MHz VOS Input offset voltage Noninverting, unity gain, TA = 25℃, VDD = 3.3V CHOPCLKMODE = 0x0 ±0.2 ±6.5 mV CHOPCLKMODE = 0x1 ±0.08 ±0.4 dVOS/dT Input offset voltage temperature drift Noninverting, unity gain CHOPCLKMODE = 0x0 7.7 µV/°C CHOPCLKMODE = 0x1 0.34 Ibias Input bias for muxed I/O pin at SoC 0.1V<Vin<VDD-0.3V, VDD=3.3V, CHOPCLKMODE=0x0 TA = 25°C ±40 pA TA = 125°C ±4000 0.1V<Vin<VDD-0.3V, VDD=3.3V, CHOPCLKMODE=0x1 TA = 25°C ±200 TA = 125°C ±4000 CMRRDC Common mode rejection ratio, DC Over common mode voltage range CHOPCLKMODE = 0x0 48 77 dB CHOPCLKMODE = 0x1 56 105 en Input voltage noise density Noninverting, unity gain f = 1 kHz 43 nV/√Hz f = 10 kHz 19 Rin Input resistance #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376816/SF.OB27_BQRM_SF1 0.65 kΩ Cin Input capacitance Common mode 4 pF Differential 2 AOL Open-loop voltage gain, DC RL = 350 kΩ, 0.3 < Vo < VDD-0.3 82 90 107 dB PM phase margin CL = 200 pF, RL= 350 kΩ 69 70 72 degree SR Slew rate Noninverting, unity gain, CL = 40 pF 0.32 V/µs THDN Total Harmonic Distortion + Noise 0.012 % ILoad Output load current ±4 mA CLoad Output load capacitance 200 pF The term 'Rin' refers to the input resistance of the multiplexer (mux) in the GPAMP. Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tEN GPAMP enable time ENABLE = 0x0 to 0x1, Bandgap reference ON, 0.1% Noninverting, unity gain 12 20 µs tdisable GPAMP disable time 4 ULPCLK Cycles tSETTLE GPAMP settling time CL = 200 pF, Vstep = 0.3V to VDD - 0.3V, 0.1%, ENABLE = 0x1 Noninverting, unity gain 9 µs OPA Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCM Common mode voltage range RRI = 0x0 -0.1 VDD-1.1 V RRI = 0x1 -0.1 VDD-0.3 VO Voltage output swing from rail range RL = 10kΩ connected to VDD/2 20 68 mV Iq Quiescent current, per op-amp #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376800/SFNBH0LJNI8Z IO= 0mA, RRI = 0x0 GBW = 0x0 100 µA GBW = 0x1 350 IO= 0mA, RRI = 0x1 GBW = 0x0 140 170 GBW = 0x1 450 600 IBCS Burn-out current source current 2 µA GBW Gain-bandwidth product Noninverting, unity gain,CL = 40 pF GBW = 0x0 1.5 MHz GBW = 0x1 6 VOS Input offset voltage Noninverting, unity gain, VDD = 3.3V, TA = 25°C CHOP = 0x0 ±0.4 ±2 mV CHOP = 0x1 or 0x2 ±0.3 Noninverting, unity gain, VDD = 3.3V CHOP = 0x0 ±1.5 ±3.5 CHOP = 0x1 or 0x2 ±0.1 ±0.5 dVOS/dT Input offset voltage temperature drift Noninverting, unity gain, CHOP = 0x0 GBW = 0x0 ±8.5 µV/°C GBW = 0x1 ±6 Noninverting, unity gain, CHOP = 0x1 or 0x2 ±0.5 PSRRDC Power Supply Rejection Ratio, DC Noninverting, unity gain CHOP = 0x0 74 86 dB CHOP = 0x1 or 0x2 74 86 Ibias Input bias current for dedicated OPA input pin 0.1V<Vin<VDD-0.3V, VDD = 3.3V, CHOP=0x0 TA = 25°C ±6 pA TA = 125°C ±0.35 ±0.4 nA 0.1V<Vin<VDD-0.3V, VDD = 3.3V, CHOP=0x1 TA = 25°C ±0.4 nA TA = 125°C ±0.4 ±0.5 nA CMRRDC Common mode rejection ratio, DC RRI = 0x0: 0V<VCM<VDD-1.1VRRI = 0x1: 0V<VCM<VDD-0.3V CHOP = 0x0 89 dB CHOP = 0x1 or 0x2 73 102 en Input voltage noise density GBW = 0x0, Noninverting, unity gain, CHOP = 0x0 f = 1kHz 240 nV/√Hz f = 10kHz 88 Rin Input resistance #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376800/SFN2NS4M4XOF 2.6 kΩ Cin Input capacitance Common mode 3 pF AOL Open-loop voltage gain, DC RL = 20kΩ to GND, 0.3<Vo<VDD-0.3 105 dB PM phase margin CL = 40pF GBW = 0x0 57 degree GBW = 0x1 50 SR Slew rate Noninverting, unity gain, CL = 40 pF GBW = 0x0 1.3 V/µs GBW = 0x1 4.9 THDN Total harmonic distortion + noise Noninverting, unity gain, GBW = 0x0, f = 1.5kHz, Integration BW = 100kHz 0.0034 % Noninverting, unity gain, GBW = 0x1, f = 6kHz, Integration BW = 100kHz 0.004 ILoad Short circuit current GBW = 0x0, TA = 25°C ±9 mA GBW = 0x1, TA = 25°C ±30 CLoad Output load capacitance 40 pF Rin here means the input resistance of mux in OPA. Excluding VBOOST current. VBOOST must be enabled when OPA is enabled. Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tEN OPA enable time ENABLE = 0x0 to 0x1, Bandgap reference ON, 0.1%, Noninverting, unity gain GBW = 0x0 7.3 12 µs GBW = 0x1 4.4 6 tdisable OPA disable time 4 ULPCLK cycles fCHOP OPA Chopping Frequency CHOP = 0x1 GAIN = 0x0 125 kHz GAIN = 0x1 62.5 GAIN = 0x2 31.25 GAIN = 0x3 15.625 GAIN = 0x4 7.8 GAIN = 0x5 3.9 tSETTLE OPA settling time CL = 40 pF, Vstep = 0.3V to VDD-0.3V, 0.1%, ENABLE = 0x1, Noninverting, unity gain GBW = 0x0 2.5 9 µs GBW = 0x1 1.3 5 PGA Mode over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT G Non- inverting gain accuracy Buffer Mode #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376802/SFSHW.CA2PDZ Unity Gain -0.05 +0.05 % GAIN = 0x1 Gain of 2 -0.6 +0.6 % GAIN = 0x2 Gain of 4 –0.8 +0.8 GAIN = 0x3 Gain of 8 –1 +1 GAIN = 0x4 Gain of 16 –1.5 1.5 GAIN = 0x5 Gain of 32 –2.6 +2.6 Inverting gain accuracy GAIN = 0x1 Gain of -1 –0.8 +0.8 GAIN = 0x2 Gain of -3 –1.0 +1.0 GAIN = 0x3 Gain of -7 –1.2 1.2 GAIN = 0x4 Gain of -15 –1.5 1.5 GAIN = 0x5 Gain of -31 –2.7 2.7 RPGA Programmable gain stage resistance GAIN = 0x1 R1 64 kΩ R2 (feedback resistor) 64 GAIN = 0x2 R1 32 R2 (feedback resistor) 96 GAIN = 0x3 R1 16 R2 (feedback resistor) 112 GAIN = 0x4 R1 8 R2 (feedback resistor) 120 GAIN = 0x5 R1 4 R2 (feedback resistor) 124 G/dV Gain supply drift 0.026 0.84 %/V G/dT Gain temperature drift 0.0007 0.014 %/C THD Total harmonic distortion f = 3kHz, RL = 1.5kOhm to VDD/2, GBW = 0x1, GAIN = 0x1 88 dB f = 188Hz, RL = 1.5kOhm to VDD/2, GBW = 0x1, GAIN = 0x5 61 OPA operates with unity gain in buffer mode, providing impedance matching and signal buffering without the amplification. I2C I2C Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS Standard mode Fast mode Fast mode plus UNIT MIN MAX MIN MAX MIN MAX fI2C I2C input clock frequency I2C in Power Domain0 2 32 8 32 20 32 MHz fSCL SCL clock frequency 0.1 0.4 1 MHz tHD,STA Hold time (repeated) START 4 0.6 0.26 us tLOW Low period of the SCL clock 4.7 1.3 0.5 us tHIGH High period of the SCL clock 4 0.6 0.26 us tSU,STA Setup time for a repeated START 4.7 0.6 0.26 us tHD,DAT Data hold time 0 0 0 ns tSU,DAT Data setup time 250 100 50 ns tSU,STO Setup time for STOP 4 0.6 0.26 us tBUF Bus free time between a STOP and START condition 4.7 1.3 0.5 us tVD;DAT Data valid time 3.45 0.9 0.45 us tVD;ACK Data valid acknowledge time 3.45 0.9 0.45 us I2C Filter over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT fSP Pulse duration of spikes suppressed by input filter AGFSELx = 0 6 ns AGFSELx = 1 14 35 ns AGFSELx = 2 22 60 ns AGFSELx = 3 35 90 ns I²C Timing Diagram I2C Timing Diagram SPI SPI over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT SPI fSPI SPI clock frequency Clock max speed = 32MHz1.62 < VDD < 3.6VController mode 16 MHz fSPI SPI clock frequency Clock max speed = 32MHz1.62 < VDD < 3.6VPeripheral mode 16 MHz DCSCK SCK Duty Cycle 40 50 60 % Controller tSCLK_H/L SCLK High or Low time (tSPI/2) - 1 tSPI / 2 (tSPI/2) + 1 ns tSU.CI POCI input data setup time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFE3FRNWR5LF 2.7 < VDD < 3.6V, delayed sampling enabled 1 ns 1.62 < VDD < 2.7V, delayed sampling enabled 1 tSU.CI POCI input data setup time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFE3FRNWR5LF 2.7 < VDD < 3.6V, no delayed sampling 27 ns 1.62 < VDD < 2.7V, no delayed sampling 35 tHD.CI POCI input data hold time 9 ns tVALID.CO PICO output data valid time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFR2FE1H6R5J 10 ns tHD.CO PICO output data hold time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFGGI3_DYZFT 1 ns Peripheral tCS.LEAD CS lead-time, CS active to clock 8 ns tCS.LAG CS lag time, Last clock to CS inactive 1 ns tCS.ACC CS access time, CS active to POCI data out 23 ns tCS.DIS CS disable time, CS inactive to POCI high impedance 19 ns tSU.PI PICO input data setup time 7 ns tHD.PI PICO input data hold time 31.25 ns tVALID.PO POCI output data valid time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFR2FE1H6R5J 2.7 < VDD < 3.6V 24 ns tVALID.PO POCI output data valid time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFR2FE1H6R5J 1.62 < VDD < 2.7V 31 ns tHD.PO POCI output data hold time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFGGI3_DYZFT 5 ns The POCI input data setup time can be fully compensated when delayed sampling feature is enabled. Specifies the time to drive the next valid data to the output after the output changing SCLK clock edge Specifies how long data on the output is valid after the output changing SCLK clock edge SPI Timing Diagram SPI Timing Diagram - Controller Mode SPI Timing Diagram - Peripheral Mode UART over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT fUART UART input clock frequency 32 MHz fBITCLK BITCLK clock frequency(equals baud rate in MBaud) 4 MHz tSP Pulse duration of spikes suppressed by input filter AGFSELx = 0 6 ns AGFSELx = 1 14 35 ns AGFSELx = 2 22 60 ns AGFSELx = 3 35 90 ns TIMx over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT tres Timer resolution time fTIMxCLK = 32MHz 31.25 ns 1 tTIMxCLK tres Timer resolution time TIMx with 16bit counter 16 bit tCOUNTER 16-bit counter clock period fTIMxCLK = 32MHz 0.03125 2048 us 1 65536 tTIMxCLK Emulation and Debug SWD Timing over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSWD SWD frequency 10 MHz Specifications Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376819/A_LEGO_LORDBUSINESS_1_ABSMAX_FOOTER1_SF1 MIN MAX UNIT VDD Supply voltage At VDD pin, with respect to VSS –0.3 4.1 V VI Input voltage Applied to any 5-V tolerant open-drain pins –0.3 5.5 V VI Input voltage Applied to any common tolerance pins –0.3 VDD + 0.3 (4.1 MAX) V IVDD Current into VDD pin (source) -40℃ ≤ Tj ≤ 130℃ 80 mA -40℃ ≤ Tj ≤ 85℃ 100 mA IVSS Current out of VSS pin (sink) -40℃ ≤ Tj ≤ 130℃ 80 mA -40℃ ≤ Tj ≤ 85℃ 100 mA IIO Current for SDIO pin Current sunk or sourced by SDIO pin 6 mA Current for HSIO pin Current sunk or sourced by HSIO pin 6 mA Current for ODIO pin Current sunk by ODIO pin 20 mA ID Supported diode current Diode current at any device pin ±2 mA Tj Junction temperature -40 130 °C Tstg Storage temperature#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376819/SF0PLDJ1QO3B –40 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Higher temperatures may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376819/A_LEGO_LORDBUSINESS_1_ABSMAX_FOOTER1_SF1 MIN MAX UNIT VDD Supply voltage At VDD pin, with respect to VSS –0.3 4.1 V VI Input voltage Applied to any 5-V tolerant open-drain pins –0.3 5.5 V VI Input voltage Applied to any common tolerance pins –0.3 VDD + 0.3 (4.1 MAX) V IVDD Current into VDD pin (source) -40℃ ≤ Tj ≤ 130℃ 80 mA -40℃ ≤ Tj ≤ 85℃ 100 mA IVSS Current out of VSS pin (sink) -40℃ ≤ Tj ≤ 130℃ 80 mA -40℃ ≤ Tj ≤ 85℃ 100 mA IIO Current for SDIO pin Current sunk or sourced by SDIO pin 6 mA Current for HSIO pin Current sunk or sourced by HSIO pin 6 mA Current for ODIO pin Current sunk by ODIO pin 20 mA ID Supported diode current Diode current at any device pin ±2 mA Tj Junction temperature -40 130 °C Tstg Storage temperature#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376819/SF0PLDJ1QO3B –40 150 °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Higher temperatures may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376819/A_LEGO_LORDBUSINESS_1_ABSMAX_FOOTER1_SF1 MIN MAX UNIT VDD Supply voltage At VDD pin, with respect to VSS –0.3 4.1 V VI Input voltage Applied to any 5-V tolerant open-drain pins –0.3 5.5 V VI Input voltage Applied to any common tolerance pins –0.3 VDD + 0.3 (4.1 MAX) V IVDD Current into VDD pin (source) -40℃ ≤ Tj ≤ 130℃ 80 mA -40℃ ≤ Tj ≤ 85℃ 100 mA IVSS Current out of VSS pin (sink) -40℃ ≤ Tj ≤ 130℃ 80 mA -40℃ ≤ Tj ≤ 85℃ 100 mA IIO Current for SDIO pin Current sunk or sourced by SDIO pin 6 mA Current for HSIO pin Current sunk or sourced by HSIO pin 6 mA Current for ODIO pin Current sunk by ODIO pin 20 mA ID Supported diode current Diode current at any device pin ±2 mA Tj Junction temperature -40 130 °C Tstg Storage temperature#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376819/SF0PLDJ1QO3B –40 150 °C over operating free-air temperature range (unless otherwise noted)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376819/A_LEGO_LORDBUSINESS_1_ABSMAX_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376819/A_LEGO_LORDBUSINESS_1_ABSMAX_FOOTER1_SF1 MIN MAX UNIT VDD Supply voltage At VDD pin, with respect to VSS –0.3 4.1 V VI Input voltage Applied to any 5-V tolerant open-drain pins –0.3 5.5 V VI Input voltage Applied to any common tolerance pins –0.3 VDD + 0.3 (4.1 MAX) V IVDD Current into VDD pin (source) -40℃ ≤ Tj ≤ 130℃ 80 mA -40℃ ≤ Tj ≤ 85℃ 100 mA IVSS Current out of VSS pin (sink) -40℃ ≤ Tj ≤ 130℃ 80 mA -40℃ ≤ Tj ≤ 85℃ 100 mA IIO Current for SDIO pin Current sunk or sourced by SDIO pin 6 mA Current for HSIO pin Current sunk or sourced by HSIO pin 6 mA Current for ODIO pin Current sunk by ODIO pin 20 mA ID Supported diode current Diode current at any device pin ±2 mA Tj Junction temperature -40 130 °C Tstg Storage temperature#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376819/SF0PLDJ1QO3B –40 150 °C MIN MAX UNIT MIN MAX UNIT MINMAXUNIT VDD Supply voltage At VDD pin, with respect to VSS –0.3 4.1 V VI Input voltage Applied to any 5-V tolerant open-drain pins –0.3 5.5 V VI Input voltage Applied to any common tolerance pins –0.3 VDD + 0.3 (4.1 MAX) V IVDD Current into VDD pin (source) -40℃ ≤ Tj ≤ 130℃ 80 mA -40℃ ≤ Tj ≤ 85℃ 100 mA IVSS Current out of VSS pin (sink) -40℃ ≤ Tj ≤ 130℃ 80 mA -40℃ ≤ Tj ≤ 85℃ 100 mA IIO Current for SDIO pin Current sunk or sourced by SDIO pin 6 mA Current for HSIO pin Current sunk or sourced by HSIO pin 6 mA Current for ODIO pin Current sunk by ODIO pin 20 mA ID Supported diode current Diode current at any device pin ±2 mA Tj Junction temperature -40 130 °C Tstg Storage temperature#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376819/SF0PLDJ1QO3B –40 150 °C VDD Supply voltage At VDD pin, with respect to VSS –0.3 4.1 V VDDSupply voltageAt VDD pin, with respect to VSS–0.34.1V VI Input voltage Applied to any 5-V tolerant open-drain pins –0.3 5.5 V VI IInput voltageApplied to any 5-V tolerant open-drain pins–0.35.5V VI Input voltage Applied to any common tolerance pins –0.3 VDD + 0.3 (4.1 MAX) V VI IInput voltageApplied to any common tolerance pins–0.3VDD + 0.3 (4.1 MAX)DDV IVDD Current into VDD pin (source) -40℃ ≤ Tj ≤ 130℃ 80 mA IVDD VDDCurrent into VDD pin (source)-40℃ ≤ Tj ≤ 130℃80mA -40℃ ≤ Tj ≤ 85℃ 100 mA -40℃ ≤ Tj ≤ 85℃100mA IVSS Current out of VSS pin (sink) -40℃ ≤ Tj ≤ 130℃ 80 mA IVSS VSSCurrent out of VSS pin (sink)-40℃ ≤ Tj ≤ 130℃80mA -40℃ ≤ Tj ≤ 85℃ 100 mA -40℃ ≤ Tj ≤ 85℃100mA IIO Current for SDIO pin Current sunk or sourced by SDIO pin 6 mA IIO IOCurrent for SDIO pinCurrent sunk or sourced by SDIO pin6mA Current for HSIO pin Current sunk or sourced by HSIO pin 6 mA Current for HSIO pinCurrent sunk or sourced by HSIO pin6mA Current for ODIO pin Current sunk by ODIO pin 20 mA Current for ODIO pinCurrent sunk by ODIO pin20mA ID Supported diode current Diode current at any device pin ±2 mA ID DSupported diode currentDiode current at any device pin±2mA Tj Junction temperature -40 130 °C TjJunction temperature-40130°C Tstg Storage temperature#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376819/SF0PLDJ1QO3B –40 150 °C Tstg stgStorage temperature#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376819/SF0PLDJ1QO3B #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376819/SF0PLDJ1QO3B–40150°C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Higher temperatures may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.Absolute Maximum RatingRecommended Operating ConditionHigher temperatures may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per AEC-Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376820/SFXYZYKTFK_T ±2000 V Charged device model (CDM), per AEC-Q100-011 , All pins ±500 V Charged device model (CDM), per AEC-Q100-011 , Corner pins ±750 V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. ESD Ratings VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per AEC-Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376820/SFXYZYKTFK_T ±2000 V Charged device model (CDM), per AEC-Q100-011 , All pins ±500 V Charged device model (CDM), per AEC-Q100-011 , Corner pins ±750 V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per AEC-Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376820/SFXYZYKTFK_T ±2000 V Charged device model (CDM), per AEC-Q100-011 , All pins ±500 V Charged device model (CDM), per AEC-Q100-011 , Corner pins ±750 V VALUE UNIT V(ESD) Electrostatic discharge Human body model (HBM), per AEC-Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376820/SFXYZYKTFK_T ±2000 V Charged device model (CDM), per AEC-Q100-011 , All pins ±500 V Charged device model (CDM), per AEC-Q100-011 , Corner pins ±750 V VALUE UNIT VALUE UNIT VALUEUNIT V(ESD) Electrostatic discharge Human body model (HBM), per AEC-Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376820/SFXYZYKTFK_T ±2000 V Charged device model (CDM), per AEC-Q100-011 , All pins ±500 V Charged device model (CDM), per AEC-Q100-011 , Corner pins ±750 V V(ESD) Electrostatic discharge Human body model (HBM), per AEC-Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376820/SFXYZYKTFK_T ±2000 V V(ESD) (ESD)Electrostatic dischargeHuman body model (HBM), per AEC-Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376820/SFXYZYKTFK_T #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376820/SFXYZYKTFK_T±2000V Charged device model (CDM), per AEC-Q100-011 , All pins ±500 V Charged device model (CDM), per AEC-Q100-011 , All pins±500V Charged device model (CDM), per AEC-Q100-011 , Corner pins ±750 V Charged device model (CDM), per AEC-Q100-011 , Corner pins±750V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD Supply voltage #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFSZM16G67.F 1.62#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFJNPATJ6J3M 3.6 V VCORE Voltage on VCORE pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFOKMBJY110E_SF1 1.35 V CVDD Capacitor placed between VDD and VSS #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF8R4NLA4JN._SF1 10 uF CVCORE Capacitor placed between VCORE and VSS #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF8R4NLA4JN._SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFOKMBJY110E_SF1 470 nF TA Ambient temperature, Q version -40 125 °C TJ Max junction temperature, Q version 130 °C fMCLK MCLK, CPUCLK, ULPCLK frequency with 1 flash wait state #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF5LYWVWVU5N_SF1 32 MHz MCLK, CPUCLK, ULPCLK frequency with 0 flash wait states #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF5LYWVWVU5N_SF1 24 Connect CVDD and CVCORE between VDD/VSS and VCORE/VSS, respectively, as close to the device pins as possible. A low-ESR capacitor with at least the specified value and tolerance of ±20% or better is required for CVDD and CVCORE. The VCORE pin must only be connected to CVCORE. Do not supply any voltage or apply any external load to the VCORE pin. Wait states are managed automatically by the system controller (SYSCTL) and do not need to be configured by application software. There is no dependency on MCLK frequency with respect to VDD recommended operating range. Functionality is guaranteed down to VBOR0-(min). Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD Supply voltage #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFSZM16G67.F 1.62#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFJNPATJ6J3M 3.6 V VCORE Voltage on VCORE pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFOKMBJY110E_SF1 1.35 V CVDD Capacitor placed between VDD and VSS #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF8R4NLA4JN._SF1 10 uF CVCORE Capacitor placed between VCORE and VSS #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF8R4NLA4JN._SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFOKMBJY110E_SF1 470 nF TA Ambient temperature, Q version -40 125 °C TJ Max junction temperature, Q version 130 °C fMCLK MCLK, CPUCLK, ULPCLK frequency with 1 flash wait state #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF5LYWVWVU5N_SF1 32 MHz MCLK, CPUCLK, ULPCLK frequency with 0 flash wait states #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF5LYWVWVU5N_SF1 24 Connect CVDD and CVCORE between VDD/VSS and VCORE/VSS, respectively, as close to the device pins as possible. A low-ESR capacitor with at least the specified value and tolerance of ±20% or better is required for CVDD and CVCORE. The VCORE pin must only be connected to CVCORE. Do not supply any voltage or apply any external load to the VCORE pin. Wait states are managed automatically by the system controller (SYSCTL) and do not need to be configured by application software. There is no dependency on MCLK frequency with respect to VDD recommended operating range. Functionality is guaranteed down to VBOR0-(min). over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD Supply voltage #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFSZM16G67.F 1.62#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFJNPATJ6J3M 3.6 V VCORE Voltage on VCORE pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFOKMBJY110E_SF1 1.35 V CVDD Capacitor placed between VDD and VSS #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF8R4NLA4JN._SF1 10 uF CVCORE Capacitor placed between VCORE and VSS #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF8R4NLA4JN._SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFOKMBJY110E_SF1 470 nF TA Ambient temperature, Q version -40 125 °C TJ Max junction temperature, Q version 130 °C fMCLK MCLK, CPUCLK, ULPCLK frequency with 1 flash wait state #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF5LYWVWVU5N_SF1 32 MHz MCLK, CPUCLK, ULPCLK frequency with 0 flash wait states #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF5LYWVWVU5N_SF1 24 over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD Supply voltage #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFSZM16G67.F 1.62#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFJNPATJ6J3M 3.6 V VCORE Voltage on VCORE pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFOKMBJY110E_SF1 1.35 V CVDD Capacitor placed between VDD and VSS #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF8R4NLA4JN._SF1 10 uF CVCORE Capacitor placed between VCORE and VSS #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF8R4NLA4JN._SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFOKMBJY110E_SF1 470 nF TA Ambient temperature, Q version -40 125 °C TJ Max junction temperature, Q version 130 °C fMCLK MCLK, CPUCLK, ULPCLK frequency with 1 flash wait state #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF5LYWVWVU5N_SF1 32 MHz MCLK, CPUCLK, ULPCLK frequency with 0 flash wait states #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF5LYWVWVU5N_SF1 24 MIN NOM MAX UNIT MIN NOM MAX UNIT MINNOMMAXUNIT VDD Supply voltage #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFSZM16G67.F 1.62#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFJNPATJ6J3M 3.6 V VCORE Voltage on VCORE pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFOKMBJY110E_SF1 1.35 V CVDD Capacitor placed between VDD and VSS #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF8R4NLA4JN._SF1 10 uF CVCORE Capacitor placed between VCORE and VSS #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF8R4NLA4JN._SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFOKMBJY110E_SF1 470 nF TA Ambient temperature, Q version -40 125 °C TJ Max junction temperature, Q version 130 °C fMCLK MCLK, CPUCLK, ULPCLK frequency with 1 flash wait state #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF5LYWVWVU5N_SF1 32 MHz MCLK, CPUCLK, ULPCLK frequency with 0 flash wait states #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF5LYWVWVU5N_SF1 24 VDD Supply voltage #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFSZM16G67.F 1.62#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFJNPATJ6J3M 3.6 V VDDSupply voltage #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFSZM16G67.F #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFSZM16G67.F1.62#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFJNPATJ6J3M #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFJNPATJ6J3M3.6V VCORE Voltage on VCORE pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFOKMBJY110E_SF1 1.35 V VCOREVoltage on VCORE pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFOKMBJY110E_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFOKMBJY110E_SF11.35V CVDD Capacitor placed between VDD and VSS #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF8R4NLA4JN._SF1 10 uF CVDD VDDCapacitor placed between VDD and VSS #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF8R4NLA4JN._SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF8R4NLA4JN._SF110uF CVCORE Capacitor placed between VCORE and VSS #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF8R4NLA4JN._SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFOKMBJY110E_SF1 470 nF CVCORE VCORECapacitor placed between VCORE and VSS #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF8R4NLA4JN._SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFOKMBJY110E_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF8R4NLA4JN._SF1#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SFOKMBJY110E_SF1470nF TA Ambient temperature, Q version -40 125 °C TA AAmbient temperature, Q version-40125°C TJ Max junction temperature, Q version 130 °C TJ JMax junction temperature, Q version130°C fMCLK MCLK, CPUCLK, ULPCLK frequency with 1 flash wait state #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF5LYWVWVU5N_SF1 32 MHz fMCLK MCLKMCLK, CPUCLK, ULPCLK frequency with 1 flash wait state #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF5LYWVWVU5N_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF5LYWVWVU5N_SF132MHz MCLK, CPUCLK, ULPCLK frequency with 0 flash wait states #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF5LYWVWVU5N_SF1 24 MCLK, CPUCLK, ULPCLK frequency with 0 flash wait states #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF5LYWVWVU5N_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376821/SF5LYWVWVU5N_SF124 Connect CVDD and CVCORE between VDD/VSS and VCORE/VSS, respectively, as close to the device pins as possible. A low-ESR capacitor with at least the specified value and tolerance of ±20% or better is required for CVDD and CVCORE. The VCORE pin must only be connected to CVCORE. Do not supply any voltage or apply any external load to the VCORE pin. Wait states are managed automatically by the system controller (SYSCTL) and do not need to be configured by application software. There is no dependency on MCLK frequency with respect to VDD recommended operating range. Functionality is guaranteed down to VBOR0-(min). Connect CVDD and CVCORE between VDD/VSS and VCORE/VSS, respectively, as close to the device pins as possible. A low-ESR capacitor with at least the specified value and tolerance of ±20% or better is required for CVDD and CVCORE.VDDVCOREVDDVCOREThe VCORE pin must only be connected to CVCORE. Do not supply any voltage or apply any external load to the VCORE pin.VCOREWait states are managed automatically by the system controller (SYSCTL) and do not need to be configured by application software.There is no dependency on MCLK frequency with respect to VDD recommended operating range. Functionality is guaranteed down to VBOR0-(min).BOR0-(min) Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376825/A_LEGO_LORDBUSINESS_4_THERMAL_FOOTER1 PACKAGE VALUE UNIT RθJA Junction-to-ambient thermal resistance VQFN-32 (RHB) 36.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 28.5 °C/W RθJB Junction-to-board thermal resistance 17.2 °C/W ΨJT Junction-to-top characterization parameter 0.8 °C/W ΨJB Junction-to-board characterization parameter 17.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 6.9 °C/W RθJA Junction-to-ambient thermal resistance VSSOP-32 (DGS32) 72.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 28.3 °C/W RθJB Junction-to-board thermal resistance 37.2 °C/W ΨJT Junction-to-top characterization parameter 1.0 °C/W ΨJB Junction-to-board characterization parameter 37.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W RθJA Junction-to-ambient thermal resistance VSSOP-28 (DGS28) 78.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 38.6 °C/W RθJB Junction-to-board thermal resistance 41.3 °C/W ΨJT Junction-to-top characterization parameter 3.4 °C/W ΨJB Junction-to-board characterization parameter 41.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W RθJA Junction-to-ambient thermal resistance VQFN-24 (RGE) 44.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 38.1 °C/W RθJB Junction-to-board thermal resistance 21.9 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 21.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 7.1 °C/W RθJA Junction-to-ambient thermal resistance VSSOP-20 (DGS20) 91.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 29.3 °C/W RθJB Junction-to-board thermal resistance 48.3 °C/W ΨJT Junction-to-top characterization parameter 0.7 °C/W ΨJB Junction-to-board characterization parameter 47.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W RθJA Junction-to-ambient thermal resistance SOT-16 (DYY) 86.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 39.3 °C/W RθJB Junction-to-board thermal resistance 27.8 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 27.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Thermal Information THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376825/A_LEGO_LORDBUSINESS_4_THERMAL_FOOTER1 PACKAGE VALUE UNIT RθJA Junction-to-ambient thermal resistance VQFN-32 (RHB) 36.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 28.5 °C/W RθJB Junction-to-board thermal resistance 17.2 °C/W ΨJT Junction-to-top characterization parameter 0.8 °C/W ΨJB Junction-to-board characterization parameter 17.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 6.9 °C/W RθJA Junction-to-ambient thermal resistance VSSOP-32 (DGS32) 72.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 28.3 °C/W RθJB Junction-to-board thermal resistance 37.2 °C/W ΨJT Junction-to-top characterization parameter 1.0 °C/W ΨJB Junction-to-board characterization parameter 37.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W RθJA Junction-to-ambient thermal resistance VSSOP-28 (DGS28) 78.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 38.6 °C/W RθJB Junction-to-board thermal resistance 41.3 °C/W ΨJT Junction-to-top characterization parameter 3.4 °C/W ΨJB Junction-to-board characterization parameter 41.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W RθJA Junction-to-ambient thermal resistance VQFN-24 (RGE) 44.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 38.1 °C/W RθJB Junction-to-board thermal resistance 21.9 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 21.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 7.1 °C/W RθJA Junction-to-ambient thermal resistance VSSOP-20 (DGS20) 91.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 29.3 °C/W RθJB Junction-to-board thermal resistance 48.3 °C/W ΨJT Junction-to-top characterization parameter 0.7 °C/W ΨJB Junction-to-board characterization parameter 47.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W RθJA Junction-to-ambient thermal resistance SOT-16 (DYY) 86.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 39.3 °C/W RθJB Junction-to-board thermal resistance 27.8 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 27.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376825/A_LEGO_LORDBUSINESS_4_THERMAL_FOOTER1 PACKAGE VALUE UNIT RθJA Junction-to-ambient thermal resistance VQFN-32 (RHB) 36.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 28.5 °C/W RθJB Junction-to-board thermal resistance 17.2 °C/W ΨJT Junction-to-top characterization parameter 0.8 °C/W ΨJB Junction-to-board characterization parameter 17.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 6.9 °C/W RθJA Junction-to-ambient thermal resistance VSSOP-32 (DGS32) 72.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 28.3 °C/W RθJB Junction-to-board thermal resistance 37.2 °C/W ΨJT Junction-to-top characterization parameter 1.0 °C/W ΨJB Junction-to-board characterization parameter 37.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W RθJA Junction-to-ambient thermal resistance VSSOP-28 (DGS28) 78.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 38.6 °C/W RθJB Junction-to-board thermal resistance 41.3 °C/W ΨJT Junction-to-top characterization parameter 3.4 °C/W ΨJB Junction-to-board characterization parameter 41.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W RθJA Junction-to-ambient thermal resistance VQFN-24 (RGE) 44.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 38.1 °C/W RθJB Junction-to-board thermal resistance 21.9 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 21.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 7.1 °C/W RθJA Junction-to-ambient thermal resistance VSSOP-20 (DGS20) 91.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 29.3 °C/W RθJB Junction-to-board thermal resistance 48.3 °C/W ΨJT Junction-to-top characterization parameter 0.7 °C/W ΨJB Junction-to-board characterization parameter 47.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W RθJA Junction-to-ambient thermal resistance SOT-16 (DYY) 86.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 39.3 °C/W RθJB Junction-to-board thermal resistance 27.8 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 27.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376825/A_LEGO_LORDBUSINESS_4_THERMAL_FOOTER1 PACKAGE VALUE UNIT RθJA Junction-to-ambient thermal resistance VQFN-32 (RHB) 36.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 28.5 °C/W RθJB Junction-to-board thermal resistance 17.2 °C/W ΨJT Junction-to-top characterization parameter 0.8 °C/W ΨJB Junction-to-board characterization parameter 17.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 6.9 °C/W RθJA Junction-to-ambient thermal resistance VSSOP-32 (DGS32) 72.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 28.3 °C/W RθJB Junction-to-board thermal resistance 37.2 °C/W ΨJT Junction-to-top characterization parameter 1.0 °C/W ΨJB Junction-to-board characterization parameter 37.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W RθJA Junction-to-ambient thermal resistance VSSOP-28 (DGS28) 78.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 38.6 °C/W RθJB Junction-to-board thermal resistance 41.3 °C/W ΨJT Junction-to-top characterization parameter 3.4 °C/W ΨJB Junction-to-board characterization parameter 41.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W RθJA Junction-to-ambient thermal resistance VQFN-24 (RGE) 44.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 38.1 °C/W RθJB Junction-to-board thermal resistance 21.9 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 21.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 7.1 °C/W RθJA Junction-to-ambient thermal resistance VSSOP-20 (DGS20) 91.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 29.3 °C/W RθJB Junction-to-board thermal resistance 48.3 °C/W ΨJT Junction-to-top characterization parameter 0.7 °C/W ΨJB Junction-to-board characterization parameter 47.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W RθJA Junction-to-ambient thermal resistance SOT-16 (DYY) 86.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 39.3 °C/W RθJB Junction-to-board thermal resistance 27.8 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 27.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376825/A_LEGO_LORDBUSINESS_4_THERMAL_FOOTER1 PACKAGE VALUE UNIT THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376825/A_LEGO_LORDBUSINESS_4_THERMAL_FOOTER1 PACKAGE VALUE UNIT THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376825/A_LEGO_LORDBUSINESS_4_THERMAL_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376825/A_LEGO_LORDBUSINESS_4_THERMAL_FOOTER1PACKAGEVALUEUNIT RθJA Junction-to-ambient thermal resistance VQFN-32 (RHB) 36.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 28.5 °C/W RθJB Junction-to-board thermal resistance 17.2 °C/W ΨJT Junction-to-top characterization parameter 0.8 °C/W ΨJB Junction-to-board characterization parameter 17.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 6.9 °C/W RθJA Junction-to-ambient thermal resistance VSSOP-32 (DGS32) 72.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 28.3 °C/W RθJB Junction-to-board thermal resistance 37.2 °C/W ΨJT Junction-to-top characterization parameter 1.0 °C/W ΨJB Junction-to-board characterization parameter 37.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W RθJA Junction-to-ambient thermal resistance VSSOP-28 (DGS28) 78.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 38.6 °C/W RθJB Junction-to-board thermal resistance 41.3 °C/W ΨJT Junction-to-top characterization parameter 3.4 °C/W ΨJB Junction-to-board characterization parameter 41.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W RθJA Junction-to-ambient thermal resistance VQFN-24 (RGE) 44.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 38.1 °C/W RθJB Junction-to-board thermal resistance 21.9 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 21.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 7.1 °C/W RθJA Junction-to-ambient thermal resistance VSSOP-20 (DGS20) 91.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 29.3 °C/W RθJB Junction-to-board thermal resistance 48.3 °C/W ΨJT Junction-to-top characterization parameter 0.7 °C/W ΨJB Junction-to-board characterization parameter 47.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W RθJA Junction-to-ambient thermal resistance SOT-16 (DYY) 86.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 39.3 °C/W RθJB Junction-to-board thermal resistance 27.8 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 27.8 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W RθJA Junction-to-ambient thermal resistance VQFN-32 (RHB) 36.3 °C/W RθJA θJA Junction-to-ambient thermal resistanceVQFN-32 (RHB)36.3°C/W RθJC(top) Junction-to-case (top) thermal resistance 28.5 °C/W RθJC(top) θJC(top)Junction-to-case (top) thermal resistance28.5°C/W RθJB Junction-to-board thermal resistance 17.2 °C/W RθJB θJBJunction-to-board thermal resistance17.2°C/W ΨJT Junction-to-top characterization parameter 0.8 °C/W ΨJT JTJunction-to-top characterization parameter0.8°C/W ΨJB Junction-to-board characterization parameter 17.2 °C/W ΨJB JBJunction-to-board characterization parameter17.2°C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 6.9 °C/W RθJC(bot) θJC(bot)Junction-to-case (bottom) thermal resistance6.9°C/W RθJA Junction-to-ambient thermal resistance VSSOP-32 (DGS32) 72.9 °C/W RθJA θJA Junction-to-ambient thermal resistanceVSSOP-32 (DGS32) 72.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 28.3 °C/W RθJC(top) θJC(top)Junction-to-case (top) thermal resistance 28.3 °C/W RθJB Junction-to-board thermal resistance 37.2 °C/W RθJB θJBJunction-to-board thermal resistance37.2°C/W ΨJT Junction-to-top characterization parameter 1.0 °C/W ΨJT JTJunction-to-top characterization parameter1.0°C/W ΨJB Junction-to-board characterization parameter 37.0 °C/W ΨJB JBJunction-to-board characterization parameter 37.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W RθJC(bot) θJC(bot)Junction-to-case (bottom) thermal resistanceN/A°C/W RθJA Junction-to-ambient thermal resistance VSSOP-28 (DGS28) 78.9 °C/W RθJA θJA Junction-to-ambient thermal resistanceVSSOP-28 (DGS28)78.9°C/W RθJC(top) Junction-to-case (top) thermal resistance 38.6 °C/W RθJC(top) θJC(top)Junction-to-case (top) thermal resistance38.6°C/W RθJB Junction-to-board thermal resistance 41.3 °C/W RθJB θJBJunction-to-board thermal resistance41.3°C/W ΨJT Junction-to-top characterization parameter 3.4 °C/W ΨJT JTJunction-to-top characterization parameter3.4°C/W ΨJB Junction-to-board characterization parameter 41.0 °C/W ΨJB JBJunction-to-board characterization parameter41.0°C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W RθJC(bot) θJC(bot)Junction-to-case (bottom) thermal resistanceN/A°C/W RθJA Junction-to-ambient thermal resistance VQFN-24 (RGE) 44.7 °C/W RθJA θJA Junction-to-ambient thermal resistanceVQFN-24 (RGE)44.7°C/W RθJC(top) Junction-to-case (top) thermal resistance 38.1 °C/W RθJC(top) θJC(top)Junction-to-case (top) thermal resistance38.1°C/W RθJB Junction-to-board thermal resistance 21.9 °C/W RθJB θJBJunction-to-board thermal resistance21.9°C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJT JTJunction-to-top characterization parameter1.1°C/W ΨJB Junction-to-board characterization parameter 21.9 °C/W ΨJB JBJunction-to-board characterization parameter21.9°C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 7.1 °C/W RθJC(bot) θJC(bot)Junction-to-case (bottom) thermal resistance7.1°C/W RθJA Junction-to-ambient thermal resistance VSSOP-20 (DGS20) 91.3 °C/W RθJA θJA Junction-to-ambient thermal resistanceVSSOP-20 (DGS20)91.3°C/W RθJC(top) Junction-to-case (top) thermal resistance 29.3 °C/W RθJC(top) θJC(top)Junction-to-case (top) thermal resistance29.3°C/W RθJB Junction-to-board thermal resistance 48.3 °C/W RθJB θJBJunction-to-board thermal resistance48.3°C/W ΨJT Junction-to-top characterization parameter 0.7 °C/W ΨJT JTJunction-to-top characterization parameter0.7°C/W ΨJB Junction-to-board characterization parameter 47.9 °C/W ΨJB JBJunction-to-board characterization parameter47.9°C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W RθJC(bot) θJC(bot)Junction-to-case (bottom) thermal resistanceN/A°C/W RθJA Junction-to-ambient thermal resistance SOT-16 (DYY) 86.6 °C/W RθJA θJA Junction-to-ambient thermal resistanceSOT-16 (DYY)86.6°C/W RθJC(top) Junction-to-case (top) thermal resistance 39.3 °C/W RθJC(top) θJC(top)Junction-to-case (top) thermal resistance39.3°C/W RθJB Junction-to-board thermal resistance 27.8 °C/W RθJB θJBJunction-to-board thermal resistance27.8°C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJT JTJunction-to-top characterization parameter1.1°C/W ΨJB Junction-to-board characterization parameter 27.8 °C/W ΨJB JBJunction-to-board characterization parameter27.8°C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W RθJC(bot) θJC(bot)Junction-to-case (bottom) thermal resistanceN/A°C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.Semiconductor and IC Package Thermal Metrics Supply Current Characteristics RUN/SLEEP Modes VDD=3.3V. All inputs tied to 0V or VDD. Outputs do not source or sink any current. All peripherals are disabled. PARAMETER MCLK -40°C 25°C 85°C 105°C 125°C UNIT TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX RUN Mode IDDRUN MCLK=SYSOSC, CoreMark, execute from flash 32MHz 2.3 2.3 2.3 2.3 2.4 mA 4MHz 0.52 0.52 0.54 0.56 0.60 IDDRUN, per MHz MCLK=SYSOSC, While(1), execute from flash 32MHz 40 48 40 50 41 50 42 51 43 56 uA/Mhz MCLK=SYSOSC, CoreMark, execute from flash 32MHz 72 72 72 73 74 MCLK=SYSOSC, CoreMark, execute from flash 4MHz 130 130 135 140 150 SLEEP Mode IDDSLEEP MCLK=SYSOSC, CPU is halted 32MHz 967 1047 978 1066 1002 1192 1024 1301 1070 1416 uA 4MHz 356 416 363 441 389 577 411 689 458 809 STOP/STANDBY Modes VDD=3.3V unless otherwise noted. All inputs tied to 0V or VDD. Outputs do not source or sink any current. All peripherals not noted are disabled. PARAMETER ULPCLK -40°C 25°C 85°C 105°C 125°C UNIT TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX STOP Mode IDDSTOP0 SYSOSC=32MHz, USE4MHZSTOP=0, DISABLESTOP=0 4MHz 316 342 320 344 323 347 327 352 334 361 uA IDDSTOP1 SYSOSC=4MHz, USE4MHZSTOP=1, DISABLESTOP=0 4MHz 146 167 151 171 155 176 158 182 166 192 IDDSTOP2 SYSOSC off, DISABLESTOP=1, ULPCLK=LFCLK 32kHz 42 51 44 54 47 58 50 64 56 76 STANDBY Mode IDDSTBY0 STOPCLKSTBY=0, TIMG0 enabled 32kHz 1.2 1.3 1.3 1.7 2.7 6.2 4.7 12 11 25 uA IDDSTBY1 STOPCLKSTBY=1, TIMG0 enabled 0.9 1.0 1.0 1.4 2.4 5.9 4.4 12 11 25 STOPCLKSTBY=1, GPIOA enabled 0.9 1.0 1.0 1.4 2.4 5.9 4.4 12 10 25 SHUTDOWN Mode All inputs tied to 0V or VDD. Outputs do not source or sink any current. Core regulator is powered down. PARAMETER VDD -40°C 25°C 85°C 105°C 125°C UNIT TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX IDDSHDN Supply current in SHUTDOWN mode 3.3V 47 61 352 793 2020 nA Supply Current Characteristics RUN/SLEEP Modes VDD=3.3V. All inputs tied to 0V or VDD. Outputs do not source or sink any current. All peripherals are disabled. PARAMETER MCLK -40°C 25°C 85°C 105°C 125°C UNIT TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX RUN Mode IDDRUN MCLK=SYSOSC, CoreMark, execute from flash 32MHz 2.3 2.3 2.3 2.3 2.4 mA 4MHz 0.52 0.52 0.54 0.56 0.60 IDDRUN, per MHz MCLK=SYSOSC, While(1), execute from flash 32MHz 40 48 40 50 41 50 42 51 43 56 uA/Mhz MCLK=SYSOSC, CoreMark, execute from flash 32MHz 72 72 72 73 74 MCLK=SYSOSC, CoreMark, execute from flash 4MHz 130 130 135 140 150 SLEEP Mode IDDSLEEP MCLK=SYSOSC, CPU is halted 32MHz 967 1047 978 1066 1002 1192 1024 1301 1070 1416 uA 4MHz 356 416 363 441 389 577 411 689 458 809 RUN/SLEEP Modes VDD=3.3V. All inputs tied to 0V or VDD. Outputs do not source or sink any current. All peripherals are disabled. PARAMETER MCLK -40°C 25°C 85°C 105°C 125°C UNIT TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX RUN Mode IDDRUN MCLK=SYSOSC, CoreMark, execute from flash 32MHz 2.3 2.3 2.3 2.3 2.4 mA 4MHz 0.52 0.52 0.54 0.56 0.60 IDDRUN, per MHz MCLK=SYSOSC, While(1), execute from flash 32MHz 40 48 40 50 41 50 42 51 43 56 uA/Mhz MCLK=SYSOSC, CoreMark, execute from flash 32MHz 72 72 72 73 74 MCLK=SYSOSC, CoreMark, execute from flash 4MHz 130 130 135 140 150 SLEEP Mode IDDSLEEP MCLK=SYSOSC, CPU is halted 32MHz 967 1047 978 1066 1002 1192 1024 1301 1070 1416 uA 4MHz 356 416 363 441 389 577 411 689 458 809 VDD=3.3V. All inputs tied to 0V or VDD. Outputs do not source or sink any current. All peripherals are disabled. PARAMETER MCLK -40°C 25°C 85°C 105°C 125°C UNIT TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX RUN Mode IDDRUN MCLK=SYSOSC, CoreMark, execute from flash 32MHz 2.3 2.3 2.3 2.3 2.4 mA 4MHz 0.52 0.52 0.54 0.56 0.60 IDDRUN, per MHz MCLK=SYSOSC, While(1), execute from flash 32MHz 40 48 40 50 41 50 42 51 43 56 uA/Mhz MCLK=SYSOSC, CoreMark, execute from flash 32MHz 72 72 72 73 74 MCLK=SYSOSC, CoreMark, execute from flash 4MHz 130 130 135 140 150 SLEEP Mode IDDSLEEP MCLK=SYSOSC, CPU is halted 32MHz 967 1047 978 1066 1002 1192 1024 1301 1070 1416 uA 4MHz 356 416 363 441 389 577 411 689 458 809 VDD=3.3V. All inputs tied to 0V or VDD. Outputs do not source or sink any current. All peripherals are disabled. PARAMETER MCLK -40°C 25°C 85°C 105°C 125°C UNIT TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX RUN Mode IDDRUN MCLK=SYSOSC, CoreMark, execute from flash 32MHz 2.3 2.3 2.3 2.3 2.4 mA 4MHz 0.52 0.52 0.54 0.56 0.60 IDDRUN, per MHz MCLK=SYSOSC, While(1), execute from flash 32MHz 40 48 40 50 41 50 42 51 43 56 uA/Mhz MCLK=SYSOSC, CoreMark, execute from flash 32MHz 72 72 72 73 74 MCLK=SYSOSC, CoreMark, execute from flash 4MHz 130 130 135 140 150 SLEEP Mode IDDSLEEP MCLK=SYSOSC, CPU is halted 32MHz 967 1047 978 1066 1002 1192 1024 1301 1070 1416 uA 4MHz 356 416 363 441 389 577 411 689 458 809 PARAMETER MCLK -40°C 25°C 85°C 105°C 125°C UNIT TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX PARAMETER MCLK -40°C 25°C 85°C 105°C 125°C UNIT PARAMETERMCLK-40°C25°C85°C105°C125°CUNIT TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX TYPMAXTYPMAXTYPMAXTYPMAXTYPMAX RUN Mode IDDRUN MCLK=SYSOSC, CoreMark, execute from flash 32MHz 2.3 2.3 2.3 2.3 2.4 mA 4MHz 0.52 0.52 0.54 0.56 0.60 IDDRUN, per MHz MCLK=SYSOSC, While(1), execute from flash 32MHz 40 48 40 50 41 50 42 51 43 56 uA/Mhz MCLK=SYSOSC, CoreMark, execute from flash 32MHz 72 72 72 73 74 MCLK=SYSOSC, CoreMark, execute from flash 4MHz 130 130 135 140 150 SLEEP Mode IDDSLEEP MCLK=SYSOSC, CPU is halted 32MHz 967 1047 978 1066 1002 1192 1024 1301 1070 1416 uA 4MHz 356 416 363 441 389 577 411 689 458 809 RUN Mode RUN Mode IDDRUN MCLK=SYSOSC, CoreMark, execute from flash 32MHz 2.3 2.3 2.3 2.3 2.4 mA IDDRUN RUNMCLK=SYSOSC, CoreMark, execute from flash32MHz2.32.32.32.32.4mA 4MHz 0.52 0.52 0.54 0.56 0.60 4MHz0.520.520.540.560.60 IDDRUN, per MHz MCLK=SYSOSC, While(1), execute from flash 32MHz 40 48 40 50 41 50 42 51 43 56 uA/Mhz IDDRUN, per MHzRUNMCLK=SYSOSC, While(1), execute from flash32MHz40484050415042514356uA/Mhz MCLK=SYSOSC, CoreMark, execute from flash 32MHz 72 72 72 73 74 MCLK=SYSOSC, CoreMark, execute from flash32MHz7272727374 MCLK=SYSOSC, CoreMark, execute from flash 4MHz 130 130 135 140 150 MCLK=SYSOSC, CoreMark, execute from flash4MHz130130135140150 SLEEP Mode SLEEP Mode IDDSLEEP MCLK=SYSOSC, CPU is halted 32MHz 967 1047 978 1066 1002 1192 1024 1301 1070 1416 uA IDDSLEEP SLEEPMCLK=SYSOSC, CPU is halted32MHz96710479781066100211921024130110701416uA 4MHz 356 416 363 441 389 577 411 689 458 809 4MHz356416363441389577411689458809 STOP/STANDBY Modes VDD=3.3V unless otherwise noted. All inputs tied to 0V or VDD. Outputs do not source or sink any current. All peripherals not noted are disabled. PARAMETER ULPCLK -40°C 25°C 85°C 105°C 125°C UNIT TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX STOP Mode IDDSTOP0 SYSOSC=32MHz, USE4MHZSTOP=0, DISABLESTOP=0 4MHz 316 342 320 344 323 347 327 352 334 361 uA IDDSTOP1 SYSOSC=4MHz, USE4MHZSTOP=1, DISABLESTOP=0 4MHz 146 167 151 171 155 176 158 182 166 192 IDDSTOP2 SYSOSC off, DISABLESTOP=1, ULPCLK=LFCLK 32kHz 42 51 44 54 47 58 50 64 56 76 STANDBY Mode IDDSTBY0 STOPCLKSTBY=0, TIMG0 enabled 32kHz 1.2 1.3 1.3 1.7 2.7 6.2 4.7 12 11 25 uA IDDSTBY1 STOPCLKSTBY=1, TIMG0 enabled 0.9 1.0 1.0 1.4 2.4 5.9 4.4 12 11 25 STOPCLKSTBY=1, GPIOA enabled 0.9 1.0 1.0 1.4 2.4 5.9 4.4 12 10 25 STOP/STANDBY Modes VDD=3.3V unless otherwise noted. All inputs tied to 0V or VDD. Outputs do not source or sink any current. All peripherals not noted are disabled. PARAMETER ULPCLK -40°C 25°C 85°C 105°C 125°C UNIT TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX STOP Mode IDDSTOP0 SYSOSC=32MHz, USE4MHZSTOP=0, DISABLESTOP=0 4MHz 316 342 320 344 323 347 327 352 334 361 uA IDDSTOP1 SYSOSC=4MHz, USE4MHZSTOP=1, DISABLESTOP=0 4MHz 146 167 151 171 155 176 158 182 166 192 IDDSTOP2 SYSOSC off, DISABLESTOP=1, ULPCLK=LFCLK 32kHz 42 51 44 54 47 58 50 64 56 76 STANDBY Mode IDDSTBY0 STOPCLKSTBY=0, TIMG0 enabled 32kHz 1.2 1.3 1.3 1.7 2.7 6.2 4.7 12 11 25 uA IDDSTBY1 STOPCLKSTBY=1, TIMG0 enabled 0.9 1.0 1.0 1.4 2.4 5.9 4.4 12 11 25 STOPCLKSTBY=1, GPIOA enabled 0.9 1.0 1.0 1.4 2.4 5.9 4.4 12 10 25 VDD=3.3V unless otherwise noted. All inputs tied to 0V or VDD. Outputs do not source or sink any current. All peripherals not noted are disabled. PARAMETER ULPCLK -40°C 25°C 85°C 105°C 125°C UNIT TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX STOP Mode IDDSTOP0 SYSOSC=32MHz, USE4MHZSTOP=0, DISABLESTOP=0 4MHz 316 342 320 344 323 347 327 352 334 361 uA IDDSTOP1 SYSOSC=4MHz, USE4MHZSTOP=1, DISABLESTOP=0 4MHz 146 167 151 171 155 176 158 182 166 192 IDDSTOP2 SYSOSC off, DISABLESTOP=1, ULPCLK=LFCLK 32kHz 42 51 44 54 47 58 50 64 56 76 STANDBY Mode IDDSTBY0 STOPCLKSTBY=0, TIMG0 enabled 32kHz 1.2 1.3 1.3 1.7 2.7 6.2 4.7 12 11 25 uA IDDSTBY1 STOPCLKSTBY=1, TIMG0 enabled 0.9 1.0 1.0 1.4 2.4 5.9 4.4 12 11 25 STOPCLKSTBY=1, GPIOA enabled 0.9 1.0 1.0 1.4 2.4 5.9 4.4 12 10 25 VDD=3.3V unless otherwise noted. All inputs tied to 0V or VDD. Outputs do not source or sink any current. All peripherals not noted are disabled. PARAMETER ULPCLK -40°C 25°C 85°C 105°C 125°C UNIT TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX STOP Mode IDDSTOP0 SYSOSC=32MHz, USE4MHZSTOP=0, DISABLESTOP=0 4MHz 316 342 320 344 323 347 327 352 334 361 uA IDDSTOP1 SYSOSC=4MHz, USE4MHZSTOP=1, DISABLESTOP=0 4MHz 146 167 151 171 155 176 158 182 166 192 IDDSTOP2 SYSOSC off, DISABLESTOP=1, ULPCLK=LFCLK 32kHz 42 51 44 54 47 58 50 64 56 76 STANDBY Mode IDDSTBY0 STOPCLKSTBY=0, TIMG0 enabled 32kHz 1.2 1.3 1.3 1.7 2.7 6.2 4.7 12 11 25 uA IDDSTBY1 STOPCLKSTBY=1, TIMG0 enabled 0.9 1.0 1.0 1.4 2.4 5.9 4.4 12 11 25 STOPCLKSTBY=1, GPIOA enabled 0.9 1.0 1.0 1.4 2.4 5.9 4.4 12 10 25 PARAMETER ULPCLK -40°C 25°C 85°C 105°C 125°C UNIT TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX PARAMETER ULPCLK -40°C 25°C 85°C 105°C 125°C UNIT PARAMETERULPCLK-40°C25°C85°C105°C125°CUNIT TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX TYPMAXTYPMAXTYPMAXTYPMAXTYPMAX STOP Mode IDDSTOP0 SYSOSC=32MHz, USE4MHZSTOP=0, DISABLESTOP=0 4MHz 316 342 320 344 323 347 327 352 334 361 uA IDDSTOP1 SYSOSC=4MHz, USE4MHZSTOP=1, DISABLESTOP=0 4MHz 146 167 151 171 155 176 158 182 166 192 IDDSTOP2 SYSOSC off, DISABLESTOP=1, ULPCLK=LFCLK 32kHz 42 51 44 54 47 58 50 64 56 76 STANDBY Mode IDDSTBY0 STOPCLKSTBY=0, TIMG0 enabled 32kHz 1.2 1.3 1.3 1.7 2.7 6.2 4.7 12 11 25 uA IDDSTBY1 STOPCLKSTBY=1, TIMG0 enabled 0.9 1.0 1.0 1.4 2.4 5.9 4.4 12 11 25 STOPCLKSTBY=1, GPIOA enabled 0.9 1.0 1.0 1.4 2.4 5.9 4.4 12 10 25 STOP Mode STOP Mode IDDSTOP0 SYSOSC=32MHz, USE4MHZSTOP=0, DISABLESTOP=0 4MHz 316 342 320 344 323 347 327 352 334 361 uA IDDSTOP0 STOP0SYSOSC=32MHz, USE4MHZSTOP=0, DISABLESTOP=04MHz316342320344323347327352334361uA IDDSTOP1 SYSOSC=4MHz, USE4MHZSTOP=1, DISABLESTOP=0 4MHz 146 167 151 171 155 176 158 182 166 192 IDDSTOP1 STOP1SYSOSC=4MHz, USE4MHZSTOP=1, DISABLESTOP=04MHz146167151171155176158182166192 IDDSTOP2 SYSOSC off, DISABLESTOP=1, ULPCLK=LFCLK 32kHz 42 51 44 54 47 58 50 64 56 76 IDDSTOP2 STOP2SYSOSC off, DISABLESTOP=1, ULPCLK=LFCLK32kHz42514454475850645676 STANDBY Mode STANDBY Mode IDDSTBY0 STOPCLKSTBY=0, TIMG0 enabled 32kHz 1.2 1.3 1.3 1.7 2.7 6.2 4.7 12 11 25 uA IDDSTBY0 STBY0STOPCLKSTBY=0, TIMG0 enabled32kHz1.21.31.31.72.76.24.7121125uA IDDSTBY1 STOPCLKSTBY=1, TIMG0 enabled 0.9 1.0 1.0 1.4 2.4 5.9 4.4 12 11 25 IDDSTBY1 STBY1STOPCLKSTBY=1, TIMG0 enabled0.91.01.01.42.45.94.4121125 STOPCLKSTBY=1, GPIOA enabled 0.9 1.0 1.0 1.4 2.4 5.9 4.4 12 10 25 STOPCLKSTBY=1, GPIOA enabled0.91.01.01.42.45.94.4121025 SHUTDOWN Mode All inputs tied to 0V or VDD. Outputs do not source or sink any current. Core regulator is powered down. PARAMETER VDD -40°C 25°C 85°C 105°C 125°C UNIT TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX IDDSHDN Supply current in SHUTDOWN mode 3.3V 47 61 352 793 2020 nA SHUTDOWN Mode All inputs tied to 0V or VDD. Outputs do not source or sink any current. Core regulator is powered down. PARAMETER VDD -40°C 25°C 85°C 105°C 125°C UNIT TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX IDDSHDN Supply current in SHUTDOWN mode 3.3V 47 61 352 793 2020 nA All inputs tied to 0V or VDD. Outputs do not source or sink any current. Core regulator is powered down. PARAMETER VDD -40°C 25°C 85°C 105°C 125°C UNIT TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX IDDSHDN Supply current in SHUTDOWN mode 3.3V 47 61 352 793 2020 nA All inputs tied to 0V or VDD. Outputs do not source or sink any current. Core regulator is powered down. PARAMETER VDD -40°C 25°C 85°C 105°C 125°C UNIT TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX IDDSHDN Supply current in SHUTDOWN mode 3.3V 47 61 352 793 2020 nA PARAMETER VDD -40°C 25°C 85°C 105°C 125°C UNIT TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX PARAMETER VDD -40°C 25°C 85°C 105°C 125°C UNIT PARAMETERVDD-40°C25°C85°C105°C125°CUNIT TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX TYPMAXTYPMAXTYPMAXTYPMAXTYPMAX IDDSHDN Supply current in SHUTDOWN mode 3.3V 47 61 352 793 2020 nA IDDSHDN Supply current in SHUTDOWN mode 3.3V 47 61 352 793 2020 nA IDDSHDN SHDNSupply current in SHUTDOWN mode3.3V47613527932020nA Power Supply Sequencing POR and BOR over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT dVDD/dt VDD (supply voltage) slew rate Rising 1 V/us Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 0.01 Falling, STANDBY 0.1 V/ms VPOR+ Power-on reset voltage level Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 0.95 1.30 1.51 V VPOR- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 0.9 1.25 1.48 V VHYS, POR POR hysteresis #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 30 45 60 mV VBOR0+, COLD Brown-out reset voltage level 0 (default level) Cold start, rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 1.48 1.54 1.61 V VBOR0+ Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 1.55 1.59 1.62 VBOR0- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 1.54 1.58 1.61 VBOR0, STBY STANDBY mode #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 1.51 1.57 1.61 VBOR1+ Brown-out-reset voltage level 1 Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.13 2.18 2.23 V VBOR1- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.10 2.15 2.19 VBOR2+ Brown-out-reset voltage level 2 Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.73 2.77 2.82 V VBOR2- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.7 2.74 2.79 VBOR3+ Brown-out-reset voltage level 3 Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.88 2.97 3.04 V VBOR3- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.85 2.94 3.01 VHYS,BOR Brown-out reset hysteresis Level 0 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 15 21 mV Levels 1-3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 34 40 TPD, BOR BOR propagation delay RUN/SLEEP/STOP mode 10 us STANDBY mode 100 us \|dVDD/dt\| ≤ 3V/s Device operating in RUN, SLEEP, or STOP mode. Power Supply Ramp shows the relationships of POR-, POR+, BOR0-, and BOR0+ during powerup and powerdown. Power Cycle POR and BOR Conditions Power Supply Sequencing POR and BOR over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT dVDD/dt VDD (supply voltage) slew rate Rising 1 V/us Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 0.01 Falling, STANDBY 0.1 V/ms VPOR+ Power-on reset voltage level Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 0.95 1.30 1.51 V VPOR- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 0.9 1.25 1.48 V VHYS, POR POR hysteresis #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 30 45 60 mV VBOR0+, COLD Brown-out reset voltage level 0 (default level) Cold start, rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 1.48 1.54 1.61 V VBOR0+ Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 1.55 1.59 1.62 VBOR0- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 1.54 1.58 1.61 VBOR0, STBY STANDBY mode #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 1.51 1.57 1.61 VBOR1+ Brown-out-reset voltage level 1 Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.13 2.18 2.23 V VBOR1- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.10 2.15 2.19 VBOR2+ Brown-out-reset voltage level 2 Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.73 2.77 2.82 V VBOR2- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.7 2.74 2.79 VBOR3+ Brown-out-reset voltage level 3 Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.88 2.97 3.04 V VBOR3- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.85 2.94 3.01 VHYS,BOR Brown-out reset hysteresis Level 0 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 15 21 mV Levels 1-3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 34 40 TPD, BOR BOR propagation delay RUN/SLEEP/STOP mode 10 us STANDBY mode 100 us \|dVDD/dt\| ≤ 3V/s Device operating in RUN, SLEEP, or STOP mode. POR and BOR over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT dVDD/dt VDD (supply voltage) slew rate Rising 1 V/us Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 0.01 Falling, STANDBY 0.1 V/ms VPOR+ Power-on reset voltage level Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 0.95 1.30 1.51 V VPOR- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 0.9 1.25 1.48 V VHYS, POR POR hysteresis #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 30 45 60 mV VBOR0+, COLD Brown-out reset voltage level 0 (default level) Cold start, rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 1.48 1.54 1.61 V VBOR0+ Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 1.55 1.59 1.62 VBOR0- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 1.54 1.58 1.61 VBOR0, STBY STANDBY mode #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 1.51 1.57 1.61 VBOR1+ Brown-out-reset voltage level 1 Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.13 2.18 2.23 V VBOR1- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.10 2.15 2.19 VBOR2+ Brown-out-reset voltage level 2 Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.73 2.77 2.82 V VBOR2- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.7 2.74 2.79 VBOR3+ Brown-out-reset voltage level 3 Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.88 2.97 3.04 V VBOR3- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.85 2.94 3.01 VHYS,BOR Brown-out reset hysteresis Level 0 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 15 21 mV Levels 1-3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 34 40 TPD, BOR BOR propagation delay RUN/SLEEP/STOP mode 10 us STANDBY mode 100 us \|dVDD/dt\| ≤ 3V/s Device operating in RUN, SLEEP, or STOP mode. over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT dVDD/dt VDD (supply voltage) slew rate Rising 1 V/us Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 0.01 Falling, STANDBY 0.1 V/ms VPOR+ Power-on reset voltage level Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 0.95 1.30 1.51 V VPOR- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 0.9 1.25 1.48 V VHYS, POR POR hysteresis #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 30 45 60 mV VBOR0+, COLD Brown-out reset voltage level 0 (default level) Cold start, rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 1.48 1.54 1.61 V VBOR0+ Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 1.55 1.59 1.62 VBOR0- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 1.54 1.58 1.61 VBOR0, STBY STANDBY mode #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 1.51 1.57 1.61 VBOR1+ Brown-out-reset voltage level 1 Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.13 2.18 2.23 V VBOR1- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.10 2.15 2.19 VBOR2+ Brown-out-reset voltage level 2 Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.73 2.77 2.82 V VBOR2- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.7 2.74 2.79 VBOR3+ Brown-out-reset voltage level 3 Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.88 2.97 3.04 V VBOR3- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.85 2.94 3.01 VHYS,BOR Brown-out reset hysteresis Level 0 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 15 21 mV Levels 1-3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 34 40 TPD, BOR BOR propagation delay RUN/SLEEP/STOP mode 10 us STANDBY mode 100 us over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT dVDD/dt VDD (supply voltage) slew rate Rising 1 V/us Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 0.01 Falling, STANDBY 0.1 V/ms VPOR+ Power-on reset voltage level Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 0.95 1.30 1.51 V VPOR- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 0.9 1.25 1.48 V VHYS, POR POR hysteresis #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 30 45 60 mV VBOR0+, COLD Brown-out reset voltage level 0 (default level) Cold start, rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 1.48 1.54 1.61 V VBOR0+ Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 1.55 1.59 1.62 VBOR0- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 1.54 1.58 1.61 VBOR0, STBY STANDBY mode #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 1.51 1.57 1.61 VBOR1+ Brown-out-reset voltage level 1 Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.13 2.18 2.23 V VBOR1- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.10 2.15 2.19 VBOR2+ Brown-out-reset voltage level 2 Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.73 2.77 2.82 V VBOR2- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.7 2.74 2.79 VBOR3+ Brown-out-reset voltage level 3 Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.88 2.97 3.04 V VBOR3- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.85 2.94 3.01 VHYS,BOR Brown-out reset hysteresis Level 0 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 15 21 mV Levels 1-3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 34 40 TPD, BOR BOR propagation delay RUN/SLEEP/STOP mode 10 us STANDBY mode 100 us PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT dVDD/dt VDD (supply voltage) slew rate Rising 1 V/us Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 0.01 Falling, STANDBY 0.1 V/ms VPOR+ Power-on reset voltage level Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 0.95 1.30 1.51 V VPOR- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 0.9 1.25 1.48 V VHYS, POR POR hysteresis #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 30 45 60 mV VBOR0+, COLD Brown-out reset voltage level 0 (default level) Cold start, rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 1.48 1.54 1.61 V VBOR0+ Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 1.55 1.59 1.62 VBOR0- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 1.54 1.58 1.61 VBOR0, STBY STANDBY mode #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 1.51 1.57 1.61 VBOR1+ Brown-out-reset voltage level 1 Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.13 2.18 2.23 V VBOR1- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.10 2.15 2.19 VBOR2+ Brown-out-reset voltage level 2 Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.73 2.77 2.82 V VBOR2- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.7 2.74 2.79 VBOR3+ Brown-out-reset voltage level 3 Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.88 2.97 3.04 V VBOR3- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.85 2.94 3.01 VHYS,BOR Brown-out reset hysteresis Level 0 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 15 21 mV Levels 1-3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 34 40 TPD, BOR BOR propagation delay RUN/SLEEP/STOP mode 10 us STANDBY mode 100 us dVDD/dt VDD (supply voltage) slew rate Rising 1 V/us dVDD/dtVDD (supply voltage) slew rateRising1V/us Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 0.01 Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA0.01 Falling, STANDBY 0.1 V/ms Falling, STANDBY0.1V/ms VPOR+ Power-on reset voltage level Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 0.95 1.30 1.51 V VPOR+ POR+Power-on reset voltage levelRising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ0.951.301.51V VPOR- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 0.9 1.25 1.48 V VPOR- POR-Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ0.91.251.48V VHYS, POR POR hysteresis #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 30 45 60 mV VHYS, POR HYS, PORPOR hysteresis #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ304560mV VBOR0+, COLD Brown-out reset voltage level 0 (default level) Cold start, rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 1.48 1.54 1.61 V VBOR0+, COLD BOR0+, COLDBrown-out reset voltage level 0 (default level)Cold start, rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ1.481.541.61V VBOR0+ Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 1.55 1.59 1.62 VBOR0+ BOR0+Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA1.551.591.62 VBOR0- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 1.54 1.58 1.61 VBOR0- BOR0-Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA1.541.581.61 VBOR0, STBY STANDBY mode #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 1.51 1.57 1.61 VBOR0, STBY BOR0, STBYSTANDBY mode #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ1.511.571.61 VBOR1+ Brown-out-reset voltage level 1 Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.13 2.18 2.23 V VBOR1+ BOR1+Brown-out-reset voltage level 1Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA2.132.182.23V VBOR1- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.10 2.15 2.19 VBOR1- BOR1-Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA2.102.152.19 VBOR2+ Brown-out-reset voltage level 2 Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.73 2.77 2.82 V VBOR2+ BOR2+Brown-out-reset voltage level 2Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA2.732.772.82V VBOR2- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.7 2.74 2.79 VBOR2- BOR2-Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA2.72.742.79 VBOR3+ Brown-out-reset voltage level 3 Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.88 2.97 3.04 V VBOR3+ BOR3+Brown-out-reset voltage level 3Rising #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA2.882.973.04V VBOR3- Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA 2.85 2.94 3.01 VBOR3- BOR3-Falling #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SF99G_ABDANA2.852.943.01 VHYS,BOR Brown-out reset hysteresis Level 0 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 15 21 mV VHYS,BOR HYS,BORBrown-out reset hysteresisLevel 0 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ1521mV Levels 1-3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ 34 40 Levels 1-3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376805/SFPV6IVOHUBJ3440 TPD, BOR BOR propagation delay RUN/SLEEP/STOP mode 10 us TPD, BOR PD, BORBOR propagation delayRUN/SLEEP/STOP mode10us STANDBY mode 100 us STANDBY mode100us \|dVDD/dt\| ≤ 3V/s Device operating in RUN, SLEEP, or STOP mode. \|dVDD/dt\| ≤ 3V/sDevice operating in RUN, SLEEP, or STOP mode. Power Supply Ramp shows the relationships of POR-, POR+, BOR0-, and BOR0+ during powerup and powerdown. Power Cycle POR and BOR Conditions Power Supply Ramp shows the relationships of POR-, POR+, BOR0-, and BOR0+ during powerup and powerdown. Power Cycle POR and BOR Conditions shows the relationships of POR-, POR+, BOR0-, and BOR0+ during powerup and powerdown. Power Cycle POR and BOR Conditions shows the relationships of POR-, POR+, BOR0-, and BOR0+ during powerup and powerdown. Power Cycle POR and BOR Conditions Power Cycle POR and BOR Conditions Flash Memory Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply VDDPGM/ERASE Program and erase supply voltage 1.62 3.6 V IDDERASE Supply current from VDD during erase operation Supply current delta 2 mA IDDPGM Supply current from VDD during program operation Supply current delta 2.5 mA Endurance NWEC(LOWER) Erase/program cycle endurance (lower 32kB flash) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER1 100 k cycles NWEC(UPPER) Erase/program cycle endurance (remaining flash) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER1 10 k cycles NE(MAX) Total erase operations before failure #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER2 802 k erase operations NW(MAX) Write operations per word line before sector erase #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER3 83 write operations Retention tRET_85 Flash memory data retention -40°C ≤Tj ≤ 85°C 60 years tRET_105 Flash memory data retention -40°C ≤Tj ≤ 105°C 11.4 years Program and Erase Timing tPROG (WORD, 64) Program time for flash word #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SF_BXS133C.K #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SFJ8_0982PVP 50 275 µs tPROG (SEC, 64) Program time for 1kB sector #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SFLOZC2V0Q1K #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SFJ8_0982PVP 6.4 ms tERASE (SEC) Sector erase time ≤2k erase/program cycles, Tj≥25°C 4 20 ms tERASE (SEC) Sector erase time ≤10k erase/program cycles, Tj≥25°C 20 150 ms tERASE (SEC) Sector erase time ≤10k erase/program cycles 20 200 ms tERASE (BANK) Bank erase time ≤10k erase/program cycles 22 220 ms The lower 32kB flash address space supports higher erase/program endurance to enable EEPROM emulation applications. On devices with <=32kB flash memory, the entire flash memory supports NWEC(LOWER) erase/program cycles. Total number of cumulative erase operations supported by the flash before failure. A sector erase or bank erase operation is considered to be one erase operation. Maximum number of write operations allowed per word line before the word line must be erased. If additional writes to the same word line are required, a sector erase is required once the maximum number of write operations per word line is reached. Program time is defined as the time from when the program command is triggered until the command completion interrupt flag is set in the flash controller. Sector program time is defined as the time from when the first word program command is triggered until the final word program command completes and the interrupt flag is set in the flash controller. This time includes the time needed for software to load each flash word (after the first flash word) into the flash controller during programming of the sector. Flash word size is 64 data bits (8 bytes). On devices with ECC, the total flash word size is 72 bits (64 data bits plus 8 ECC bits). Flash Memory Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply VDDPGM/ERASE Program and erase supply voltage 1.62 3.6 V IDDERASE Supply current from VDD during erase operation Supply current delta 2 mA IDDPGM Supply current from VDD during program operation Supply current delta 2.5 mA Endurance NWEC(LOWER) Erase/program cycle endurance (lower 32kB flash) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER1 100 k cycles NWEC(UPPER) Erase/program cycle endurance (remaining flash) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER1 10 k cycles NE(MAX) Total erase operations before failure #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER2 802 k erase operations NW(MAX) Write operations per word line before sector erase #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER3 83 write operations Retention tRET_85 Flash memory data retention -40°C ≤Tj ≤ 85°C 60 years tRET_105 Flash memory data retention -40°C ≤Tj ≤ 105°C 11.4 years Program and Erase Timing tPROG (WORD, 64) Program time for flash word #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SF_BXS133C.K #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SFJ8_0982PVP 50 275 µs tPROG (SEC, 64) Program time for 1kB sector #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SFLOZC2V0Q1K #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SFJ8_0982PVP 6.4 ms tERASE (SEC) Sector erase time ≤2k erase/program cycles, Tj≥25°C 4 20 ms tERASE (SEC) Sector erase time ≤10k erase/program cycles, Tj≥25°C 20 150 ms tERASE (SEC) Sector erase time ≤10k erase/program cycles 20 200 ms tERASE (BANK) Bank erase time ≤10k erase/program cycles 22 220 ms The lower 32kB flash address space supports higher erase/program endurance to enable EEPROM emulation applications. On devices with <=32kB flash memory, the entire flash memory supports NWEC(LOWER) erase/program cycles. Total number of cumulative erase operations supported by the flash before failure. A sector erase or bank erase operation is considered to be one erase operation. Maximum number of write operations allowed per word line before the word line must be erased. If additional writes to the same word line are required, a sector erase is required once the maximum number of write operations per word line is reached. Program time is defined as the time from when the program command is triggered until the command completion interrupt flag is set in the flash controller. Sector program time is defined as the time from when the first word program command is triggered until the final word program command completes and the interrupt flag is set in the flash controller. This time includes the time needed for software to load each flash word (after the first flash word) into the flash controller during programming of the sector. Flash word size is 64 data bits (8 bytes). On devices with ECC, the total flash word size is 72 bits (64 data bits plus 8 ECC bits). over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply VDDPGM/ERASE Program and erase supply voltage 1.62 3.6 V IDDERASE Supply current from VDD during erase operation Supply current delta 2 mA IDDPGM Supply current from VDD during program operation Supply current delta 2.5 mA Endurance NWEC(LOWER) Erase/program cycle endurance (lower 32kB flash) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER1 100 k cycles NWEC(UPPER) Erase/program cycle endurance (remaining flash) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER1 10 k cycles NE(MAX) Total erase operations before failure #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER2 802 k erase operations NW(MAX) Write operations per word line before sector erase #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER3 83 write operations Retention tRET_85 Flash memory data retention -40°C ≤Tj ≤ 85°C 60 years tRET_105 Flash memory data retention -40°C ≤Tj ≤ 105°C 11.4 years Program and Erase Timing tPROG (WORD, 64) Program time for flash word #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SF_BXS133C.K #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SFJ8_0982PVP 50 275 µs tPROG (SEC, 64) Program time for 1kB sector #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SFLOZC2V0Q1K #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SFJ8_0982PVP 6.4 ms tERASE (SEC) Sector erase time ≤2k erase/program cycles, Tj≥25°C 4 20 ms tERASE (SEC) Sector erase time ≤10k erase/program cycles, Tj≥25°C 20 150 ms tERASE (SEC) Sector erase time ≤10k erase/program cycles 20 200 ms tERASE (BANK) Bank erase time ≤10k erase/program cycles 22 220 ms over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply VDDPGM/ERASE Program and erase supply voltage 1.62 3.6 V IDDERASE Supply current from VDD during erase operation Supply current delta 2 mA IDDPGM Supply current from VDD during program operation Supply current delta 2.5 mA Endurance NWEC(LOWER) Erase/program cycle endurance (lower 32kB flash) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER1 100 k cycles NWEC(UPPER) Erase/program cycle endurance (remaining flash) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER1 10 k cycles NE(MAX) Total erase operations before failure #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER2 802 k erase operations NW(MAX) Write operations per word line before sector erase #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER3 83 write operations Retention tRET_85 Flash memory data retention -40°C ≤Tj ≤ 85°C 60 years tRET_105 Flash memory data retention -40°C ≤Tj ≤ 105°C 11.4 years Program and Erase Timing tPROG (WORD, 64) Program time for flash word #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SF_BXS133C.K #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SFJ8_0982PVP 50 275 µs tPROG (SEC, 64) Program time for 1kB sector #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SFLOZC2V0Q1K #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SFJ8_0982PVP 6.4 ms tERASE (SEC) Sector erase time ≤2k erase/program cycles, Tj≥25°C 4 20 ms tERASE (SEC) Sector erase time ≤10k erase/program cycles, Tj≥25°C 20 150 ms tERASE (SEC) Sector erase time ≤10k erase/program cycles 20 200 ms tERASE (BANK) Bank erase time ≤10k erase/program cycles 22 220 ms PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT Supply VDDPGM/ERASE Program and erase supply voltage 1.62 3.6 V IDDERASE Supply current from VDD during erase operation Supply current delta 2 mA IDDPGM Supply current from VDD during program operation Supply current delta 2.5 mA Endurance NWEC(LOWER) Erase/program cycle endurance (lower 32kB flash) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER1 100 k cycles NWEC(UPPER) Erase/program cycle endurance (remaining flash) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER1 10 k cycles NE(MAX) Total erase operations before failure #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER2 802 k erase operations NW(MAX) Write operations per word line before sector erase #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER3 83 write operations Retention tRET_85 Flash memory data retention -40°C ≤Tj ≤ 85°C 60 years tRET_105 Flash memory data retention -40°C ≤Tj ≤ 105°C 11.4 years Program and Erase Timing tPROG (WORD, 64) Program time for flash word #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SF_BXS133C.K #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SFJ8_0982PVP 50 275 µs tPROG (SEC, 64) Program time for 1kB sector #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SFLOZC2V0Q1K #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SFJ8_0982PVP 6.4 ms tERASE (SEC) Sector erase time ≤2k erase/program cycles, Tj≥25°C 4 20 ms tERASE (SEC) Sector erase time ≤10k erase/program cycles, Tj≥25°C 20 150 ms tERASE (SEC) Sector erase time ≤10k erase/program cycles 20 200 ms tERASE (BANK) Bank erase time ≤10k erase/program cycles 22 220 ms Supply Supply VDDPGM/ERASE Program and erase supply voltage 1.62 3.6 V VDDPGM/ERASE PGM/ERASEProgram and erase supply voltage1.623.6V IDDERASE Supply current from VDD during erase operation Supply current delta 2 mA IDDERASE ERASESupply current from VDD during erase operationSupply current delta2mA IDDPGM Supply current from VDD during program operation Supply current delta 2.5 mA IDDPGM PGMSupply current from VDD during program operationSupply current delta2.5mA Endurance Endurance NWEC(LOWER) Erase/program cycle endurance (lower 32kB flash) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER1 100 k cycles NWEC(LOWER) (LOWER)Erase/program cycle endurance (lower 32kB flash) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER1100k cycles NWEC(UPPER) Erase/program cycle endurance (remaining flash) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER1 10 k cycles NWEC(UPPER) (UPPER)Erase/program cycle endurance (remaining flash) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER110k cycles NE(MAX) Total erase operations before failure #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER2 802 k erase operations NE(MAX) (MAX)Total erase operations before failure #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER2 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER2802k erase operations NW(MAX) Write operations per word line before sector erase #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER3 83 write operations NW(MAX) (MAX)Write operations per word line before sector erase #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/A_LEGO_IP_FLASHCTL_STARFISH_1_FLASHMEMELECCHAR_FOOTER383write operations Retention Retention tRET_85 Flash memory data retention -40°C ≤Tj ≤ 85°C 60 years tRET_85 RET_85Flash memory data retention-40°C ≤Tj ≤ 85°Cj 60years tRET_105 Flash memory data retention -40°C ≤Tj ≤ 105°C 11.4 years tRET_105 RET_105Flash memory data retention-40°C ≤Tj ≤ 105°Cj 11.4years Program and Erase Timing Program and Erase Timing tPROG (WORD, 64) Program time for flash word #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SF_BXS133C.K #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SFJ8_0982PVP 50 275 µs tPROG (WORD, 64) PROG (WORD, 64)Program time for flash word #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SF_BXS133C.K #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SFJ8_0982PVP #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SF_BXS133C.K#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SFJ8_0982PVP50275µs tPROG (SEC, 64) Program time for 1kB sector #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SFLOZC2V0Q1K #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SFJ8_0982PVP 6.4 ms tPROG (SEC, 64) PROG (SEC, 64)Program time for 1kB sector #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SFLOZC2V0Q1K #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SFJ8_0982PVP #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SFLOZC2V0Q1K#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376782/SFJ8_0982PVP6.4ms tERASE (SEC) Sector erase time ≤2k erase/program cycles, Tj≥25°C 4 20 ms tERASE (SEC) ERASE (SEC)Sector erase time≤2k erase/program cycles, Tj≥25°Cj420ms tERASE (SEC) Sector erase time ≤10k erase/program cycles, Tj≥25°C 20 150 ms tERASE (SEC) ERASE (SEC)Sector erase time≤10k erase/program cycles, Tj≥25°Cj20150ms tERASE (SEC) Sector erase time ≤10k erase/program cycles 20 200 ms tERASE (SEC) ERASE (SEC)Sector erase time≤10k erase/program cycles20200ms tERASE (BANK) Bank erase time ≤10k erase/program cycles 22 220 ms tERASE (BANK) ERASE (BANK)Bank erase time≤10k erase/program cycles22220ms The lower 32kB flash address space supports higher erase/program endurance to enable EEPROM emulation applications. On devices with <=32kB flash memory, the entire flash memory supports NWEC(LOWER) erase/program cycles. Total number of cumulative erase operations supported by the flash before failure. A sector erase or bank erase operation is considered to be one erase operation. Maximum number of write operations allowed per word line before the word line must be erased. If additional writes to the same word line are required, a sector erase is required once the maximum number of write operations per word line is reached. Program time is defined as the time from when the program command is triggered until the command completion interrupt flag is set in the flash controller. Sector program time is defined as the time from when the first word program command is triggered until the final word program command completes and the interrupt flag is set in the flash controller. This time includes the time needed for software to load each flash word (after the first flash word) into the flash controller during programming of the sector. Flash word size is 64 data bits (8 bytes). On devices with ECC, the total flash word size is 72 bits (64 data bits plus 8 ECC bits). The lower 32kB flash address space supports higher erase/program endurance to enable EEPROM emulation applications. On devices with <=32kB flash memory, the entire flash memory supports NWEC(LOWER) erase/program cycles.(LOWER)Total number of cumulative erase operations supported by the flash before failure. A sector erase or bank erase operation is considered to be one erase operation.Maximum number of write operations allowed per word line before the word line must be erased. If additional writes to the same word line are required, a sector erase is required once the maximum number of write operations per word line is reached.Program time is defined as the time from when the program command is triggered until the command completion interrupt flag is set in the flash controller.Sector program time is defined as the time from when the first word program command is triggered until the final word program command completes and the interrupt flag is set in the flash controller. This time includes the time needed for software to load each flash word (after the first flash word) into the flash controller during programming of the sector.Flash word size is 64 data bits (8 bytes). On devices with ECC, the total flash word size is 72 bits (64 data bits plus 8 ECC bits). Timing Characteristics VDD=3.3V, Ta=25 ℃ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Wakeup Timing tWAKE, SLEEP Wakeup time from SLEEP to RUN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 2 cycles tWAKE, STOP Wakeup time from STOP1 to RUN (SYSOSC enabled) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 14 us Wakeup time from STOP2 to RUN (SYSOSC disabled) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 13 us tWAKE, STBY Wakeup time from STANDBY to RUN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 15 us tWAKE, SHDN Wakeup time from SHUTDOWN to RUN Fast boot enabled 214 us tWAKE, SHDN Wakeup time from SHUTDOWN to RUN Fast boot disabled 230 us Asynchronous Fast Clock Request Timing tDELAY Delay time from edge of asynchronous request to first 32MHz MCLK edge Mode is SLEEP2 0.9 us Mode is STOP1 2.4 us Mode is STOP2 0.9 us Mode is STANDBY1 3.2 us Startup Timing tSTART, RESET Device cold start-up time from reset/power-up #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFQMUUIAC0BH_SF1 Fast boot enabled 241 us Fast boot disabled 284 us NRST Timing tRST, BOOTRST Minimum pulse length on NRST pin to generate BOOTRST ULPCLK≥4MHz 2 us ULPCLK=32kHz 100 us tRST, POR Minimum pulse length on NRST pin to generate POR 1 s The wake-up time is measured from the edge of an external signal (GPIO wake-up event) to the time that the first CPU instruction is executed, with the GPIO glitch filter disabled (FILTEREN=0x0) and fast wake enabled (FASTWAKEONLY=1) The start-up time is measured from the time that VDD crosses VBOR0+ (cold start-up) to the time that the first instruction of the user program is executed. Timing Characteristics VDD=3.3V, Ta=25 ℃ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Wakeup Timing tWAKE, SLEEP Wakeup time from SLEEP to RUN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 2 cycles tWAKE, STOP Wakeup time from STOP1 to RUN (SYSOSC enabled) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 14 us Wakeup time from STOP2 to RUN (SYSOSC disabled) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 13 us tWAKE, STBY Wakeup time from STANDBY to RUN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 15 us tWAKE, SHDN Wakeup time from SHUTDOWN to RUN Fast boot enabled 214 us tWAKE, SHDN Wakeup time from SHUTDOWN to RUN Fast boot disabled 230 us Asynchronous Fast Clock Request Timing tDELAY Delay time from edge of asynchronous request to first 32MHz MCLK edge Mode is SLEEP2 0.9 us Mode is STOP1 2.4 us Mode is STOP2 0.9 us Mode is STANDBY1 3.2 us Startup Timing tSTART, RESET Device cold start-up time from reset/power-up #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFQMUUIAC0BH_SF1 Fast boot enabled 241 us Fast boot disabled 284 us NRST Timing tRST, BOOTRST Minimum pulse length on NRST pin to generate BOOTRST ULPCLK≥4MHz 2 us ULPCLK=32kHz 100 us tRST, POR Minimum pulse length on NRST pin to generate POR 1 s The wake-up time is measured from the edge of an external signal (GPIO wake-up event) to the time that the first CPU instruction is executed, with the GPIO glitch filter disabled (FILTEREN=0x0) and fast wake enabled (FASTWAKEONLY=1) The start-up time is measured from the time that VDD crosses VBOR0+ (cold start-up) to the time that the first instruction of the user program is executed. VDD=3.3V, Ta=25 ℃ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Wakeup Timing tWAKE, SLEEP Wakeup time from SLEEP to RUN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 2 cycles tWAKE, STOP Wakeup time from STOP1 to RUN (SYSOSC enabled) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 14 us Wakeup time from STOP2 to RUN (SYSOSC disabled) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 13 us tWAKE, STBY Wakeup time from STANDBY to RUN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 15 us tWAKE, SHDN Wakeup time from SHUTDOWN to RUN Fast boot enabled 214 us tWAKE, SHDN Wakeup time from SHUTDOWN to RUN Fast boot disabled 230 us Asynchronous Fast Clock Request Timing tDELAY Delay time from edge of asynchronous request to first 32MHz MCLK edge Mode is SLEEP2 0.9 us Mode is STOP1 2.4 us Mode is STOP2 0.9 us Mode is STANDBY1 3.2 us Startup Timing tSTART, RESET Device cold start-up time from reset/power-up #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFQMUUIAC0BH_SF1 Fast boot enabled 241 us Fast boot disabled 284 us NRST Timing tRST, BOOTRST Minimum pulse length on NRST pin to generate BOOTRST ULPCLK≥4MHz 2 us ULPCLK=32kHz 100 us tRST, POR Minimum pulse length on NRST pin to generate POR 1 s VDD=3.3V, Ta=25 ℃ (unless otherwise noted)a PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Wakeup Timing tWAKE, SLEEP Wakeup time from SLEEP to RUN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 2 cycles tWAKE, STOP Wakeup time from STOP1 to RUN (SYSOSC enabled) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 14 us Wakeup time from STOP2 to RUN (SYSOSC disabled) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 13 us tWAKE, STBY Wakeup time from STANDBY to RUN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 15 us tWAKE, SHDN Wakeup time from SHUTDOWN to RUN Fast boot enabled 214 us tWAKE, SHDN Wakeup time from SHUTDOWN to RUN Fast boot disabled 230 us Asynchronous Fast Clock Request Timing tDELAY Delay time from edge of asynchronous request to first 32MHz MCLK edge Mode is SLEEP2 0.9 us Mode is STOP1 2.4 us Mode is STOP2 0.9 us Mode is STANDBY1 3.2 us Startup Timing tSTART, RESET Device cold start-up time from reset/power-up #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFQMUUIAC0BH_SF1 Fast boot enabled 241 us Fast boot disabled 284 us NRST Timing tRST, BOOTRST Minimum pulse length on NRST pin to generate BOOTRST ULPCLK≥4MHz 2 us ULPCLK=32kHz 100 us tRST, POR Minimum pulse length on NRST pin to generate POR 1 s PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT Wakeup Timing tWAKE, SLEEP Wakeup time from SLEEP to RUN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 2 cycles tWAKE, STOP Wakeup time from STOP1 to RUN (SYSOSC enabled) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 14 us Wakeup time from STOP2 to RUN (SYSOSC disabled) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 13 us tWAKE, STBY Wakeup time from STANDBY to RUN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 15 us tWAKE, SHDN Wakeup time from SHUTDOWN to RUN Fast boot enabled 214 us tWAKE, SHDN Wakeup time from SHUTDOWN to RUN Fast boot disabled 230 us Asynchronous Fast Clock Request Timing tDELAY Delay time from edge of asynchronous request to first 32MHz MCLK edge Mode is SLEEP2 0.9 us Mode is STOP1 2.4 us Mode is STOP2 0.9 us Mode is STANDBY1 3.2 us Startup Timing tSTART, RESET Device cold start-up time from reset/power-up #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFQMUUIAC0BH_SF1 Fast boot enabled 241 us Fast boot disabled 284 us NRST Timing tRST, BOOTRST Minimum pulse length on NRST pin to generate BOOTRST ULPCLK≥4MHz 2 us ULPCLK=32kHz 100 us tRST, POR Minimum pulse length on NRST pin to generate POR 1 s Wakeup Timing Wakeup Timing tWAKE, SLEEP Wakeup time from SLEEP to RUN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 2 cycles tWAKE, SLEEP WAKE, SLEEPWakeup time from SLEEP to RUN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF12cycles tWAKE, STOP Wakeup time from STOP1 to RUN (SYSOSC enabled) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 14 us tWAKE, STOP WAKE, STOPWakeup time from STOP1 to RUN (SYSOSC enabled) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF114us Wakeup time from STOP2 to RUN (SYSOSC disabled) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 13 us Wakeup time from STOP2 to RUN (SYSOSC disabled) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF113us tWAKE, STBY Wakeup time from STANDBY to RUN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 15 us tWAKE, STBY WAKE, STBYWakeup time from STANDBY to RUN #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFL_X17AKF31_SF115us tWAKE, SHDN Wakeup time from SHUTDOWN to RUN Fast boot enabled 214 us tWAKE, SHDN WAKE, SHDNWakeup time from SHUTDOWN to RUNFast boot enabled214us tWAKE, SHDN Wakeup time from SHUTDOWN to RUN Fast boot disabled 230 us tWAKE, SHDN WAKE, SHDNWakeup time from SHUTDOWN to RUNFast boot disabled230us Asynchronous Fast Clock Request Timing Asynchronous Fast Clock Request Timing tDELAY Delay time from edge of asynchronous request to first 32MHz MCLK edge Mode is SLEEP2 0.9 us tDELAY DELAYDelay time from edge of asynchronous request to first 32MHz MCLK edgeMode is SLEEP20.9us Mode is STOP1 2.4 us Mode is STOP12.4us Mode is STOP2 0.9 us Mode is STOP20.9us Mode is STANDBY1 3.2 us Mode is STANDBY13.2us Startup Timing Startup Timing tSTART, RESET Device cold start-up time from reset/power-up #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFQMUUIAC0BH_SF1 Fast boot enabled 241 us tSTART, RESET START, RESETDevice cold start-up time from reset/power-up #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFQMUUIAC0BH_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376826/SFQMUUIAC0BH_SF1Fast boot enabled241us Fast boot disabled 284 us Fast boot disabled284us NRST Timing NRST Timing tRST, BOOTRST Minimum pulse length on NRST pin to generate BOOTRST ULPCLK≥4MHz 2 us tRST, BOOTRST RST, BOOTRSTMinimum pulse length on NRST pin to generate BOOTRSTULPCLK≥4MHz2us ULPCLK=32kHz 100 us ULPCLK=32kHz100us tRST, POR Minimum pulse length on NRST pin to generate POR 1 s tRST, POR RST, PORMinimum pulse length on NRST pin to generate POR1s The wake-up time is measured from the edge of an external signal (GPIO wake-up event) to the time that the first CPU instruction is executed, with the GPIO glitch filter disabled (FILTEREN=0x0) and fast wake enabled (FASTWAKEONLY=1) The start-up time is measured from the time that VDD crosses VBOR0+ (cold start-up) to the time that the first instruction of the user program is executed. The wake-up time is measured from the edge of an external signal (GPIO wake-up event) to the time that the first CPU instruction is executed, with the GPIO glitch filter disabled (FILTEREN=0x0) and fast wake enabled (FASTWAKEONLY=1)The start-up time is measured from the time that VDD crosses VBOR0+ (cold start-up) to the time that the first instruction of the user program is executed. Clock Specifications System Oscillator (SYSOSC) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSYSOSC Factory trimmed SYSOSC frequency SYSOSCCFG.FREQ=00 (BASE) 32 MHz SYSOSCCFG.FREQ=01 4 User trimmed SYSOSC frequency SYSOSCCFG.FREQ=10, SYSOSCTRIMUSER.FREQ=10 24 SYSOSCCFG.FREQ=10, SYSOSCTRIMUSER.FREQ=01 16 SYSOSC frequency accuracy when frequency correction loop (FCL) is enabled and an ideal ROSC resistor is assumed #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SF880TXESCLO SETUSEFCL=1, Ta = 25°C -0.41 0.58 % SETUSEFCL=1, -40°C ≤ Ta ≤ 85°C -0.80 0.93 SETUSEFCL=1, -40°C ≤ Ta ≤ 105°C -0.80 1.09 SETUSEFCL=1, -40°C ≤ Ta ≤ 125°C -0.80 1.30 SYSOSC accuracy when frequency correction loop (FCL) is enabled with ROSC resistor put at ROSC pin, for factory trimmed frequencies #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ SETUSEFCL=1, Ta = 25°C, ±0.1% ±25ppm ROSC –0.5 0.7 % SETUSEFCL=1, -40°C ≤ Ta ≤ 85°C, ±0.1% ±25ppm ROSC –1.1 1.2 SETUSEFCL=1, -40°C ≤ Ta ≤ 105°C, ±0.1% ±25ppm ROSC –1.1 1.4 SETUSEFCL=1, -40°C ≤ Ta ≤ 125°C, ±0.1% ±25ppm ROSC –1.1 1.7 SYSOSC accuracy when frequency correction loop (FCL) is disabled, 32MHz SETUSEFCL=0, SYSOSCCFG.FREQ=00, -40°C ≤ Ta ≤ 125°C –2.6 1.8 % fSYSOSC SYSOSC accuracy when frequency correction loop (FCL) is disabled, for factory trimmed frequencies, 4MHz SETUSEFCL=0, SYSOSCCFG.FREQ=01, -40°C ≤ Ta ≤ 125°C –2.7 2.3 % ROSC External resistor put between ROSC pin and VSS #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ SETUSEFCL=1 100 kΩ tsettle, SYSOSC Settling time to target accuracy #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SF0D42GVUNIM SETUSEFCL=1, ±0.1% 25ppm ROSC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ 30 us fsettle, SYSOSC fSYSOSC additional undershoot accuracy during tsettle #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SF0D42GVUNIM SETUSEFCL=1, ±0.1% 25ppm ROSC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ -11 % The SYSOSC frequency correction loop (FCL) enables high SYSOSC accuracy via an external reference resistor (ROSC) which must be connected between the device ROSC pin and VSS when using the FCL. Accuracies are shown for a ±0.1% ±25ppm ROSC; relaxed tolerance resistors may also be used (with reduced SYSOSC accuracy). See the SYSOSC section of the technical reference manual for details on computing SYSOSC accuracy for various ROSC accuracies. ROSC does not need to be populated if the FCL is not enabled. Represents the device accuracy only. The tolerance and temperature drift of the ROSC resistor used must be combined with this spec to determine final accuracy. Performance for a ±0.1% ±25ppm ROSC is given as a reference point. When SYSOSC is waking up (for example, when exiting a low power mode) and FCL is enabled, the SYSOSC will initially undershoot the target frequency fSYSOSC by an additional error of up to fsettle,SYSOSC for the time tsettle,SYSOSC, after which the target accuracy is achieved. Low Frequency Oscillator (LFOSC) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fLFOSC LFOSC frequency 32768 Hz LFOSC accuracy -40 ℃ ≤ Ta ≤ 125 ℃ –5 5 % -40 ℃ ≤ Ta ≤ 85 ℃ –3 3 % tstart, LFOSC LFOSC start-up time 1.7 ms Clock Specifications System Oscillator (SYSOSC) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSYSOSC Factory trimmed SYSOSC frequency SYSOSCCFG.FREQ=00 (BASE) 32 MHz SYSOSCCFG.FREQ=01 4 User trimmed SYSOSC frequency SYSOSCCFG.FREQ=10, SYSOSCTRIMUSER.FREQ=10 24 SYSOSCCFG.FREQ=10, SYSOSCTRIMUSER.FREQ=01 16 SYSOSC frequency accuracy when frequency correction loop (FCL) is enabled and an ideal ROSC resistor is assumed #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SF880TXESCLO SETUSEFCL=1, Ta = 25°C -0.41 0.58 % SETUSEFCL=1, -40°C ≤ Ta ≤ 85°C -0.80 0.93 SETUSEFCL=1, -40°C ≤ Ta ≤ 105°C -0.80 1.09 SETUSEFCL=1, -40°C ≤ Ta ≤ 125°C -0.80 1.30 SYSOSC accuracy when frequency correction loop (FCL) is enabled with ROSC resistor put at ROSC pin, for factory trimmed frequencies #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ SETUSEFCL=1, Ta = 25°C, ±0.1% ±25ppm ROSC –0.5 0.7 % SETUSEFCL=1, -40°C ≤ Ta ≤ 85°C, ±0.1% ±25ppm ROSC –1.1 1.2 SETUSEFCL=1, -40°C ≤ Ta ≤ 105°C, ±0.1% ±25ppm ROSC –1.1 1.4 SETUSEFCL=1, -40°C ≤ Ta ≤ 125°C, ±0.1% ±25ppm ROSC –1.1 1.7 SYSOSC accuracy when frequency correction loop (FCL) is disabled, 32MHz SETUSEFCL=0, SYSOSCCFG.FREQ=00, -40°C ≤ Ta ≤ 125°C –2.6 1.8 % fSYSOSC SYSOSC accuracy when frequency correction loop (FCL) is disabled, for factory trimmed frequencies, 4MHz SETUSEFCL=0, SYSOSCCFG.FREQ=01, -40°C ≤ Ta ≤ 125°C –2.7 2.3 % ROSC External resistor put between ROSC pin and VSS #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ SETUSEFCL=1 100 kΩ tsettle, SYSOSC Settling time to target accuracy #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SF0D42GVUNIM SETUSEFCL=1, ±0.1% 25ppm ROSC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ 30 us fsettle, SYSOSC fSYSOSC additional undershoot accuracy during tsettle #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SF0D42GVUNIM SETUSEFCL=1, ±0.1% 25ppm ROSC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ -11 % The SYSOSC frequency correction loop (FCL) enables high SYSOSC accuracy via an external reference resistor (ROSC) which must be connected between the device ROSC pin and VSS when using the FCL. Accuracies are shown for a ±0.1% ±25ppm ROSC; relaxed tolerance resistors may also be used (with reduced SYSOSC accuracy). See the SYSOSC section of the technical reference manual for details on computing SYSOSC accuracy for various ROSC accuracies. ROSC does not need to be populated if the FCL is not enabled. Represents the device accuracy only. The tolerance and temperature drift of the ROSC resistor used must be combined with this spec to determine final accuracy. Performance for a ±0.1% ±25ppm ROSC is given as a reference point. When SYSOSC is waking up (for example, when exiting a low power mode) and FCL is enabled, the SYSOSC will initially undershoot the target frequency fSYSOSC by an additional error of up to fsettle,SYSOSC for the time tsettle,SYSOSC, after which the target accuracy is achieved. System Oscillator (SYSOSC) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSYSOSC Factory trimmed SYSOSC frequency SYSOSCCFG.FREQ=00 (BASE) 32 MHz SYSOSCCFG.FREQ=01 4 User trimmed SYSOSC frequency SYSOSCCFG.FREQ=10, SYSOSCTRIMUSER.FREQ=10 24 SYSOSCCFG.FREQ=10, SYSOSCTRIMUSER.FREQ=01 16 SYSOSC frequency accuracy when frequency correction loop (FCL) is enabled and an ideal ROSC resistor is assumed #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SF880TXESCLO SETUSEFCL=1, Ta = 25°C -0.41 0.58 % SETUSEFCL=1, -40°C ≤ Ta ≤ 85°C -0.80 0.93 SETUSEFCL=1, -40°C ≤ Ta ≤ 105°C -0.80 1.09 SETUSEFCL=1, -40°C ≤ Ta ≤ 125°C -0.80 1.30 SYSOSC accuracy when frequency correction loop (FCL) is enabled with ROSC resistor put at ROSC pin, for factory trimmed frequencies #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ SETUSEFCL=1, Ta = 25°C, ±0.1% ±25ppm ROSC –0.5 0.7 % SETUSEFCL=1, -40°C ≤ Ta ≤ 85°C, ±0.1% ±25ppm ROSC –1.1 1.2 SETUSEFCL=1, -40°C ≤ Ta ≤ 105°C, ±0.1% ±25ppm ROSC –1.1 1.4 SETUSEFCL=1, -40°C ≤ Ta ≤ 125°C, ±0.1% ±25ppm ROSC –1.1 1.7 SYSOSC accuracy when frequency correction loop (FCL) is disabled, 32MHz SETUSEFCL=0, SYSOSCCFG.FREQ=00, -40°C ≤ Ta ≤ 125°C –2.6 1.8 % fSYSOSC SYSOSC accuracy when frequency correction loop (FCL) is disabled, for factory trimmed frequencies, 4MHz SETUSEFCL=0, SYSOSCCFG.FREQ=01, -40°C ≤ Ta ≤ 125°C –2.7 2.3 % ROSC External resistor put between ROSC pin and VSS #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ SETUSEFCL=1 100 kΩ tsettle, SYSOSC Settling time to target accuracy #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SF0D42GVUNIM SETUSEFCL=1, ±0.1% 25ppm ROSC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ 30 us fsettle, SYSOSC fSYSOSC additional undershoot accuracy during tsettle #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SF0D42GVUNIM SETUSEFCL=1, ±0.1% 25ppm ROSC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ -11 % The SYSOSC frequency correction loop (FCL) enables high SYSOSC accuracy via an external reference resistor (ROSC) which must be connected between the device ROSC pin and VSS when using the FCL. Accuracies are shown for a ±0.1% ±25ppm ROSC; relaxed tolerance resistors may also be used (with reduced SYSOSC accuracy). See the SYSOSC section of the technical reference manual for details on computing SYSOSC accuracy for various ROSC accuracies. ROSC does not need to be populated if the FCL is not enabled. Represents the device accuracy only. The tolerance and temperature drift of the ROSC resistor used must be combined with this spec to determine final accuracy. Performance for a ±0.1% ±25ppm ROSC is given as a reference point. When SYSOSC is waking up (for example, when exiting a low power mode) and FCL is enabled, the SYSOSC will initially undershoot the target frequency fSYSOSC by an additional error of up to fsettle,SYSOSC for the time tsettle,SYSOSC, after which the target accuracy is achieved. over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSYSOSC Factory trimmed SYSOSC frequency SYSOSCCFG.FREQ=00 (BASE) 32 MHz SYSOSCCFG.FREQ=01 4 User trimmed SYSOSC frequency SYSOSCCFG.FREQ=10, SYSOSCTRIMUSER.FREQ=10 24 SYSOSCCFG.FREQ=10, SYSOSCTRIMUSER.FREQ=01 16 SYSOSC frequency accuracy when frequency correction loop (FCL) is enabled and an ideal ROSC resistor is assumed #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SF880TXESCLO SETUSEFCL=1, Ta = 25°C -0.41 0.58 % SETUSEFCL=1, -40°C ≤ Ta ≤ 85°C -0.80 0.93 SETUSEFCL=1, -40°C ≤ Ta ≤ 105°C -0.80 1.09 SETUSEFCL=1, -40°C ≤ Ta ≤ 125°C -0.80 1.30 SYSOSC accuracy when frequency correction loop (FCL) is enabled with ROSC resistor put at ROSC pin, for factory trimmed frequencies #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ SETUSEFCL=1, Ta = 25°C, ±0.1% ±25ppm ROSC –0.5 0.7 % SETUSEFCL=1, -40°C ≤ Ta ≤ 85°C, ±0.1% ±25ppm ROSC –1.1 1.2 SETUSEFCL=1, -40°C ≤ Ta ≤ 105°C, ±0.1% ±25ppm ROSC –1.1 1.4 SETUSEFCL=1, -40°C ≤ Ta ≤ 125°C, ±0.1% ±25ppm ROSC –1.1 1.7 SYSOSC accuracy when frequency correction loop (FCL) is disabled, 32MHz SETUSEFCL=0, SYSOSCCFG.FREQ=00, -40°C ≤ Ta ≤ 125°C –2.6 1.8 % fSYSOSC SYSOSC accuracy when frequency correction loop (FCL) is disabled, for factory trimmed frequencies, 4MHz SETUSEFCL=0, SYSOSCCFG.FREQ=01, -40°C ≤ Ta ≤ 125°C –2.7 2.3 % ROSC External resistor put between ROSC pin and VSS #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ SETUSEFCL=1 100 kΩ tsettle, SYSOSC Settling time to target accuracy #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SF0D42GVUNIM SETUSEFCL=1, ±0.1% 25ppm ROSC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ 30 us fsettle, SYSOSC fSYSOSC additional undershoot accuracy during tsettle #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SF0D42GVUNIM SETUSEFCL=1, ±0.1% 25ppm ROSC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ -11 % over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSYSOSC Factory trimmed SYSOSC frequency SYSOSCCFG.FREQ=00 (BASE) 32 MHz SYSOSCCFG.FREQ=01 4 User trimmed SYSOSC frequency SYSOSCCFG.FREQ=10, SYSOSCTRIMUSER.FREQ=10 24 SYSOSCCFG.FREQ=10, SYSOSCTRIMUSER.FREQ=01 16 SYSOSC frequency accuracy when frequency correction loop (FCL) is enabled and an ideal ROSC resistor is assumed #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SF880TXESCLO SETUSEFCL=1, Ta = 25°C -0.41 0.58 % SETUSEFCL=1, -40°C ≤ Ta ≤ 85°C -0.80 0.93 SETUSEFCL=1, -40°C ≤ Ta ≤ 105°C -0.80 1.09 SETUSEFCL=1, -40°C ≤ Ta ≤ 125°C -0.80 1.30 SYSOSC accuracy when frequency correction loop (FCL) is enabled with ROSC resistor put at ROSC pin, for factory trimmed frequencies #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ SETUSEFCL=1, Ta = 25°C, ±0.1% ±25ppm ROSC –0.5 0.7 % SETUSEFCL=1, -40°C ≤ Ta ≤ 85°C, ±0.1% ±25ppm ROSC –1.1 1.2 SETUSEFCL=1, -40°C ≤ Ta ≤ 105°C, ±0.1% ±25ppm ROSC –1.1 1.4 SETUSEFCL=1, -40°C ≤ Ta ≤ 125°C, ±0.1% ±25ppm ROSC –1.1 1.7 SYSOSC accuracy when frequency correction loop (FCL) is disabled, 32MHz SETUSEFCL=0, SYSOSCCFG.FREQ=00, -40°C ≤ Ta ≤ 125°C –2.6 1.8 % fSYSOSC SYSOSC accuracy when frequency correction loop (FCL) is disabled, for factory trimmed frequencies, 4MHz SETUSEFCL=0, SYSOSCCFG.FREQ=01, -40°C ≤ Ta ≤ 125°C –2.7 2.3 % ROSC External resistor put between ROSC pin and VSS #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ SETUSEFCL=1 100 kΩ tsettle, SYSOSC Settling time to target accuracy #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SF0D42GVUNIM SETUSEFCL=1, ±0.1% 25ppm ROSC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ 30 us fsettle, SYSOSC fSYSOSC additional undershoot accuracy during tsettle #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SF0D42GVUNIM SETUSEFCL=1, ±0.1% 25ppm ROSC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ -11 % PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT fSYSOSC Factory trimmed SYSOSC frequency SYSOSCCFG.FREQ=00 (BASE) 32 MHz SYSOSCCFG.FREQ=01 4 User trimmed SYSOSC frequency SYSOSCCFG.FREQ=10, SYSOSCTRIMUSER.FREQ=10 24 SYSOSCCFG.FREQ=10, SYSOSCTRIMUSER.FREQ=01 16 SYSOSC frequency accuracy when frequency correction loop (FCL) is enabled and an ideal ROSC resistor is assumed #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SF880TXESCLO SETUSEFCL=1, Ta = 25°C -0.41 0.58 % SETUSEFCL=1, -40°C ≤ Ta ≤ 85°C -0.80 0.93 SETUSEFCL=1, -40°C ≤ Ta ≤ 105°C -0.80 1.09 SETUSEFCL=1, -40°C ≤ Ta ≤ 125°C -0.80 1.30 SYSOSC accuracy when frequency correction loop (FCL) is enabled with ROSC resistor put at ROSC pin, for factory trimmed frequencies #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ SETUSEFCL=1, Ta = 25°C, ±0.1% ±25ppm ROSC –0.5 0.7 % SETUSEFCL=1, -40°C ≤ Ta ≤ 85°C, ±0.1% ±25ppm ROSC –1.1 1.2 SETUSEFCL=1, -40°C ≤ Ta ≤ 105°C, ±0.1% ±25ppm ROSC –1.1 1.4 SETUSEFCL=1, -40°C ≤ Ta ≤ 125°C, ±0.1% ±25ppm ROSC –1.1 1.7 SYSOSC accuracy when frequency correction loop (FCL) is disabled, 32MHz SETUSEFCL=0, SYSOSCCFG.FREQ=00, -40°C ≤ Ta ≤ 125°C –2.6 1.8 % fSYSOSC SYSOSC accuracy when frequency correction loop (FCL) is disabled, for factory trimmed frequencies, 4MHz SETUSEFCL=0, SYSOSCCFG.FREQ=01, -40°C ≤ Ta ≤ 125°C –2.7 2.3 % ROSC External resistor put between ROSC pin and VSS #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ SETUSEFCL=1 100 kΩ tsettle, SYSOSC Settling time to target accuracy #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SF0D42GVUNIM SETUSEFCL=1, ±0.1% 25ppm ROSC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ 30 us fsettle, SYSOSC fSYSOSC additional undershoot accuracy during tsettle #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SF0D42GVUNIM SETUSEFCL=1, ±0.1% 25ppm ROSC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ -11 % fSYSOSC Factory trimmed SYSOSC frequency SYSOSCCFG.FREQ=00 (BASE) 32 MHz fSYSOSC SYSOSCFactory trimmed SYSOSC frequencySYSOSCCFG.FREQ=00 (BASE)32MHz SYSOSCCFG.FREQ=01 4 SYSOSCCFG.FREQ=014 User trimmed SYSOSC frequency SYSOSCCFG.FREQ=10, SYSOSCTRIMUSER.FREQ=10 24 User trimmed SYSOSC frequencySYSOSCCFG.FREQ=10, SYSOSCTRIMUSER.FREQ=1024 SYSOSCCFG.FREQ=10, SYSOSCTRIMUSER.FREQ=01 16 SYSOSCCFG.FREQ=10, SYSOSCTRIMUSER.FREQ=0116 SYSOSC frequency accuracy when frequency correction loop (FCL) is enabled and an ideal ROSC resistor is assumed #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SF880TXESCLO SETUSEFCL=1, Ta = 25°C -0.41 0.58 % SYSOSC frequency accuracy when frequency correction loop (FCL) is enabled and an ideal ROSC resistor is assumed #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SF880TXESCLO #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SF880TXESCLOSETUSEFCL=1, Ta = 25°Ca-0.410.58% SETUSEFCL=1, -40°C ≤ Ta ≤ 85°C -0.80 0.93 SETUSEFCL=1, -40°C ≤ Ta ≤ 85°Ca-0.800.93 SETUSEFCL=1, -40°C ≤ Ta ≤ 105°C -0.80 1.09 SETUSEFCL=1, -40°C ≤ Ta ≤ 105°Ca-0.801.09 SETUSEFCL=1, -40°C ≤ Ta ≤ 125°C -0.80 1.30 SETUSEFCL=1, -40°C ≤ Ta ≤ 125°Ca-0.801.30 SYSOSC accuracy when frequency correction loop (FCL) is enabled with ROSC resistor put at ROSC pin, for factory trimmed frequencies #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ SETUSEFCL=1, Ta = 25°C, ±0.1% ±25ppm ROSC –0.5 0.7 % SYSOSC accuracy when frequency correction loop (FCL) is enabled with ROSC resistor put at ROSC pin, for factory trimmed frequencies #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ OSCOSC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZSETUSEFCL=1, Ta = 25°C, ±0.1% ±25ppm ROSC aOSC–0.50.7% SETUSEFCL=1, -40°C ≤ Ta ≤ 85°C, ±0.1% ±25ppm ROSC –1.1 1.2 SETUSEFCL=1, -40°C ≤ Ta ≤ 85°C, ±0.1% ±25ppm ROSC aOSC–1.11.2 SETUSEFCL=1, -40°C ≤ Ta ≤ 105°C, ±0.1% ±25ppm ROSC –1.1 1.4 SETUSEFCL=1, -40°C ≤ Ta ≤ 105°C, ±0.1% ±25ppm ROSC aOSC–1.11.4 SETUSEFCL=1, -40°C ≤ Ta ≤ 125°C, ±0.1% ±25ppm ROSC –1.1 1.7 SETUSEFCL=1, -40°C ≤ Ta ≤ 125°C, ±0.1% ±25ppm ROSC aOSC–1.11.7 SYSOSC accuracy when frequency correction loop (FCL) is disabled, 32MHz SETUSEFCL=0, SYSOSCCFG.FREQ=00, -40°C ≤ Ta ≤ 125°C –2.6 1.8 % SYSOSC accuracy when frequency correction loop (FCL) is disabled, 32MHzSETUSEFCL=0, SYSOSCCFG.FREQ=00, -40°C ≤ Ta ≤ 125°Ca–2.61.8% fSYSOSC SYSOSC accuracy when frequency correction loop (FCL) is disabled, for factory trimmed frequencies, 4MHz SETUSEFCL=0, SYSOSCCFG.FREQ=01, -40°C ≤ Ta ≤ 125°C –2.7 2.3 % fSYSOSC SYSOSCSYSOSC accuracy when frequency correction loop (FCL) is disabled, for factory trimmed frequencies, 4MHzSETUSEFCL=0, SYSOSCCFG.FREQ=01, -40°C ≤ Ta ≤ 125°Ca–2.72.3% ROSC External resistor put between ROSC pin and VSS #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ SETUSEFCL=1 100 kΩ ROSC OSCExternal resistor put between ROSC pin and VSS #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZSETUSEFCL=1100kΩ tsettle, SYSOSC Settling time to target accuracy #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SF0D42GVUNIM SETUSEFCL=1, ±0.1% 25ppm ROSC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ 30 us tsettle, SYSOSC settle, SYSOSCSettling time to target accuracy #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SF0D42GVUNIM #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SF0D42GVUNIMSETUSEFCL=1, ±0.1% 25ppm ROSC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ OSC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ30us fsettle, SYSOSC fSYSOSC additional undershoot accuracy during tsettle #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SF0D42GVUNIM SETUSEFCL=1, ±0.1% 25ppm ROSC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ -11 % fsettle, SYSOSC settle, SYSOSCfSYSOSC additional undershoot accuracy during tsettle #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SF0D42GVUNIM SYSOSCsettle #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SF0D42GVUNIMSETUSEFCL=1, ±0.1% 25ppm ROSC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ OSC #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376775/SFX3R2V09BVZ-11% The SYSOSC frequency correction loop (FCL) enables high SYSOSC accuracy via an external reference resistor (ROSC) which must be connected between the device ROSC pin and VSS when using the FCL. Accuracies are shown for a ±0.1% ±25ppm ROSC; relaxed tolerance resistors may also be used (with reduced SYSOSC accuracy). See the SYSOSC section of the technical reference manual for details on computing SYSOSC accuracy for various ROSC accuracies. ROSC does not need to be populated if the FCL is not enabled. Represents the device accuracy only. The tolerance and temperature drift of the ROSC resistor used must be combined with this spec to determine final accuracy. Performance for a ±0.1% ±25ppm ROSC is given as a reference point. When SYSOSC is waking up (for example, when exiting a low power mode) and FCL is enabled, the SYSOSC will initially undershoot the target frequency fSYSOSC by an additional error of up to fsettle,SYSOSC for the time tsettle,SYSOSC, after which the target accuracy is achieved. The SYSOSC frequency correction loop (FCL) enables high SYSOSC accuracy via an external reference resistor (ROSC) which must be connected between the device ROSC pin and VSS when using the FCL. Accuracies are shown for a ±0.1% ±25ppm ROSC; relaxed tolerance resistors may also be used (with reduced SYSOSC accuracy). See the SYSOSC section of the technical reference manual for details on computing SYSOSC accuracy for various ROSC accuracies. ROSC does not need to be populated if the FCL is not enabled.OSCOSCOSCOSCRepresents the device accuracy only. The tolerance and temperature drift of the ROSC resistor used must be combined with this spec to determine final accuracy. Performance for a ±0.1% ±25ppm ROSC is given as a reference point.OSCWhen SYSOSC is waking up (for example, when exiting a low power mode) and FCL is enabled, the SYSOSC will initially undershoot the target frequency fSYSOSC by an additional error of up to fsettle,SYSOSC for the time tsettle,SYSOSC, after which the target accuracy is achieved.SYSOSCsettle,SYSOSCsettle,SYSOSC Low Frequency Oscillator (LFOSC) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fLFOSC LFOSC frequency 32768 Hz LFOSC accuracy -40 ℃ ≤ Ta ≤ 125 ℃ –5 5 % -40 ℃ ≤ Ta ≤ 85 ℃ –3 3 % tstart, LFOSC LFOSC start-up time 1.7 ms Low Frequency Oscillator (LFOSC) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fLFOSC LFOSC frequency 32768 Hz LFOSC accuracy -40 ℃ ≤ Ta ≤ 125 ℃ –5 5 % -40 ℃ ≤ Ta ≤ 85 ℃ –3 3 % tstart, LFOSC LFOSC start-up time 1.7 ms over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fLFOSC LFOSC frequency 32768 Hz LFOSC accuracy -40 ℃ ≤ Ta ≤ 125 ℃ –5 5 % -40 ℃ ≤ Ta ≤ 85 ℃ –3 3 % tstart, LFOSC LFOSC start-up time 1.7 ms over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fLFOSC LFOSC frequency 32768 Hz LFOSC accuracy -40 ℃ ≤ Ta ≤ 125 ℃ –5 5 % -40 ℃ ≤ Ta ≤ 85 ℃ –3 3 % tstart, LFOSC LFOSC start-up time 1.7 ms PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT fLFOSC LFOSC frequency 32768 Hz LFOSC accuracy -40 ℃ ≤ Ta ≤ 125 ℃ –5 5 % -40 ℃ ≤ Ta ≤ 85 ℃ –3 3 % tstart, LFOSC LFOSC start-up time 1.7 ms fLFOSC LFOSC frequency 32768 Hz fLFOSC LFOSCLFOSC frequency32768Hz LFOSC accuracy -40 ℃ ≤ Ta ≤ 125 ℃ –5 5 % LFOSC accuracy-40 ℃ ≤ Ta ≤ 125 ℃a–55% -40 ℃ ≤ Ta ≤ 85 ℃ –3 3 % -40 ℃ ≤ Ta ≤ 85 ℃a–33% tstart, LFOSC LFOSC start-up time 1.7 ms tstart, LFOSC start, LFOSCLFOSC start-up time1.7ms Digital IO Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH High level input voltage ODIO #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SF72TYWLT.00 VDD ≥ 1.62V 0.7×VDD 5.5 V VDD ≥ 2.7V 2 5.5 V All I/O except ODIO & Reset VDD ≥ 1.62V 0.7×VDD VDD+0.3 V VIL Low level input voltage ODIO VDD ≥ 1.62V -0.3 0.3×VDD V VDD ≥ 2.7V -0.3 0.8 V All I/O except ODIO & Reset VDD ≥ 1.62V -0.3 0.3×VDD V VHYS Hysteresis ODIO 0.05×VDD V All I/O except ODIO 0.1×VDD V Ilkg High-Z leakage current SDIO#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SFX6NSJXZJ1U #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SFDQQ0PR40NZ ±50#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SFNV3RMBMORA nA RPU Pull up resistance All I/O except ODIO 40 kΩ RPD Pull down resistance 40 kΩ CI Input capacitance 5 pF VOH High level output voltage SDIO VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤25 °C VDD-0.4 V VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C VDD-0.45 HSIO VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mA-40 °C ≤Tj≤25 °C VDD-0.4 VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mA-40 °C ≤Tj≤130 °C VDD-0.4 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, DRV = 0, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤25 °C VDD-0.45 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C VDD-0.45 VOL Low level output voltage SDIO VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤25 °C 0.4 V VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C 0.45 HSIO VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mATj≤85 °C 0.4 VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mA-40 °C ≤Tj≤130 °C 0.45 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, DRV = 0, \|IIO\|,max = 1.5mATj≤85 °C 0.4 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, DRV = 0, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C 0.45 ODIO VDD ≥ 2.7V, IOL,max = 8mAVDD ≥ 1.71V, IOL,max = 4mA-40 °C ≤Tj≤25 °C 0.4 VDD ≥ 2.7V, IOL,max = 8mAVDD ≥ 1.71V, IOL,max = 4mA-40 °C ≤Tj≤130 °C 0.45 I/O Types: ODIO = 5V Tolerant Open-Drain , SDIO = Standard-Drive , HSIO = High-Speed The leakage current is measured with VSS or VDD applied to the corresponding pins, unless otherwise noted. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled. This value is for SDIO not muxed with any analog inputs. If the SDIO is muxed with analog inputs then the leakage can be as high as 100nA. Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fmax Port output frequency SDIO #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376799/SFHPZH8IHV7S VDD ≥ 1.71V, CL= 20pF 16 MHz VDD ≥ 2.7V, CL = 20pF 32 HSIO VDD ≥ 1.71V, DRV = 0, CL = 20pF 16 VDD ≥ 1.71V, DRV = 1, CL = 20pF 24 VDD ≥ 2.7V, DRV = 0, CL = 20pF 32 ODIO VDD ≥ 1.71V, FM+, CL = 20pF - 100pF 1 tr,tf Output rise/fall time All output ports except ODIO VDD ≥ 1.71V 0.3×fmax s tf Output fall time ODIO VDD ≥ 1.71V, FM+, CL = 20pF to 100pF 20×VDD/5.5 120 ns I/O Types: ODIO = 5V Tolerant Open-Drain , SDIO = Standard-Drive , HSIO = High-Speed Digital IO Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH High level input voltage ODIO #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SF72TYWLT.00 VDD ≥ 1.62V 0.7×VDD 5.5 V VDD ≥ 2.7V 2 5.5 V All I/O except ODIO & Reset VDD ≥ 1.62V 0.7×VDD VDD+0.3 V VIL Low level input voltage ODIO VDD ≥ 1.62V -0.3 0.3×VDD V VDD ≥ 2.7V -0.3 0.8 V All I/O except ODIO & Reset VDD ≥ 1.62V -0.3 0.3×VDD V VHYS Hysteresis ODIO 0.05×VDD V All I/O except ODIO 0.1×VDD V Ilkg High-Z leakage current SDIO#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SFX6NSJXZJ1U #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SFDQQ0PR40NZ ±50#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SFNV3RMBMORA nA RPU Pull up resistance All I/O except ODIO 40 kΩ RPD Pull down resistance 40 kΩ CI Input capacitance 5 pF VOH High level output voltage SDIO VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤25 °C VDD-0.4 V VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C VDD-0.45 HSIO VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mA-40 °C ≤Tj≤25 °C VDD-0.4 VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mA-40 °C ≤Tj≤130 °C VDD-0.4 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, DRV = 0, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤25 °C VDD-0.45 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C VDD-0.45 VOL Low level output voltage SDIO VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤25 °C 0.4 V VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C 0.45 HSIO VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mATj≤85 °C 0.4 VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mA-40 °C ≤Tj≤130 °C 0.45 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, DRV = 0, \|IIO\|,max = 1.5mATj≤85 °C 0.4 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, DRV = 0, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C 0.45 ODIO VDD ≥ 2.7V, IOL,max = 8mAVDD ≥ 1.71V, IOL,max = 4mA-40 °C ≤Tj≤25 °C 0.4 VDD ≥ 2.7V, IOL,max = 8mAVDD ≥ 1.71V, IOL,max = 4mA-40 °C ≤Tj≤130 °C 0.45 I/O Types: ODIO = 5V Tolerant Open-Drain , SDIO = Standard-Drive , HSIO = High-Speed The leakage current is measured with VSS or VDD applied to the corresponding pins, unless otherwise noted. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled. This value is for SDIO not muxed with any analog inputs. If the SDIO is muxed with analog inputs then the leakage can be as high as 100nA. Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH High level input voltage ODIO #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SF72TYWLT.00 VDD ≥ 1.62V 0.7×VDD 5.5 V VDD ≥ 2.7V 2 5.5 V All I/O except ODIO & Reset VDD ≥ 1.62V 0.7×VDD VDD+0.3 V VIL Low level input voltage ODIO VDD ≥ 1.62V -0.3 0.3×VDD V VDD ≥ 2.7V -0.3 0.8 V All I/O except ODIO & Reset VDD ≥ 1.62V -0.3 0.3×VDD V VHYS Hysteresis ODIO 0.05×VDD V All I/O except ODIO 0.1×VDD V Ilkg High-Z leakage current SDIO#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SFX6NSJXZJ1U #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SFDQQ0PR40NZ ±50#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SFNV3RMBMORA nA RPU Pull up resistance All I/O except ODIO 40 kΩ RPD Pull down resistance 40 kΩ CI Input capacitance 5 pF VOH High level output voltage SDIO VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤25 °C VDD-0.4 V VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C VDD-0.45 HSIO VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mA-40 °C ≤Tj≤25 °C VDD-0.4 VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mA-40 °C ≤Tj≤130 °C VDD-0.4 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, DRV = 0, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤25 °C VDD-0.45 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C VDD-0.45 VOL Low level output voltage SDIO VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤25 °C 0.4 V VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C 0.45 HSIO VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mATj≤85 °C 0.4 VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mA-40 °C ≤Tj≤130 °C 0.45 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, DRV = 0, \|IIO\|,max = 1.5mATj≤85 °C 0.4 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, DRV = 0, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C 0.45 ODIO VDD ≥ 2.7V, IOL,max = 8mAVDD ≥ 1.71V, IOL,max = 4mA-40 °C ≤Tj≤25 °C 0.4 VDD ≥ 2.7V, IOL,max = 8mAVDD ≥ 1.71V, IOL,max = 4mA-40 °C ≤Tj≤130 °C 0.45 I/O Types: ODIO = 5V Tolerant Open-Drain , SDIO = Standard-Drive , HSIO = High-Speed The leakage current is measured with VSS or VDD applied to the corresponding pins, unless otherwise noted. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled. This value is for SDIO not muxed with any analog inputs. If the SDIO is muxed with analog inputs then the leakage can be as high as 100nA. over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH High level input voltage ODIO #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SF72TYWLT.00 VDD ≥ 1.62V 0.7×VDD 5.5 V VDD ≥ 2.7V 2 5.5 V All I/O except ODIO & Reset VDD ≥ 1.62V 0.7×VDD VDD+0.3 V VIL Low level input voltage ODIO VDD ≥ 1.62V -0.3 0.3×VDD V VDD ≥ 2.7V -0.3 0.8 V All I/O except ODIO & Reset VDD ≥ 1.62V -0.3 0.3×VDD V VHYS Hysteresis ODIO 0.05×VDD V All I/O except ODIO 0.1×VDD V Ilkg High-Z leakage current SDIO#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SFX6NSJXZJ1U #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SFDQQ0PR40NZ ±50#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SFNV3RMBMORA nA RPU Pull up resistance All I/O except ODIO 40 kΩ RPD Pull down resistance 40 kΩ CI Input capacitance 5 pF VOH High level output voltage SDIO VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤25 °C VDD-0.4 V VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C VDD-0.45 HSIO VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mA-40 °C ≤Tj≤25 °C VDD-0.4 VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mA-40 °C ≤Tj≤130 °C VDD-0.4 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, DRV = 0, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤25 °C VDD-0.45 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C VDD-0.45 VOL Low level output voltage SDIO VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤25 °C 0.4 V VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C 0.45 HSIO VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mATj≤85 °C 0.4 VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mA-40 °C ≤Tj≤130 °C 0.45 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, DRV = 0, \|IIO\|,max = 1.5mATj≤85 °C 0.4 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, DRV = 0, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C 0.45 ODIO VDD ≥ 2.7V, IOL,max = 8mAVDD ≥ 1.71V, IOL,max = 4mA-40 °C ≤Tj≤25 °C 0.4 VDD ≥ 2.7V, IOL,max = 8mAVDD ≥ 1.71V, IOL,max = 4mA-40 °C ≤Tj≤130 °C 0.45 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH High level input voltage ODIO #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SF72TYWLT.00 VDD ≥ 1.62V 0.7×VDD 5.5 V VDD ≥ 2.7V 2 5.5 V All I/O except ODIO & Reset VDD ≥ 1.62V 0.7×VDD VDD+0.3 V VIL Low level input voltage ODIO VDD ≥ 1.62V -0.3 0.3×VDD V VDD ≥ 2.7V -0.3 0.8 V All I/O except ODIO & Reset VDD ≥ 1.62V -0.3 0.3×VDD V VHYS Hysteresis ODIO 0.05×VDD V All I/O except ODIO 0.1×VDD V Ilkg High-Z leakage current SDIO#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SFX6NSJXZJ1U #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SFDQQ0PR40NZ ±50#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SFNV3RMBMORA nA RPU Pull up resistance All I/O except ODIO 40 kΩ RPD Pull down resistance 40 kΩ CI Input capacitance 5 pF VOH High level output voltage SDIO VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤25 °C VDD-0.4 V VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C VDD-0.45 HSIO VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mA-40 °C ≤Tj≤25 °C VDD-0.4 VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mA-40 °C ≤Tj≤130 °C VDD-0.4 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, DRV = 0, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤25 °C VDD-0.45 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C VDD-0.45 VOL Low level output voltage SDIO VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤25 °C 0.4 V VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C 0.45 HSIO VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mATj≤85 °C 0.4 VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mA-40 °C ≤Tj≤130 °C 0.45 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, DRV = 0, \|IIO\|,max = 1.5mATj≤85 °C 0.4 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, DRV = 0, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C 0.45 ODIO VDD ≥ 2.7V, IOL,max = 8mAVDD ≥ 1.71V, IOL,max = 4mA-40 °C ≤Tj≤25 °C 0.4 VDD ≥ 2.7V, IOL,max = 8mAVDD ≥ 1.71V, IOL,max = 4mA-40 °C ≤Tj≤130 °C 0.45 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT VIH High level input voltage ODIO #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SF72TYWLT.00 VDD ≥ 1.62V 0.7×VDD 5.5 V VDD ≥ 2.7V 2 5.5 V All I/O except ODIO & Reset VDD ≥ 1.62V 0.7×VDD VDD+0.3 V VIL Low level input voltage ODIO VDD ≥ 1.62V -0.3 0.3×VDD V VDD ≥ 2.7V -0.3 0.8 V All I/O except ODIO & Reset VDD ≥ 1.62V -0.3 0.3×VDD V VHYS Hysteresis ODIO 0.05×VDD V All I/O except ODIO 0.1×VDD V Ilkg High-Z leakage current SDIO#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SFX6NSJXZJ1U #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SFDQQ0PR40NZ ±50#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SFNV3RMBMORA nA RPU Pull up resistance All I/O except ODIO 40 kΩ RPD Pull down resistance 40 kΩ CI Input capacitance 5 pF VOH High level output voltage SDIO VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤25 °C VDD-0.4 V VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C VDD-0.45 HSIO VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mA-40 °C ≤Tj≤25 °C VDD-0.4 VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mA-40 °C ≤Tj≤130 °C VDD-0.4 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, DRV = 0, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤25 °C VDD-0.45 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C VDD-0.45 VOL Low level output voltage SDIO VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤25 °C 0.4 V VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C 0.45 HSIO VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mATj≤85 °C 0.4 VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mA-40 °C ≤Tj≤130 °C 0.45 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, DRV = 0, \|IIO\|,max = 1.5mATj≤85 °C 0.4 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, DRV = 0, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C 0.45 ODIO VDD ≥ 2.7V, IOL,max = 8mAVDD ≥ 1.71V, IOL,max = 4mA-40 °C ≤Tj≤25 °C 0.4 VDD ≥ 2.7V, IOL,max = 8mAVDD ≥ 1.71V, IOL,max = 4mA-40 °C ≤Tj≤130 °C 0.45 VIH High level input voltage ODIO #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SF72TYWLT.00 VDD ≥ 1.62V 0.7×VDD 5.5 V VIH IHHigh level input voltageODIO #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SF72TYWLT.00 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SF72TYWLT.00VDD ≥ 1.62VDD0.7×VDD DD5.5V VDD ≥ 2.7V 2 5.5 V VDD ≥ 2.7VDD25.5V All I/O except ODIO & Reset VDD ≥ 1.62V 0.7×VDD VDD+0.3 V All I/O except ODIO & ResetVDD ≥ 1.62VDD0.7×VDD DDVDD+0.3DDV VIL Low level input voltage ODIO VDD ≥ 1.62V -0.3 0.3×VDD V VIL ILLow level input voltageODIOVDD ≥ 1.62VDD-0.30.3×VDD DDV VDD ≥ 2.7V -0.3 0.8 V VDD ≥ 2.7VDD-0.30.8V All I/O except ODIO & Reset VDD ≥ 1.62V -0.3 0.3×VDD V All I/O except ODIO & ResetVDD ≥ 1.62VDD-0.30.3×VDD DDV VHYS Hysteresis ODIO 0.05×VDD V VHYS HYSHysteresisODIO0.05×VDD DDV All I/O except ODIO 0.1×VDD V All I/O except ODIO0.1×VDD DDV Ilkg High-Z leakage current SDIO#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SFX6NSJXZJ1U #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SFDQQ0PR40NZ ±50#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SFNV3RMBMORA nA Ilkg lkgHigh-Z leakage currentSDIO#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SFX6NSJXZJ1U #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SFDQQ0PR40NZ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SFX6NSJXZJ1U#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SFDQQ0PR40NZ±50#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SFNV3RMBMORA #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376798/SFNV3RMBMORAnA RPU Pull up resistance All I/O except ODIO 40 kΩ RPU PUPull up resistanceAll I/O except ODIO40kΩ RPD Pull down resistance 40 kΩ RPD PDPull down resistance40kΩ CI Input capacitance 5 pF CI IInput capacitance5pF VOH High level output voltage SDIO VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤25 °C VDD-0.4 V VOH OHHigh level output voltageSDIOVDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤25 °CDDIO,maxDDIO,maxDDIO,maxjVDD-0.4DDV VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C VDD-0.45 VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °CDDIO,maxDDIO,maxDDIO,maxjVDD-0.45DD HSIO VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mA-40 °C ≤Tj≤25 °C VDD-0.4 HSIOVDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mA-40 °C ≤Tj≤25 °CDDIO,maxDDIO,maxDDIO,maxjVDD-0.4DD VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mA-40 °C ≤Tj≤130 °C VDD-0.4 VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mA-40 °C ≤Tj≤130 °CDDIO,maxDDIO,maxDDIO,maxjVDD-0.4DD VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, DRV = 0, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤25 °C VDD-0.45 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, DRV = 0, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤25 °CDDIO,maxDDIO,maxDDIO,maxjVDD-0.45DD VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C VDD-0.45 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °CDDIO,maxDDIO,maxDDIO,maxjVDD-0.45DD VOL Low level output voltage SDIO VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤25 °C 0.4 V VOL OLLow level output voltageSDIOVDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤25 °CDDIO,maxDDIO,maxDDIO,maxj0.4V VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C 0.45 VDD ≥ 2.7V, \|IIO\|,max = 6mAVDD ≥ 1.71V, \|IIO\|,max = 2mAVDD ≥ 1.62V, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °CDDIO,maxDDIO,maxDDIO,maxj0.45 HSIO VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mATj≤85 °C 0.4 HSIOVDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mATj≤85 °CDDIO,maxDDIO,maxDDIO,maxj0.4 VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mA-40 °C ≤Tj≤130 °C 0.45 VDD ≥ 2.7V, DRV = 1, \|IIO\|,max = 6mAVDD ≥ 1.71V, DRV = 1, \|IIO\|,max = 3mAVDD ≥ 1.62V, DRV = 1, \|IIO\|,max = 2mA-40 °C ≤Tj≤130 °CDDIO,maxDDIO,maxDDIO,maxj0.45 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, DRV = 0, \|IIO\|,max = 1.5mATj≤85 °C 0.4 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, DRV = 0, \|IIO\|,max = 1.5mATj≤85 °CDDIO,maxDDIO,maxDDIO,maxj0.4 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, DRV = 0, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °C 0.45 VDD ≥ 2.7V, DRV = 0, \|IIO\|,max = 4mAVDD ≥ 1.71V, DRV = 0, \|IIO\|,max = 2mAVDD ≥ 1.62V, DRV = 0, \|IIO\|,max = 1.5mA-40 °C ≤Tj≤130 °CDDIO,maxDDIO,maxDDIO,maxj0.45 ODIO VDD ≥ 2.7V, IOL,max = 8mAVDD ≥ 1.71V, IOL,max = 4mA-40 °C ≤Tj≤25 °C 0.4 ODIO VDD ≥ 2.7V, IOL,max = 8mAVDD ≥ 1.71V, IOL,max = 4mA-40 °C ≤Tj≤25 °CDDOL,maxDDOL,maxj0.4 VDD ≥ 2.7V, IOL,max = 8mAVDD ≥ 1.71V, IOL,max = 4mA-40 °C ≤Tj≤130 °C 0.45 VDD ≥ 2.7V, IOL,max = 8mAVDD ≥ 1.71V, IOL,max = 4mA-40 °C ≤Tj≤130 °CDDOL,maxDDOL,maxj0.45 I/O Types: ODIO = 5V Tolerant Open-Drain , SDIO = Standard-Drive , HSIO = High-Speed The leakage current is measured with VSS or VDD applied to the corresponding pins, unless otherwise noted. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled. This value is for SDIO not muxed with any analog inputs. If the SDIO is muxed with analog inputs then the leakage can be as high as 100nA. I/O Types: ODIO = 5V Tolerant Open-Drain , SDIO = Standard-Drive , HSIO = High-SpeedThe leakage current is measured with VSS or VDD applied to the corresponding pins, unless otherwise noted.DDThe leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled.This value is for SDIO not muxed with any analog inputs. If the SDIO is muxed with analog inputs then the leakage can be as high as 100nA. Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fmax Port output frequency SDIO #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376799/SFHPZH8IHV7S VDD ≥ 1.71V, CL= 20pF 16 MHz VDD ≥ 2.7V, CL = 20pF 32 HSIO VDD ≥ 1.71V, DRV = 0, CL = 20pF 16 VDD ≥ 1.71V, DRV = 1, CL = 20pF 24 VDD ≥ 2.7V, DRV = 0, CL = 20pF 32 ODIO VDD ≥ 1.71V, FM+, CL = 20pF - 100pF 1 tr,tf Output rise/fall time All output ports except ODIO VDD ≥ 1.71V 0.3×fmax s tf Output fall time ODIO VDD ≥ 1.71V, FM+, CL = 20pF to 100pF 20×VDD/5.5 120 ns I/O Types: ODIO = 5V Tolerant Open-Drain , SDIO = Standard-Drive , HSIO = High-Speed Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fmax Port output frequency SDIO #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376799/SFHPZH8IHV7S VDD ≥ 1.71V, CL= 20pF 16 MHz VDD ≥ 2.7V, CL = 20pF 32 HSIO VDD ≥ 1.71V, DRV = 0, CL = 20pF 16 VDD ≥ 1.71V, DRV = 1, CL = 20pF 24 VDD ≥ 2.7V, DRV = 0, CL = 20pF 32 ODIO VDD ≥ 1.71V, FM+, CL = 20pF - 100pF 1 tr,tf Output rise/fall time All output ports except ODIO VDD ≥ 1.71V 0.3×fmax s tf Output fall time ODIO VDD ≥ 1.71V, FM+, CL = 20pF to 100pF 20×VDD/5.5 120 ns I/O Types: ODIO = 5V Tolerant Open-Drain , SDIO = Standard-Drive , HSIO = High-Speed over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fmax Port output frequency SDIO #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376799/SFHPZH8IHV7S VDD ≥ 1.71V, CL= 20pF 16 MHz VDD ≥ 2.7V, CL = 20pF 32 HSIO VDD ≥ 1.71V, DRV = 0, CL = 20pF 16 VDD ≥ 1.71V, DRV = 1, CL = 20pF 24 VDD ≥ 2.7V, DRV = 0, CL = 20pF 32 ODIO VDD ≥ 1.71V, FM+, CL = 20pF - 100pF 1 tr,tf Output rise/fall time All output ports except ODIO VDD ≥ 1.71V 0.3×fmax s tf Output fall time ODIO VDD ≥ 1.71V, FM+, CL = 20pF to 100pF 20×VDD/5.5 120 ns over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fmax Port output frequency SDIO #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376799/SFHPZH8IHV7S VDD ≥ 1.71V, CL= 20pF 16 MHz VDD ≥ 2.7V, CL = 20pF 32 HSIO VDD ≥ 1.71V, DRV = 0, CL = 20pF 16 VDD ≥ 1.71V, DRV = 1, CL = 20pF 24 VDD ≥ 2.7V, DRV = 0, CL = 20pF 32 ODIO VDD ≥ 1.71V, FM+, CL = 20pF - 100pF 1 tr,tf Output rise/fall time All output ports except ODIO VDD ≥ 1.71V 0.3×fmax s tf Output fall time ODIO VDD ≥ 1.71V, FM+, CL = 20pF to 100pF 20×VDD/5.5 120 ns PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT fmax Port output frequency SDIO #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376799/SFHPZH8IHV7S VDD ≥ 1.71V, CL= 20pF 16 MHz VDD ≥ 2.7V, CL = 20pF 32 HSIO VDD ≥ 1.71V, DRV = 0, CL = 20pF 16 VDD ≥ 1.71V, DRV = 1, CL = 20pF 24 VDD ≥ 2.7V, DRV = 0, CL = 20pF 32 ODIO VDD ≥ 1.71V, FM+, CL = 20pF - 100pF 1 tr,tf Output rise/fall time All output ports except ODIO VDD ≥ 1.71V 0.3×fmax s tf Output fall time ODIO VDD ≥ 1.71V, FM+, CL = 20pF to 100pF 20×VDD/5.5 120 ns fmax Port output frequency SDIO #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376799/SFHPZH8IHV7S VDD ≥ 1.71V, CL= 20pF 16 MHz fmax maxPort output frequencySDIO #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376799/SFHPZH8IHV7S #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376799/SFHPZH8IHV7SVDD ≥ 1.71V, CL= 20pFDDL16MHz VDD ≥ 2.7V, CL = 20pF 32 VDD ≥ 2.7V, CL = 20pFDDL32 HSIO VDD ≥ 1.71V, DRV = 0, CL = 20pF 16 HSIOVDD ≥ 1.71V, DRV = 0, CL = 20pFDDL16 VDD ≥ 1.71V, DRV = 1, CL = 20pF 24 VDD ≥ 1.71V, DRV = 1, CL = 20pFDDL24 VDD ≥ 2.7V, DRV = 0, CL = 20pF 32 VDD ≥ 2.7V, DRV = 0, CL = 20pFDDL32 ODIO VDD ≥ 1.71V, FM+, CL = 20pF - 100pF 1 ODIOVDD ≥ 1.71V, FM+, CL = 20pF - 100pFDD+L1 tr,tf Output rise/fall time All output ports except ODIO VDD ≥ 1.71V 0.3×fmax s tr,tf rfOutput rise/fall timeAll output ports except ODIOVDD ≥ 1.71VDD0.3×fmax maxs tf Output fall time ODIO VDD ≥ 1.71V, FM+, CL = 20pF to 100pF 20×VDD/5.5 120 ns tf fOutput fall timeODIOVDD ≥ 1.71V, FM+, CL = 20pF to 100pFDD+L20×VDD/5.5DD120ns I/O Types: ODIO = 5V Tolerant Open-Drain , SDIO = Standard-Drive , HSIO = High-Speed I/O Types: ODIO = 5V Tolerant Open-Drain , SDIO = Standard-Drive , HSIO = High-Speed Analog Mux VBOOST over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IVBST VBOOST current adder MCLK/ULPCLK is LFCLK 0.8 uA MCLK/ULPCLK is not LFCLK, SYSOSC frequency is 4MHz 8.5 tSTART,VBST VBOOST startup time 12 us Analog Mux VBOOST over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IVBST VBOOST current adder MCLK/ULPCLK is LFCLK 0.8 uA MCLK/ULPCLK is not LFCLK, SYSOSC frequency is 4MHz 8.5 tSTART,VBST VBOOST startup time 12 us over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IVBST VBOOST current adder MCLK/ULPCLK is LFCLK 0.8 uA MCLK/ULPCLK is not LFCLK, SYSOSC frequency is 4MHz 8.5 tSTART,VBST VBOOST startup time 12 us over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IVBST VBOOST current adder MCLK/ULPCLK is LFCLK 0.8 uA MCLK/ULPCLK is not LFCLK, SYSOSC frequency is 4MHz 8.5 tSTART,VBST VBOOST startup time 12 us PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT IVBST VBOOST current adder MCLK/ULPCLK is LFCLK 0.8 uA MCLK/ULPCLK is not LFCLK, SYSOSC frequency is 4MHz 8.5 tSTART,VBST VBOOST startup time 12 us IVBST VBOOST current adder MCLK/ULPCLK is LFCLK 0.8 uA IVBST VBSTVBOOST current adderMCLK/ULPCLK is LFCLK0.8uA MCLK/ULPCLK is not LFCLK, SYSOSC frequency is 4MHz 8.5 MCLK/ULPCLK is not LFCLK, SYSOSC frequency is 4MHz8.5 tSTART,VBST VBOOST startup time 12 us tSTART,VBST START,VBSTVBOOST startup time12us ADC Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted), all TYP values are measured at 25℃ and all accuracy parameters are measured using 12-bit resolution mode (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vin(ADC) Analog input voltage range#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SF.FIOPY1XB3_SF2 Applies to all ADC analog input pins 0 VDD V VR+ Positive ADC reference voltage VR+ sourced from VDD VDD V VR+ sourced from external reference pin (VREF+) 1.4 VDD V VR+ sourced from internal reference (VREF) VREF V VR- Negative ADC reference voltage 0 V FS ADC sampling frequency RES = 0x0 (12-bit mode), External Reference 1.68 Msps I(ADC) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/TG47888388372_SF2 Operating supply currentinto VDD terminal FS = 1MSPS, Internal reference OFF, VR+ = VDD 454 600 μA FS = 200ksps, Internal reference ON, VR+ = VREF = 2.5V 300 435 CS/H ADC sample-and-hold capacitance 3.3 7 pF Rin ADC sampling switch resistance 0.5 1 kΩ ENOB Effective number of bits Internal reference, VR+ = VREF = 2.5V, Fin = 10KHz 10 10.2 bit External reference, Fin = 10KHz #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2 11 11.1 SNR Signal-to-noise ratio External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2 68 71 dB Internal reference, VR+ = VREF = 2.5V 63 65 PSRRDC Power supply rejection ratio, DC External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2, VDD = VDD(min) to VDD(max) 63 68 dB VDD = VDD(min) to VDD(max) Internal reference, VR+ = VREF = 2.5V 49 55 PSRRAC Power supply rejection ratio, AC External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2, ΔVDD = 0.1 V at 1 kHz 61 dB ΔVDD = 0.1 V at 1 kHzInternal reference, VR+ = VREF = 2.5V 49 Twakeup ADC Wakeup Time Assumes internal reference is active 1 us VSupplyMon Supply Monitor voltage divider (VDD/3) accuracy ADC input channel: Supply Monitor #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SF34MRTUPYCS_SF2 -1.5 +1.5 % ISupplyMon Supply Monitor voltage divider current consumption ADC input channel: Supply Monitor 10 uA The analog input voltage range must be within the selected ADC reference voltage range VR+ to VR– for valid conversion results. The internal reference (VREF) supply current is not included in current consumption parameter I(ADC). All external reference specifications are measured with VR+ = VREF+ = VDD = 3.3V and VR- = VREF- = VSS = 0V and external 1uF cap on VREF+ pin Analog power supply monitor. Analog input on channel 15 is disconnected and is internally connected to the voltage divider which is VDD/3. Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fADCCLK ADC clock frequency 4 32 MHz tADC trigger Software trigger minimum width 3 ADCCLK cycles tSample Sampling time without OPA 12-bit mode, RS = 50Ω, Cpext = 10pF 156 ns tSample_PGA Sampling time with OPA #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376828/SFDY6E128LC3_SF1 12-bit mode GBW = 0x1, PGA gain = x1 0.31 µs GBW = 0x1, PGA gain = x32 1.5 µs tSample_GPAMP Sampling time with GPAMP 12-bit mode 2.5 µs tSample_SupplyMon Sample time with Supply Monitor (VDD/3) 12-bit mode 3 µs Only applies for devices with OPA Linearity Parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted), all TYP values are measured at 25℃ and all linearity parameters are measured using 12-bit resolution mode (unless otherwise noted) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFQ2EE8MT8H7_SF2 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EI Integral linearity error (INL) External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -2.0 +2.0 LSB ED Differential linearity error (DNL)Guaranteed no missing codes External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -1.0 +1.0 LSB EO Offset error External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -3 3 mV Internal reference, VR+ = VREF = 2.5V -3 3 mV EG Gain error External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -3 3 LSB Total Unadjusted Error (TUE) can be calculated from EI , EO , and EG using the following formula: TUE = √( EI 2 + \|EO\|2 + EG 2 )Note: You must convert all of the errors into the same unit, usually LSB, for the above equation to be accurate All external reference specifications are measured with VR+ = VREF+ = VDD = 3.3V and VR- = VREF- = VSS = 0V and external 1uF cap on VREF+ pin Typical Connection Diagram ADC Input Network Refer to ADC Electrical Characteristics for the values of Rin and CS/H Refer to Digital IO Electrical Characteristics for the value of CI Cpar and Rpar represent the parasitic capacitance and resistance of the external ADC input circuitry Use the following equations to solve for the minimum sampling time (T) required for an ADC conversion: Tau = (Rpar + Rin) × CS/H + Rpar × (Cpar + CI) K= ln(2n/Settling error) – ln((Cpar + CI)/CS/H) T (Min sampling time) = K × Tau ADC Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted), all TYP values are measured at 25℃ and all accuracy parameters are measured using 12-bit resolution mode (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vin(ADC) Analog input voltage range#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SF.FIOPY1XB3_SF2 Applies to all ADC analog input pins 0 VDD V VR+ Positive ADC reference voltage VR+ sourced from VDD VDD V VR+ sourced from external reference pin (VREF+) 1.4 VDD V VR+ sourced from internal reference (VREF) VREF V VR- Negative ADC reference voltage 0 V FS ADC sampling frequency RES = 0x0 (12-bit mode), External Reference 1.68 Msps I(ADC) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/TG47888388372_SF2 Operating supply currentinto VDD terminal FS = 1MSPS, Internal reference OFF, VR+ = VDD 454 600 μA FS = 200ksps, Internal reference ON, VR+ = VREF = 2.5V 300 435 CS/H ADC sample-and-hold capacitance 3.3 7 pF Rin ADC sampling switch resistance 0.5 1 kΩ ENOB Effective number of bits Internal reference, VR+ = VREF = 2.5V, Fin = 10KHz 10 10.2 bit External reference, Fin = 10KHz #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2 11 11.1 SNR Signal-to-noise ratio External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2 68 71 dB Internal reference, VR+ = VREF = 2.5V 63 65 PSRRDC Power supply rejection ratio, DC External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2, VDD = VDD(min) to VDD(max) 63 68 dB VDD = VDD(min) to VDD(max) Internal reference, VR+ = VREF = 2.5V 49 55 PSRRAC Power supply rejection ratio, AC External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2, ΔVDD = 0.1 V at 1 kHz 61 dB ΔVDD = 0.1 V at 1 kHzInternal reference, VR+ = VREF = 2.5V 49 Twakeup ADC Wakeup Time Assumes internal reference is active 1 us VSupplyMon Supply Monitor voltage divider (VDD/3) accuracy ADC input channel: Supply Monitor #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SF34MRTUPYCS_SF2 -1.5 +1.5 % ISupplyMon Supply Monitor voltage divider current consumption ADC input channel: Supply Monitor 10 uA The analog input voltage range must be within the selected ADC reference voltage range VR+ to VR– for valid conversion results. The internal reference (VREF) supply current is not included in current consumption parameter I(ADC). All external reference specifications are measured with VR+ = VREF+ = VDD = 3.3V and VR- = VREF- = VSS = 0V and external 1uF cap on VREF+ pin Analog power supply monitor. Analog input on channel 15 is disconnected and is internally connected to the voltage divider which is VDD/3. Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted), all TYP values are measured at 25℃ and all accuracy parameters are measured using 12-bit resolution mode (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vin(ADC) Analog input voltage range#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SF.FIOPY1XB3_SF2 Applies to all ADC analog input pins 0 VDD V VR+ Positive ADC reference voltage VR+ sourced from VDD VDD V VR+ sourced from external reference pin (VREF+) 1.4 VDD V VR+ sourced from internal reference (VREF) VREF V VR- Negative ADC reference voltage 0 V FS ADC sampling frequency RES = 0x0 (12-bit mode), External Reference 1.68 Msps I(ADC) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/TG47888388372_SF2 Operating supply currentinto VDD terminal FS = 1MSPS, Internal reference OFF, VR+ = VDD 454 600 μA FS = 200ksps, Internal reference ON, VR+ = VREF = 2.5V 300 435 CS/H ADC sample-and-hold capacitance 3.3 7 pF Rin ADC sampling switch resistance 0.5 1 kΩ ENOB Effective number of bits Internal reference, VR+ = VREF = 2.5V, Fin = 10KHz 10 10.2 bit External reference, Fin = 10KHz #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2 11 11.1 SNR Signal-to-noise ratio External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2 68 71 dB Internal reference, VR+ = VREF = 2.5V 63 65 PSRRDC Power supply rejection ratio, DC External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2, VDD = VDD(min) to VDD(max) 63 68 dB VDD = VDD(min) to VDD(max) Internal reference, VR+ = VREF = 2.5V 49 55 PSRRAC Power supply rejection ratio, AC External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2, ΔVDD = 0.1 V at 1 kHz 61 dB ΔVDD = 0.1 V at 1 kHzInternal reference, VR+ = VREF = 2.5V 49 Twakeup ADC Wakeup Time Assumes internal reference is active 1 us VSupplyMon Supply Monitor voltage divider (VDD/3) accuracy ADC input channel: Supply Monitor #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SF34MRTUPYCS_SF2 -1.5 +1.5 % ISupplyMon Supply Monitor voltage divider current consumption ADC input channel: Supply Monitor 10 uA The analog input voltage range must be within the selected ADC reference voltage range VR+ to VR– for valid conversion results. The internal reference (VREF) supply current is not included in current consumption parameter I(ADC). All external reference specifications are measured with VR+ = VREF+ = VDD = 3.3V and VR- = VREF- = VSS = 0V and external 1uF cap on VREF+ pin Analog power supply monitor. Analog input on channel 15 is disconnected and is internally connected to the voltage divider which is VDD/3. over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted), all TYP values are measured at 25℃ and all accuracy parameters are measured using 12-bit resolution mode (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vin(ADC) Analog input voltage range#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SF.FIOPY1XB3_SF2 Applies to all ADC analog input pins 0 VDD V VR+ Positive ADC reference voltage VR+ sourced from VDD VDD V VR+ sourced from external reference pin (VREF+) 1.4 VDD V VR+ sourced from internal reference (VREF) VREF V VR- Negative ADC reference voltage 0 V FS ADC sampling frequency RES = 0x0 (12-bit mode), External Reference 1.68 Msps I(ADC) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/TG47888388372_SF2 Operating supply currentinto VDD terminal FS = 1MSPS, Internal reference OFF, VR+ = VDD 454 600 μA FS = 200ksps, Internal reference ON, VR+ = VREF = 2.5V 300 435 CS/H ADC sample-and-hold capacitance 3.3 7 pF Rin ADC sampling switch resistance 0.5 1 kΩ ENOB Effective number of bits Internal reference, VR+ = VREF = 2.5V, Fin = 10KHz 10 10.2 bit External reference, Fin = 10KHz #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2 11 11.1 SNR Signal-to-noise ratio External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2 68 71 dB Internal reference, VR+ = VREF = 2.5V 63 65 PSRRDC Power supply rejection ratio, DC External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2, VDD = VDD(min) to VDD(max) 63 68 dB VDD = VDD(min) to VDD(max) Internal reference, VR+ = VREF = 2.5V 49 55 PSRRAC Power supply rejection ratio, AC External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2, ΔVDD = 0.1 V at 1 kHz 61 dB ΔVDD = 0.1 V at 1 kHzInternal reference, VR+ = VREF = 2.5V 49 Twakeup ADC Wakeup Time Assumes internal reference is active 1 us VSupplyMon Supply Monitor voltage divider (VDD/3) accuracy ADC input channel: Supply Monitor #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SF34MRTUPYCS_SF2 -1.5 +1.5 % ISupplyMon Supply Monitor voltage divider current consumption ADC input channel: Supply Monitor 10 uA over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted), all TYP values are measured at 25℃ and all accuracy parameters are measured using 12-bit resolution mode (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vin(ADC) Analog input voltage range#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SF.FIOPY1XB3_SF2 Applies to all ADC analog input pins 0 VDD V VR+ Positive ADC reference voltage VR+ sourced from VDD VDD V VR+ sourced from external reference pin (VREF+) 1.4 VDD V VR+ sourced from internal reference (VREF) VREF V VR- Negative ADC reference voltage 0 V FS ADC sampling frequency RES = 0x0 (12-bit mode), External Reference 1.68 Msps I(ADC) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/TG47888388372_SF2 Operating supply currentinto VDD terminal FS = 1MSPS, Internal reference OFF, VR+ = VDD 454 600 μA FS = 200ksps, Internal reference ON, VR+ = VREF = 2.5V 300 435 CS/H ADC sample-and-hold capacitance 3.3 7 pF Rin ADC sampling switch resistance 0.5 1 kΩ ENOB Effective number of bits Internal reference, VR+ = VREF = 2.5V, Fin = 10KHz 10 10.2 bit External reference, Fin = 10KHz #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2 11 11.1 SNR Signal-to-noise ratio External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2 68 71 dB Internal reference, VR+ = VREF = 2.5V 63 65 PSRRDC Power supply rejection ratio, DC External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2, VDD = VDD(min) to VDD(max) 63 68 dB VDD = VDD(min) to VDD(max) Internal reference, VR+ = VREF = 2.5V 49 55 PSRRAC Power supply rejection ratio, AC External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2, ΔVDD = 0.1 V at 1 kHz 61 dB ΔVDD = 0.1 V at 1 kHzInternal reference, VR+ = VREF = 2.5V 49 Twakeup ADC Wakeup Time Assumes internal reference is active 1 us VSupplyMon Supply Monitor voltage divider (VDD/3) accuracy ADC input channel: Supply Monitor #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SF34MRTUPYCS_SF2 -1.5 +1.5 % ISupplyMon Supply Monitor voltage divider current consumption ADC input channel: Supply Monitor 10 uA PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT Vin(ADC) Analog input voltage range#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SF.FIOPY1XB3_SF2 Applies to all ADC analog input pins 0 VDD V VR+ Positive ADC reference voltage VR+ sourced from VDD VDD V VR+ sourced from external reference pin (VREF+) 1.4 VDD V VR+ sourced from internal reference (VREF) VREF V VR- Negative ADC reference voltage 0 V FS ADC sampling frequency RES = 0x0 (12-bit mode), External Reference 1.68 Msps I(ADC) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/TG47888388372_SF2 Operating supply currentinto VDD terminal FS = 1MSPS, Internal reference OFF, VR+ = VDD 454 600 μA FS = 200ksps, Internal reference ON, VR+ = VREF = 2.5V 300 435 CS/H ADC sample-and-hold capacitance 3.3 7 pF Rin ADC sampling switch resistance 0.5 1 kΩ ENOB Effective number of bits Internal reference, VR+ = VREF = 2.5V, Fin = 10KHz 10 10.2 bit External reference, Fin = 10KHz #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2 11 11.1 SNR Signal-to-noise ratio External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2 68 71 dB Internal reference, VR+ = VREF = 2.5V 63 65 PSRRDC Power supply rejection ratio, DC External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2, VDD = VDD(min) to VDD(max) 63 68 dB VDD = VDD(min) to VDD(max) Internal reference, VR+ = VREF = 2.5V 49 55 PSRRAC Power supply rejection ratio, AC External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2, ΔVDD = 0.1 V at 1 kHz 61 dB ΔVDD = 0.1 V at 1 kHzInternal reference, VR+ = VREF = 2.5V 49 Twakeup ADC Wakeup Time Assumes internal reference is active 1 us VSupplyMon Supply Monitor voltage divider (VDD/3) accuracy ADC input channel: Supply Monitor #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SF34MRTUPYCS_SF2 -1.5 +1.5 % ISupplyMon Supply Monitor voltage divider current consumption ADC input channel: Supply Monitor 10 uA Vin(ADC) Analog input voltage range#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SF.FIOPY1XB3_SF2 Applies to all ADC analog input pins 0 VDD V Vin(ADC) (ADC) Analog input voltage range#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SF.FIOPY1XB3_SF2 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SF.FIOPY1XB3_SF2Applies to all ADC analog input pins0VDDV VR+ Positive ADC reference voltage VR+ sourced from VDD VDD V VR+ R+Positive ADC reference voltageVR+ sourced from VDDR+VDDV VR+ sourced from external reference pin (VREF+) 1.4 VDD V VR+ sourced from external reference pin (VREF+)R+1.4VDDV VR+ sourced from internal reference (VREF) VREF V VR+ sourced from internal reference (VREF)R+VREFV VR- Negative ADC reference voltage 0 V VR- R-Negative ADC reference voltage0V FS ADC sampling frequency RES = 0x0 (12-bit mode), External Reference 1.68 Msps FS SADC sampling frequencyRES = 0x0 (12-bit mode), External Reference1.68Msps I(ADC) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/TG47888388372_SF2 Operating supply currentinto VDD terminal FS = 1MSPS, Internal reference OFF, VR+ = VDD 454 600 μA I(ADC) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/TG47888388372_SF2 (ADC)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/TG47888388372_SF2Operating supply currentinto VDD terminalFS = 1MSPS, Internal reference OFF, VR+ = VDDSR+454600μA FS = 200ksps, Internal reference ON, VR+ = VREF = 2.5V 300 435 FS = 200ksps, Internal reference ON, VR+ = VREF = 2.5VSR+ 300435 CS/H ADC sample-and-hold capacitance 3.3 7 pF CS/H S/HADC sample-and-hold capacitance3.37pF Rin ADC sampling switch resistance 0.5 1 kΩ RinADC sampling switch resistance0.51kΩ ENOB Effective number of bits Internal reference, VR+ = VREF = 2.5V, Fin = 10KHz 10 10.2 bit ENOBEffective number of bitsInternal reference, VR+ = VREF = 2.5V, Fin = 10KHzR+ in1010.2bit External reference, Fin = 10KHz #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2 11 11.1 External reference, Fin = 10KHz #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2 in#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF21111.1 SNR Signal-to-noise ratio External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2 68 71 dB SNRSignal-to-noise ratioExternal reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF26871dB Internal reference, VR+ = VREF = 2.5V 63 65 Internal reference, VR+ = VREF = 2.5VR+ 6365 PSRRDC Power supply rejection ratio, DC External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2, VDD = VDD(min) to VDD(max) 63 68 dB PSRRDC DCPower supply rejection ratio, DCExternal reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2, VDD = VDD(min) to VDD(max) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2(min)(max)6368dB VDD = VDD(min) to VDD(max) Internal reference, VR+ = VREF = 2.5V 49 55 VDD = VDD(min) to VDD(max) Internal reference, VR+ = VREF = 2.5V(min)(max)R+ 4955 PSRRAC Power supply rejection ratio, AC External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2, ΔVDD = 0.1 V at 1 kHz 61 dB PSRRAC ACPower supply rejection ratio, ACExternal reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF2, ΔVDD = 0.1 V at 1 kHz#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SFYFL_1WVL2O_SF261dB ΔVDD = 0.1 V at 1 kHzInternal reference, VR+ = VREF = 2.5V 49 ΔVDD = 0.1 V at 1 kHzInternal reference, VR+ = VREF = 2.5VR+ 49 Twakeup ADC Wakeup Time Assumes internal reference is active 1 us Twakeup wakeupADC Wakeup TimeAssumes internal reference is active1us VSupplyMon Supply Monitor voltage divider (VDD/3) accuracy ADC input channel: Supply Monitor #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SF34MRTUPYCS_SF2 -1.5 +1.5 % VSupplyMon SupplyMonSupply Monitor voltage divider (VDD/3) accuracyADC input channel: Supply Monitor #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SF34MRTUPYCS_SF2 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SF34MRTUPYCS_SF2 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376827/SF34MRTUPYCS_SF2-1.5+1.5% ISupplyMon Supply Monitor voltage divider current consumption ADC input channel: Supply Monitor 10 uA ISupplyMon SupplyMonSupply Monitor voltage divider current consumptionADC input channel: Supply Monitor10uA The analog input voltage range must be within the selected ADC reference voltage range VR+ to VR– for valid conversion results. The internal reference (VREF) supply current is not included in current consumption parameter I(ADC). All external reference specifications are measured with VR+ = VREF+ = VDD = 3.3V and VR- = VREF- = VSS = 0V and external 1uF cap on VREF+ pin Analog power supply monitor. Analog input on channel 15 is disconnected and is internally connected to the voltage divider which is VDD/3. The analog input voltage range must be within the selected ADC reference voltage range VR+ to VR– for valid conversion results.R+R–The internal reference (VREF) supply current is not included in current consumption parameter I(ADC).(ADC)All external reference specifications are measured with VR+ = VREF+ = VDD = 3.3V and VR- = VREF- = VSS = 0V and external 1uF cap on VREF+ pinR+R-Analog power supply monitor. Analog input on channel 15 is disconnected and is internally connected to the voltage divider which is VDD/3. Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fADCCLK ADC clock frequency 4 32 MHz tADC trigger Software trigger minimum width 3 ADCCLK cycles tSample Sampling time without OPA 12-bit mode, RS = 50Ω, Cpext = 10pF 156 ns tSample_PGA Sampling time with OPA #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376828/SFDY6E128LC3_SF1 12-bit mode GBW = 0x1, PGA gain = x1 0.31 µs GBW = 0x1, PGA gain = x32 1.5 µs tSample_GPAMP Sampling time with GPAMP 12-bit mode 2.5 µs tSample_SupplyMon Sample time with Supply Monitor (VDD/3) 12-bit mode 3 µs Only applies for devices with OPA Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fADCCLK ADC clock frequency 4 32 MHz tADC trigger Software trigger minimum width 3 ADCCLK cycles tSample Sampling time without OPA 12-bit mode, RS = 50Ω, Cpext = 10pF 156 ns tSample_PGA Sampling time with OPA #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376828/SFDY6E128LC3_SF1 12-bit mode GBW = 0x1, PGA gain = x1 0.31 µs GBW = 0x1, PGA gain = x32 1.5 µs tSample_GPAMP Sampling time with GPAMP 12-bit mode 2.5 µs tSample_SupplyMon Sample time with Supply Monitor (VDD/3) 12-bit mode 3 µs Only applies for devices with OPA over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fADCCLK ADC clock frequency 4 32 MHz tADC trigger Software trigger minimum width 3 ADCCLK cycles tSample Sampling time without OPA 12-bit mode, RS = 50Ω, Cpext = 10pF 156 ns tSample_PGA Sampling time with OPA #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376828/SFDY6E128LC3_SF1 12-bit mode GBW = 0x1, PGA gain = x1 0.31 µs GBW = 0x1, PGA gain = x32 1.5 µs tSample_GPAMP Sampling time with GPAMP 12-bit mode 2.5 µs tSample_SupplyMon Sample time with Supply Monitor (VDD/3) 12-bit mode 3 µs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fADCCLK ADC clock frequency 4 32 MHz tADC trigger Software trigger minimum width 3 ADCCLK cycles tSample Sampling time without OPA 12-bit mode, RS = 50Ω, Cpext = 10pF 156 ns tSample_PGA Sampling time with OPA #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376828/SFDY6E128LC3_SF1 12-bit mode GBW = 0x1, PGA gain = x1 0.31 µs GBW = 0x1, PGA gain = x32 1.5 µs tSample_GPAMP Sampling time with GPAMP 12-bit mode 2.5 µs tSample_SupplyMon Sample time with Supply Monitor (VDD/3) 12-bit mode 3 µs PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT fADCCLK ADC clock frequency 4 32 MHz tADC trigger Software trigger minimum width 3 ADCCLK cycles tSample Sampling time without OPA 12-bit mode, RS = 50Ω, Cpext = 10pF 156 ns tSample_PGA Sampling time with OPA #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376828/SFDY6E128LC3_SF1 12-bit mode GBW = 0x1, PGA gain = x1 0.31 µs GBW = 0x1, PGA gain = x32 1.5 µs tSample_GPAMP Sampling time with GPAMP 12-bit mode 2.5 µs tSample_SupplyMon Sample time with Supply Monitor (VDD/3) 12-bit mode 3 µs fADCCLK ADC clock frequency 4 32 MHz fADCCLK ADCCLKADC clock frequency432MHz tADC trigger Software trigger minimum width 3 ADCCLK cycles tADC trigger ADC trigger Software trigger minimum width3ADCCLK cycles tSample Sampling time without OPA 12-bit mode, RS = 50Ω, Cpext = 10pF 156 ns tSample SampleSampling time without OPA12-bit mode, RS = 50Ω, Cpext = 10pF Spext156ns tSample_PGA Sampling time with OPA #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376828/SFDY6E128LC3_SF1 12-bit mode GBW = 0x1, PGA gain = x1 0.31 µs tSample_PGA Sample_PGASampling time with OPA #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376828/SFDY6E128LC3_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376828/SFDY6E128LC3_SF112-bit modeGBW = 0x1, PGA gain = x10.31µs GBW = 0x1, PGA gain = x32 1.5 µs GBW = 0x1, PGA gain = x321.5µs tSample_GPAMP Sampling time with GPAMP 12-bit mode 2.5 µs tSample_GPAMP Sample_GPAMPSampling time with GPAMP12-bit mode2.5µs tSample_SupplyMon Sample time with Supply Monitor (VDD/3) 12-bit mode 3 µs tSample_SupplyMon Sample_SupplyMonSample time with Supply Monitor (VDD/3)12-bit mode3µs Only applies for devices with OPA Only applies for devices with OPA Linearity Parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted), all TYP values are measured at 25℃ and all linearity parameters are measured using 12-bit resolution mode (unless otherwise noted) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFQ2EE8MT8H7_SF2 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EI Integral linearity error (INL) External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -2.0 +2.0 LSB ED Differential linearity error (DNL)Guaranteed no missing codes External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -1.0 +1.0 LSB EO Offset error External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -3 3 mV Internal reference, VR+ = VREF = 2.5V -3 3 mV EG Gain error External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -3 3 LSB Total Unadjusted Error (TUE) can be calculated from EI , EO , and EG using the following formula: TUE = √( EI 2 + \|EO\|2 + EG 2 )Note: You must convert all of the errors into the same unit, usually LSB, for the above equation to be accurate All external reference specifications are measured with VR+ = VREF+ = VDD = 3.3V and VR- = VREF- = VSS = 0V and external 1uF cap on VREF+ pin Linearity Parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted), all TYP values are measured at 25℃ and all linearity parameters are measured using 12-bit resolution mode (unless otherwise noted) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFQ2EE8MT8H7_SF2 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EI Integral linearity error (INL) External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -2.0 +2.0 LSB ED Differential linearity error (DNL)Guaranteed no missing codes External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -1.0 +1.0 LSB EO Offset error External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -3 3 mV Internal reference, VR+ = VREF = 2.5V -3 3 mV EG Gain error External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -3 3 LSB Total Unadjusted Error (TUE) can be calculated from EI , EO , and EG using the following formula: TUE = √( EI 2 + \|EO\|2 + EG 2 )Note: You must convert all of the errors into the same unit, usually LSB, for the above equation to be accurate All external reference specifications are measured with VR+ = VREF+ = VDD = 3.3V and VR- = VREF- = VSS = 0V and external 1uF cap on VREF+ pin over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted), all TYP values are measured at 25℃ and all linearity parameters are measured using 12-bit resolution mode (unless otherwise noted) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFQ2EE8MT8H7_SF2 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EI Integral linearity error (INL) External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -2.0 +2.0 LSB ED Differential linearity error (DNL)Guaranteed no missing codes External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -1.0 +1.0 LSB EO Offset error External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -3 3 mV Internal reference, VR+ = VREF = 2.5V -3 3 mV EG Gain error External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -3 3 LSB over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted), all TYP values are measured at 25℃ and all linearity parameters are measured using 12-bit resolution mode (unless otherwise noted) #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFQ2EE8MT8H7_SF2 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFQ2EE8MT8H7_SF2 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EI Integral linearity error (INL) External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -2.0 +2.0 LSB ED Differential linearity error (DNL)Guaranteed no missing codes External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -1.0 +1.0 LSB EO Offset error External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -3 3 mV Internal reference, VR+ = VREF = 2.5V -3 3 mV EG Gain error External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -3 3 LSB PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT EI Integral linearity error (INL) External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -2.0 +2.0 LSB ED Differential linearity error (DNL)Guaranteed no missing codes External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -1.0 +1.0 LSB EO Offset error External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -3 3 mV Internal reference, VR+ = VREF = 2.5V -3 3 mV EG Gain error External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -3 3 LSB EI Integral linearity error (INL) External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -2.0 +2.0 LSB EI IIntegral linearity error (INL)External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2-2.0+2.0LSB ED Differential linearity error (DNL)Guaranteed no missing codes External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -1.0 +1.0 LSB ED DDifferential linearity error (DNL)Guaranteed no missing codesExternal reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2-1.0+1.0LSB EO Offset error External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -3 3 mV EO OOffset errorExternal reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2-33mV Internal reference, VR+ = VREF = 2.5V -3 3 mV Internal reference, VR+ = VREF = 2.5VR+ -33mV EG Gain error External reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 -3 3 LSB EG GGain errorExternal reference #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376829/SFYI2GZ1R07._SF2-33LSB Total Unadjusted Error (TUE) can be calculated from EI , EO , and EG using the following formula: TUE = √( EI 2 + \|EO\|2 + EG 2 )Note: You must convert all of the errors into the same unit, usually LSB, for the above equation to be accurate All external reference specifications are measured with VR+ = VREF+ = VDD = 3.3V and VR- = VREF- = VSS = 0V and external 1uF cap on VREF+ pin Total Unadjusted Error (TUE) can be calculated from EI , EO , and EG using the following formula: TUE = √( EI 2 + \|EO\|2 + EG 2 )Note: You must convert all of the errors into the same unit, usually LSB, for the above equation to be accurateI O G I2 O2 G2 All external reference specifications are measured with VR+ = VREF+ = VDD = 3.3V and VR- = VREF- = VSS = 0V and external 1uF cap on VREF+ pin Typical Connection Diagram ADC Input Network Refer to ADC Electrical Characteristics for the values of Rin and CS/H Refer to Digital IO Electrical Characteristics for the value of CI Cpar and Rpar represent the parasitic capacitance and resistance of the external ADC input circuitry Use the following equations to solve for the minimum sampling time (T) required for an ADC conversion: Tau = (Rpar + Rin) × CS/H + Rpar × (Cpar + CI) K= ln(2n/Settling error) – ln((Cpar + CI)/CS/H) T (Min sampling time) = K × Tau Typical Connection Diagram ADC Input Network Refer to ADC Electrical Characteristics for the values of Rin and CS/H Refer to Digital IO Electrical Characteristics for the value of CI Cpar and Rpar represent the parasitic capacitance and resistance of the external ADC input circuitry Use the following equations to solve for the minimum sampling time (T) required for an ADC conversion: Tau = (Rpar + Rin) × CS/H + Rpar × (Cpar + CI) K= ln(2n/Settling error) – ln((Cpar + CI)/CS/H) T (Min sampling time) = K × Tau ADC Input Network Refer to ADC Electrical Characteristics for the values of Rin and CS/H Refer to Digital IO Electrical Characteristics for the value of CI Cpar and Rpar represent the parasitic capacitance and resistance of the external ADC input circuitry Use the following equations to solve for the minimum sampling time (T) required for an ADC conversion: Tau = (Rpar + Rin) × CS/H + Rpar × (Cpar + CI) K= ln(2n/Settling error) – ln((Cpar + CI)/CS/H) T (Min sampling time) = K × Tau ADC Input Network ADC Input Network Refer to ADC Electrical Characteristics for the values of Rin and CS/H Refer to Digital IO Electrical Characteristics for the value of CI Cpar and Rpar represent the parasitic capacitance and resistance of the external ADC input circuitry Refer to ADC Electrical Characteristics for the values of Rin and CS/H Refer to Digital IO Electrical Characteristics for the value of CI Cpar and Rpar represent the parasitic capacitance and resistance of the external ADC input circuitry Refer to ADC Electrical Characteristics for the values of Rin and CS/H ADC Electrical CharacteristicsinS/HRefer to Digital IO Electrical Characteristics for the value of CI Digital IO Electrical CharacteristicsICpar and Rpar represent the parasitic capacitance and resistance of the external ADC input circuitryparparUse the following equations to solve for the minimum sampling time (T) required for an ADC conversion: Tau = (Rpar + Rin) × CS/H + Rpar × (Cpar + CI) K= ln(2n/Settling error) – ln((Cpar + CI)/CS/H) T (Min sampling time) = K × Tau Tau = (Rpar + Rin) × CS/H + Rpar × (Cpar + CI) K= ln(2n/Settling error) – ln((Cpar + CI)/CS/H) T (Min sampling time) = K × Tau Tau = (Rpar + Rin) × CS/H + Rpar × (Cpar + CI)parinS/HparparIK= ln(2n/Settling error) – ln((Cpar + CI)/CS/H)nparIS/HT (Min sampling time) = K × Tau Temperature Sensor over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TSTRIM Factory trim temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376811/SF6JDHGGO20J ADC and VREF configuration: RES=0 (12-bit mode), VRSEL=2h (internal VREF), BUFCONFIG=1h (1.4V VREF), ADC tSample=12.5µs 27 30 33 ℃ TSc Temperature coefficient -1.84 -1.75 -1.66 mV/℃ tSET, TS Temperature sensor settling time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376811/SFS6639BTC85 2.5 10 us Higher absolute accuracy may be achieved through user calibration. This is the maximum time required for the temperature sensor to settle when measured by the ADC. It may be used to specify the minimum ADC sample time when measuring the temperature sensor. Temperature Sensor over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TSTRIM Factory trim temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376811/SF6JDHGGO20J ADC and VREF configuration: RES=0 (12-bit mode), VRSEL=2h (internal VREF), BUFCONFIG=1h (1.4V VREF), ADC tSample=12.5µs 27 30 33 ℃ TSc Temperature coefficient -1.84 -1.75 -1.66 mV/℃ tSET, TS Temperature sensor settling time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376811/SFS6639BTC85 2.5 10 us Higher absolute accuracy may be achieved through user calibration. This is the maximum time required for the temperature sensor to settle when measured by the ADC. It may be used to specify the minimum ADC sample time when measuring the temperature sensor. over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TSTRIM Factory trim temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376811/SF6JDHGGO20J ADC and VREF configuration: RES=0 (12-bit mode), VRSEL=2h (internal VREF), BUFCONFIG=1h (1.4V VREF), ADC tSample=12.5µs 27 30 33 ℃ TSc Temperature coefficient -1.84 -1.75 -1.66 mV/℃ tSET, TS Temperature sensor settling time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376811/SFS6639BTC85 2.5 10 us over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TSTRIM Factory trim temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376811/SF6JDHGGO20J ADC and VREF configuration: RES=0 (12-bit mode), VRSEL=2h (internal VREF), BUFCONFIG=1h (1.4V VREF), ADC tSample=12.5µs 27 30 33 ℃ TSc Temperature coefficient -1.84 -1.75 -1.66 mV/℃ tSET, TS Temperature sensor settling time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376811/SFS6639BTC85 2.5 10 us PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT TSTRIM Factory trim temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376811/SF6JDHGGO20J ADC and VREF configuration: RES=0 (12-bit mode), VRSEL=2h (internal VREF), BUFCONFIG=1h (1.4V VREF), ADC tSample=12.5µs 27 30 33 ℃ TSc Temperature coefficient -1.84 -1.75 -1.66 mV/℃ tSET, TS Temperature sensor settling time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376811/SFS6639BTC85 2.5 10 us TSTRIM Factory trim temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376811/SF6JDHGGO20J ADC and VREF configuration: RES=0 (12-bit mode), VRSEL=2h (internal VREF), BUFCONFIG=1h (1.4V VREF), ADC tSample=12.5µs 27 30 33 ℃ TSTRIM TRIMFactory trim temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376811/SF6JDHGGO20J #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376811/SF6JDHGGO20JADC and VREF configuration: RES=0 (12-bit mode), VRSEL=2h (internal VREF), BUFCONFIG=1h (1.4V VREF), ADC tSample=12.5µsSample273033℃ TSc Temperature coefficient -1.84 -1.75 -1.66 mV/℃ TSc cTemperature coefficient-1.84-1.75-1.66mV/℃ tSET, TS Temperature sensor settling time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376811/SFS6639BTC85 2.5 10 us tSET, TS SET, TSTemperature sensor settling time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376811/SFS6639BTC85 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376811/SFS6639BTC852.510us Higher absolute accuracy may be achieved through user calibration. This is the maximum time required for the temperature sensor to settle when measured by the ADC. It may be used to specify the minimum ADC sample time when measuring the temperature sensor. Higher absolute accuracy may be achieved through user calibration.This is the maximum time required for the temperature sensor to settle when measured by the ADC. It may be used to specify the minimum ADC sample time when measuring the temperature sensor. VREF Voltage Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDDmin Minimum supply voltage needed for VREF operation BUFCONFIG = 1 1.62 V BUFCONFIG = 0 2.7 VREF Voltage reference output voltage BUFCONFIG = 1 1.379 1.4 1.421 V BUFCONFIG = 0 2.462 2.5 2.538 Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IVREF VREF operating supply current BUFCONFIG = {0, 1}, No load 74 100 µA TCVREF Temperature coefficient of VREF #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376815/A_SF_TM_VREF_ELECTRICAL_CHARACTERISTICS_FOOTER1_SF1 BUFCONFIG = {0, 1} 200 ppm/°C TCdrift Long term VREF drift Time = 1000 hours, BUFCONFIG = {0, 1}, T = 25℃ 300 ppm PSRRDC VREF Power supply rejection ratio, DC VDD = 1.7 V to VDDmax, BUFCONFIG = 1 59 64 dB VDD = 2.7 V to VDDmax, BUFCONFIG = 0 49 53 Vnoise RMS noise at VREF output (0.1 Hz to 100 MHz) BUFFCONFIG = 1 500 µVrms BUFFCONFIG = 0 750 ADC FS Max supported ADC sampling frequency Using VREF as ADC reference 200 ksps Tstartup VREF startup time BUFCONFIG = {0, 1} , VDD = 2.8 V 15 us The temperature coefficient of the VREF output is the sum of TCVRBUF and the temperature coefficient of the internal bandgap reference. VREF Voltage Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDDmin Minimum supply voltage needed for VREF operation BUFCONFIG = 1 1.62 V BUFCONFIG = 0 2.7 VREF Voltage reference output voltage BUFCONFIG = 1 1.379 1.4 1.421 V BUFCONFIG = 0 2.462 2.5 2.538 Voltage Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDDmin Minimum supply voltage needed for VREF operation BUFCONFIG = 1 1.62 V BUFCONFIG = 0 2.7 VREF Voltage reference output voltage BUFCONFIG = 1 1.379 1.4 1.421 V BUFCONFIG = 0 2.462 2.5 2.538 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDDmin Minimum supply voltage needed for VREF operation BUFCONFIG = 1 1.62 V BUFCONFIG = 0 2.7 VREF Voltage reference output voltage BUFCONFIG = 1 1.379 1.4 1.421 V BUFCONFIG = 0 2.462 2.5 2.538 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDDmin Minimum supply voltage needed for VREF operation BUFCONFIG = 1 1.62 V BUFCONFIG = 0 2.7 VREF Voltage reference output voltage BUFCONFIG = 1 1.379 1.4 1.421 V BUFCONFIG = 0 2.462 2.5 2.538 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT VDDmin Minimum supply voltage needed for VREF operation BUFCONFIG = 1 1.62 V BUFCONFIG = 0 2.7 VREF Voltage reference output voltage BUFCONFIG = 1 1.379 1.4 1.421 V BUFCONFIG = 0 2.462 2.5 2.538 VDDmin Minimum supply voltage needed for VREF operation BUFCONFIG = 1 1.62 V VDDmin minMinimum supply voltage needed for VREF operationBUFCONFIG = 11.62V BUFCONFIG = 0 2.7 BUFCONFIG = 02.7 VREF Voltage reference output voltage BUFCONFIG = 1 1.379 1.4 1.421 V VREFVoltage reference output voltageBUFCONFIG = 11.3791.41.421V BUFCONFIG = 0 2.462 2.5 2.538 BUFCONFIG = 02.4622.52.538 Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IVREF VREF operating supply current BUFCONFIG = {0, 1}, No load 74 100 µA TCVREF Temperature coefficient of VREF #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376815/A_SF_TM_VREF_ELECTRICAL_CHARACTERISTICS_FOOTER1_SF1 BUFCONFIG = {0, 1} 200 ppm/°C TCdrift Long term VREF drift Time = 1000 hours, BUFCONFIG = {0, 1}, T = 25℃ 300 ppm PSRRDC VREF Power supply rejection ratio, DC VDD = 1.7 V to VDDmax, BUFCONFIG = 1 59 64 dB VDD = 2.7 V to VDDmax, BUFCONFIG = 0 49 53 Vnoise RMS noise at VREF output (0.1 Hz to 100 MHz) BUFFCONFIG = 1 500 µVrms BUFFCONFIG = 0 750 ADC FS Max supported ADC sampling frequency Using VREF as ADC reference 200 ksps Tstartup VREF startup time BUFCONFIG = {0, 1} , VDD = 2.8 V 15 us The temperature coefficient of the VREF output is the sum of TCVRBUF and the temperature coefficient of the internal bandgap reference. Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IVREF VREF operating supply current BUFCONFIG = {0, 1}, No load 74 100 µA TCVREF Temperature coefficient of VREF #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376815/A_SF_TM_VREF_ELECTRICAL_CHARACTERISTICS_FOOTER1_SF1 BUFCONFIG = {0, 1} 200 ppm/°C TCdrift Long term VREF drift Time = 1000 hours, BUFCONFIG = {0, 1}, T = 25℃ 300 ppm PSRRDC VREF Power supply rejection ratio, DC VDD = 1.7 V to VDDmax, BUFCONFIG = 1 59 64 dB VDD = 2.7 V to VDDmax, BUFCONFIG = 0 49 53 Vnoise RMS noise at VREF output (0.1 Hz to 100 MHz) BUFFCONFIG = 1 500 µVrms BUFFCONFIG = 0 750 ADC FS Max supported ADC sampling frequency Using VREF as ADC reference 200 ksps Tstartup VREF startup time BUFCONFIG = {0, 1} , VDD = 2.8 V 15 us The temperature coefficient of the VREF output is the sum of TCVRBUF and the temperature coefficient of the internal bandgap reference. over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IVREF VREF operating supply current BUFCONFIG = {0, 1}, No load 74 100 µA TCVREF Temperature coefficient of VREF #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376815/A_SF_TM_VREF_ELECTRICAL_CHARACTERISTICS_FOOTER1_SF1 BUFCONFIG = {0, 1} 200 ppm/°C TCdrift Long term VREF drift Time = 1000 hours, BUFCONFIG = {0, 1}, T = 25℃ 300 ppm PSRRDC VREF Power supply rejection ratio, DC VDD = 1.7 V to VDDmax, BUFCONFIG = 1 59 64 dB VDD = 2.7 V to VDDmax, BUFCONFIG = 0 49 53 Vnoise RMS noise at VREF output (0.1 Hz to 100 MHz) BUFFCONFIG = 1 500 µVrms BUFFCONFIG = 0 750 ADC FS Max supported ADC sampling frequency Using VREF as ADC reference 200 ksps Tstartup VREF startup time BUFCONFIG = {0, 1} , VDD = 2.8 V 15 us over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IVREF VREF operating supply current BUFCONFIG = {0, 1}, No load 74 100 µA TCVREF Temperature coefficient of VREF #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376815/A_SF_TM_VREF_ELECTRICAL_CHARACTERISTICS_FOOTER1_SF1 BUFCONFIG = {0, 1} 200 ppm/°C TCdrift Long term VREF drift Time = 1000 hours, BUFCONFIG = {0, 1}, T = 25℃ 300 ppm PSRRDC VREF Power supply rejection ratio, DC VDD = 1.7 V to VDDmax, BUFCONFIG = 1 59 64 dB VDD = 2.7 V to VDDmax, BUFCONFIG = 0 49 53 Vnoise RMS noise at VREF output (0.1 Hz to 100 MHz) BUFFCONFIG = 1 500 µVrms BUFFCONFIG = 0 750 ADC FS Max supported ADC sampling frequency Using VREF as ADC reference 200 ksps Tstartup VREF startup time BUFCONFIG = {0, 1} , VDD = 2.8 V 15 us PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT IVREF VREF operating supply current BUFCONFIG = {0, 1}, No load 74 100 µA TCVREF Temperature coefficient of VREF #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376815/A_SF_TM_VREF_ELECTRICAL_CHARACTERISTICS_FOOTER1_SF1 BUFCONFIG = {0, 1} 200 ppm/°C TCdrift Long term VREF drift Time = 1000 hours, BUFCONFIG = {0, 1}, T = 25℃ 300 ppm PSRRDC VREF Power supply rejection ratio, DC VDD = 1.7 V to VDDmax, BUFCONFIG = 1 59 64 dB VDD = 2.7 V to VDDmax, BUFCONFIG = 0 49 53 Vnoise RMS noise at VREF output (0.1 Hz to 100 MHz) BUFFCONFIG = 1 500 µVrms BUFFCONFIG = 0 750 ADC FS Max supported ADC sampling frequency Using VREF as ADC reference 200 ksps Tstartup VREF startup time BUFCONFIG = {0, 1} , VDD = 2.8 V 15 us IVREF VREF operating supply current BUFCONFIG = {0, 1}, No load 74 100 µA IVREF VREFVREF operating supply currentBUFCONFIG = {0, 1}, No load74100µA TCVREF Temperature coefficient of VREF #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376815/A_SF_TM_VREF_ELECTRICAL_CHARACTERISTICS_FOOTER1_SF1 BUFCONFIG = {0, 1} 200 ppm/°C TCVREF VREFTemperature coefficient of VREF #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376815/A_SF_TM_VREF_ELECTRICAL_CHARACTERISTICS_FOOTER1_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376815/A_SF_TM_VREF_ELECTRICAL_CHARACTERISTICS_FOOTER1_SF1BUFCONFIG = {0, 1}200ppm/°C TCdrift Long term VREF drift Time = 1000 hours, BUFCONFIG = {0, 1}, T = 25℃ 300 ppm TCdrift driftLong term VREF driftTime = 1000 hours, BUFCONFIG = {0, 1}, T = 25℃300ppm PSRRDC VREF Power supply rejection ratio, DC VDD = 1.7 V to VDDmax, BUFCONFIG = 1 59 64 dB PSRRDC DCVREF Power supply rejection ratio, DCVDD = 1.7 V to VDDmax, BUFCONFIG = 15964dB VDD = 2.7 V to VDDmax, BUFCONFIG = 0 49 53 VDD = 2.7 V to VDDmax, BUFCONFIG = 04953 Vnoise RMS noise at VREF output (0.1 Hz to 100 MHz) BUFFCONFIG = 1 500 µVrms Vnoise noiseRMS noise at VREF output (0.1 Hz to 100 MHz)BUFFCONFIG = 1500µVrms BUFFCONFIG = 0 750 BUFFCONFIG = 0750 ADC FS Max supported ADC sampling frequency Using VREF as ADC reference 200 ksps ADC FS SMax supported ADC sampling frequencyUsing VREF as ADC reference200ksps Tstartup VREF startup time BUFCONFIG = {0, 1} , VDD = 2.8 V 15 us Tstartup startupVREF startup timeBUFCONFIG = {0, 1} , VDD = 2.8 V15us The temperature coefficient of the VREF output is the sum of TCVRBUF and the temperature coefficient of the internal bandgap reference. The temperature coefficient of the VREF output is the sum of TCVRBUF and the temperature coefficient of the internal bandgap reference.VRBUF COMP Comparator Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Comparator Electrical Characteristics Vcm Common mode input range 0 VDD V Voffset Input offset voltage ±25 mV Vhys DC input hysteresis HYST=00h 0.4 mV HYST=01h 11 HYST=02h 20 HYST=03h 30 tPD_ls Propagation delay, response time Output Filter off, Overdrive = 100 mV, High Speed Mode 32 50 ns Output Filter off, Overdrive = 100 mV, Low Power Mode 5 µs ten Comparator enable time Startup time to reach propagation delay specification, High Speed Mode 10 µs Startup time to reach propagation delay specification, Low Power Mode 10 µs Icomp Comparator current consumption. Vcm = VDD/2, 100mV overdrive, DAC output as a voltage reference, VDD is reference for DAC, High Speed Mode 120 200 µA Vcm = VDD/2, 100mV overdrive, DAC output as a voltage reference, VDD is reference for DAC, Low Power Mode 0.8 2.7 µA Vcm = VDD/2, 100mV overdrive, comparator only. High Speed Mode 100 180 µA Vcm = VDD/2, 100mV overdrive, comparator only, Low Power Mode 0.7 2.1 µA 8-bit DAC Electrical Characteristics Vdac DAC output range 0 VDD V Vdac-code 8-bit DAC output voltage for a given code VIN = reference voltage into 8-bit DAC, code n = 0 to 255 VIN × (n+1) / 256 V INL Integral nonlinearity of 8-bit DAC -1 1 LSB DNL Differential nonlinearity of 8-bit DAC -1 1 LSB Gain error Gain error of 8-bit DAC Reference voltage = VDD -2 2 % of FSR Offset error Offset error of 8-bit DAC -5 5 mV tdac_settle 8-bit DAC settling time in static mode DACCODE0 = 0 → 255, DAC output accurate to 1 LSB 1.5 µs COMP COMP Comparator Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Comparator Electrical Characteristics Vcm Common mode input range 0 VDD V Voffset Input offset voltage ±25 mV Vhys DC input hysteresis HYST=00h 0.4 mV HYST=01h 11 HYST=02h 20 HYST=03h 30 tPD_ls Propagation delay, response time Output Filter off, Overdrive = 100 mV, High Speed Mode 32 50 ns Output Filter off, Overdrive = 100 mV, Low Power Mode 5 µs ten Comparator enable time Startup time to reach propagation delay specification, High Speed Mode 10 µs Startup time to reach propagation delay specification, Low Power Mode 10 µs Icomp Comparator current consumption. Vcm = VDD/2, 100mV overdrive, DAC output as a voltage reference, VDD is reference for DAC, High Speed Mode 120 200 µA Vcm = VDD/2, 100mV overdrive, DAC output as a voltage reference, VDD is reference for DAC, Low Power Mode 0.8 2.7 µA Vcm = VDD/2, 100mV overdrive, comparator only. High Speed Mode 100 180 µA Vcm = VDD/2, 100mV overdrive, comparator only, Low Power Mode 0.7 2.1 µA 8-bit DAC Electrical Characteristics Vdac DAC output range 0 VDD V Vdac-code 8-bit DAC output voltage for a given code VIN = reference voltage into 8-bit DAC, code n = 0 to 255 VIN × (n+1) / 256 V INL Integral nonlinearity of 8-bit DAC -1 1 LSB DNL Differential nonlinearity of 8-bit DAC -1 1 LSB Gain error Gain error of 8-bit DAC Reference voltage = VDD -2 2 % of FSR Offset error Offset error of 8-bit DAC -5 5 mV tdac_settle 8-bit DAC settling time in static mode DACCODE0 = 0 → 255, DAC output accurate to 1 LSB 1.5 µs Comparator Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Comparator Electrical Characteristics Vcm Common mode input range 0 VDD V Voffset Input offset voltage ±25 mV Vhys DC input hysteresis HYST=00h 0.4 mV HYST=01h 11 HYST=02h 20 HYST=03h 30 tPD_ls Propagation delay, response time Output Filter off, Overdrive = 100 mV, High Speed Mode 32 50 ns Output Filter off, Overdrive = 100 mV, Low Power Mode 5 µs ten Comparator enable time Startup time to reach propagation delay specification, High Speed Mode 10 µs Startup time to reach propagation delay specification, Low Power Mode 10 µs Icomp Comparator current consumption. Vcm = VDD/2, 100mV overdrive, DAC output as a voltage reference, VDD is reference for DAC, High Speed Mode 120 200 µA Vcm = VDD/2, 100mV overdrive, DAC output as a voltage reference, VDD is reference for DAC, Low Power Mode 0.8 2.7 µA Vcm = VDD/2, 100mV overdrive, comparator only. High Speed Mode 100 180 µA Vcm = VDD/2, 100mV overdrive, comparator only, Low Power Mode 0.7 2.1 µA 8-bit DAC Electrical Characteristics Vdac DAC output range 0 VDD V Vdac-code 8-bit DAC output voltage for a given code VIN = reference voltage into 8-bit DAC, code n = 0 to 255 VIN × (n+1) / 256 V INL Integral nonlinearity of 8-bit DAC -1 1 LSB DNL Differential nonlinearity of 8-bit DAC -1 1 LSB Gain error Gain error of 8-bit DAC Reference voltage = VDD -2 2 % of FSR Offset error Offset error of 8-bit DAC -5 5 mV tdac_settle 8-bit DAC settling time in static mode DACCODE0 = 0 → 255, DAC output accurate to 1 LSB 1.5 µs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Comparator Electrical Characteristics Vcm Common mode input range 0 VDD V Voffset Input offset voltage ±25 mV Vhys DC input hysteresis HYST=00h 0.4 mV HYST=01h 11 HYST=02h 20 HYST=03h 30 tPD_ls Propagation delay, response time Output Filter off, Overdrive = 100 mV, High Speed Mode 32 50 ns Output Filter off, Overdrive = 100 mV, Low Power Mode 5 µs ten Comparator enable time Startup time to reach propagation delay specification, High Speed Mode 10 µs Startup time to reach propagation delay specification, Low Power Mode 10 µs Icomp Comparator current consumption. Vcm = VDD/2, 100mV overdrive, DAC output as a voltage reference, VDD is reference for DAC, High Speed Mode 120 200 µA Vcm = VDD/2, 100mV overdrive, DAC output as a voltage reference, VDD is reference for DAC, Low Power Mode 0.8 2.7 µA Vcm = VDD/2, 100mV overdrive, comparator only. High Speed Mode 100 180 µA Vcm = VDD/2, 100mV overdrive, comparator only, Low Power Mode 0.7 2.1 µA 8-bit DAC Electrical Characteristics Vdac DAC output range 0 VDD V Vdac-code 8-bit DAC output voltage for a given code VIN = reference voltage into 8-bit DAC, code n = 0 to 255 VIN × (n+1) / 256 V INL Integral nonlinearity of 8-bit DAC -1 1 LSB DNL Differential nonlinearity of 8-bit DAC -1 1 LSB Gain error Gain error of 8-bit DAC Reference voltage = VDD -2 2 % of FSR Offset error Offset error of 8-bit DAC -5 5 mV tdac_settle 8-bit DAC settling time in static mode DACCODE0 = 0 → 255, DAC output accurate to 1 LSB 1.5 µs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Comparator Electrical Characteristics Vcm Common mode input range 0 VDD V Voffset Input offset voltage ±25 mV Vhys DC input hysteresis HYST=00h 0.4 mV HYST=01h 11 HYST=02h 20 HYST=03h 30 tPD_ls Propagation delay, response time Output Filter off, Overdrive = 100 mV, High Speed Mode 32 50 ns Output Filter off, Overdrive = 100 mV, Low Power Mode 5 µs ten Comparator enable time Startup time to reach propagation delay specification, High Speed Mode 10 µs Startup time to reach propagation delay specification, Low Power Mode 10 µs Icomp Comparator current consumption. Vcm = VDD/2, 100mV overdrive, DAC output as a voltage reference, VDD is reference for DAC, High Speed Mode 120 200 µA Vcm = VDD/2, 100mV overdrive, DAC output as a voltage reference, VDD is reference for DAC, Low Power Mode 0.8 2.7 µA Vcm = VDD/2, 100mV overdrive, comparator only. High Speed Mode 100 180 µA Vcm = VDD/2, 100mV overdrive, comparator only, Low Power Mode 0.7 2.1 µA 8-bit DAC Electrical Characteristics Vdac DAC output range 0 VDD V Vdac-code 8-bit DAC output voltage for a given code VIN = reference voltage into 8-bit DAC, code n = 0 to 255 VIN × (n+1) / 256 V INL Integral nonlinearity of 8-bit DAC -1 1 LSB DNL Differential nonlinearity of 8-bit DAC -1 1 LSB Gain error Gain error of 8-bit DAC Reference voltage = VDD -2 2 % of FSR Offset error Offset error of 8-bit DAC -5 5 mV tdac_settle 8-bit DAC settling time in static mode DACCODE0 = 0 → 255, DAC output accurate to 1 LSB 1.5 µs PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT Comparator Electrical Characteristics Vcm Common mode input range 0 VDD V Voffset Input offset voltage ±25 mV Vhys DC input hysteresis HYST=00h 0.4 mV HYST=01h 11 HYST=02h 20 HYST=03h 30 tPD_ls Propagation delay, response time Output Filter off, Overdrive = 100 mV, High Speed Mode 32 50 ns Output Filter off, Overdrive = 100 mV, Low Power Mode 5 µs ten Comparator enable time Startup time to reach propagation delay specification, High Speed Mode 10 µs Startup time to reach propagation delay specification, Low Power Mode 10 µs Icomp Comparator current consumption. Vcm = VDD/2, 100mV overdrive, DAC output as a voltage reference, VDD is reference for DAC, High Speed Mode 120 200 µA Vcm = VDD/2, 100mV overdrive, DAC output as a voltage reference, VDD is reference for DAC, Low Power Mode 0.8 2.7 µA Vcm = VDD/2, 100mV overdrive, comparator only. High Speed Mode 100 180 µA Vcm = VDD/2, 100mV overdrive, comparator only, Low Power Mode 0.7 2.1 µA 8-bit DAC Electrical Characteristics Vdac DAC output range 0 VDD V Vdac-code 8-bit DAC output voltage for a given code VIN = reference voltage into 8-bit DAC, code n = 0 to 255 VIN × (n+1) / 256 V INL Integral nonlinearity of 8-bit DAC -1 1 LSB DNL Differential nonlinearity of 8-bit DAC -1 1 LSB Gain error Gain error of 8-bit DAC Reference voltage = VDD -2 2 % of FSR Offset error Offset error of 8-bit DAC -5 5 mV tdac_settle 8-bit DAC settling time in static mode DACCODE0 = 0 → 255, DAC output accurate to 1 LSB 1.5 µs Comparator Electrical Characteristics Comparator Electrical Characteristics Vcm Common mode input range 0 VDD V VcmCommon mode input range0VDDV Voffset Input offset voltage ±25 mV Voffset offsetInput offset voltage±25mV Vhys DC input hysteresis HYST=00h 0.4 mV Vhys hysDC input hysteresisHYST=00h0.4mV HYST=01h 11 HYST=01h11 HYST=02h 20 HYST=02h20 HYST=03h 30 HYST=03h30 tPD_ls Propagation delay, response time Output Filter off, Overdrive = 100 mV, High Speed Mode 32 50 ns tPD_ls PD_lsPropagation delay, response timeOutput Filter off, Overdrive = 100 mV, High Speed Mode3250ns Output Filter off, Overdrive = 100 mV, Low Power Mode 5 µs Output Filter off, Overdrive = 100 mV, Low Power Mode5µs ten Comparator enable time Startup time to reach propagation delay specification, High Speed Mode 10 µs ten enComparator enable timeStartup time to reach propagation delay specification, High Speed Mode10µs Startup time to reach propagation delay specification, Low Power Mode 10 µs Startup time to reach propagation delay specification, Low Power Mode10µs Icomp Comparator current consumption. Vcm = VDD/2, 100mV overdrive, DAC output as a voltage reference, VDD is reference for DAC, High Speed Mode 120 200 µA Icomp compComparator current consumption. Vcm = VDD/2, 100mV overdrive, DAC output as a voltage reference, VDD is reference for DAC, High Speed Mode120200µA Vcm = VDD/2, 100mV overdrive, DAC output as a voltage reference, VDD is reference for DAC, Low Power Mode 0.8 2.7 µA Vcm = VDD/2, 100mV overdrive, DAC output as a voltage reference, VDD is reference for DAC, Low Power Mode0.82.7µA Vcm = VDD/2, 100mV overdrive, comparator only. High Speed Mode 100 180 µA Vcm = VDD/2, 100mV overdrive, comparator only. High Speed Mode100180µA Vcm = VDD/2, 100mV overdrive, comparator only, Low Power Mode 0.7 2.1 µA Vcm = VDD/2, 100mV overdrive, comparator only, Low Power Mode0.72.1µA 8-bit DAC Electrical Characteristics 8-bit DAC Electrical Characteristics Vdac DAC output range 0 VDD V Vdac dacDAC output range0VDDV Vdac-code 8-bit DAC output voltage for a given code VIN = reference voltage into 8-bit DAC, code n = 0 to 255 VIN × (n+1) / 256 V Vdac-code dac-code8-bit DAC output voltage for a given codeVIN = reference voltage into 8-bit DAC, code n = 0 to 255VIN × (n+1) / 256V INL Integral nonlinearity of 8-bit DAC -1 1 LSB INLIntegral nonlinearity of 8-bit DAC-11LSB DNL Differential nonlinearity of 8-bit DAC -1 1 LSB DNLDifferential nonlinearity of 8-bit DAC-11LSB Gain error Gain error of 8-bit DAC Reference voltage = VDD -2 2 % of FSR Gain errorGain error of 8-bit DACReference voltage = VDD-22% of FSR Offset error Offset error of 8-bit DAC -5 5 mV Offset errorOffset error of 8-bit DAC-55mV tdac_settle 8-bit DAC settling time in static mode DACCODE0 = 0 → 255, DAC output accurate to 1 LSB 1.5 µs tdac_settle dac_settle8-bit DAC settling time in static modeDACCODE0 = 0 → 255, DAC output accurate to 1 LSB1.5µs GPAMP Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCM Common mode voltage range RRI = 0x0 -0.1 VDD–1 V RRI = 0x1 1 VDD-0.2 RRI = 0x2 -0.1 VDD-0.2 Iq Quiescent current, per op-amp IO= 0 mA, RRI = 0x0 97 µA IO= 0 mA, RRI = 0x1 or 0x2 93 GBW Gain-bandwidth product CL = 200pF 0.32 MHz VOS Input offset voltage Noninverting, unity gain, TA = 25℃, VDD = 3.3V CHOPCLKMODE = 0x0 ±0.2 ±6.5 mV CHOPCLKMODE = 0x1 ±0.08 ±0.4 dVOS/dT Input offset voltage temperature drift Noninverting, unity gain CHOPCLKMODE = 0x0 7.7 µV/°C CHOPCLKMODE = 0x1 0.34 Ibias Input bias for muxed I/O pin at SoC 0.1V<Vin<VDD-0.3V, VDD=3.3V, CHOPCLKMODE=0x0 TA = 25°C ±40 pA TA = 125°C ±4000 0.1V<Vin<VDD-0.3V, VDD=3.3V, CHOPCLKMODE=0x1 TA = 25°C ±200 TA = 125°C ±4000 CMRRDC Common mode rejection ratio, DC Over common mode voltage range CHOPCLKMODE = 0x0 48 77 dB CHOPCLKMODE = 0x1 56 105 en Input voltage noise density Noninverting, unity gain f = 1 kHz 43 nV/√Hz f = 10 kHz 19 Rin Input resistance #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376816/SF.OB27_BQRM_SF1 0.65 kΩ Cin Input capacitance Common mode 4 pF Differential 2 AOL Open-loop voltage gain, DC RL = 350 kΩ, 0.3 < Vo < VDD-0.3 82 90 107 dB PM phase margin CL = 200 pF, RL= 350 kΩ 69 70 72 degree SR Slew rate Noninverting, unity gain, CL = 40 pF 0.32 V/µs THDN Total Harmonic Distortion + Noise 0.012 % ILoad Output load current ±4 mA CLoad Output load capacitance 200 pF The term 'Rin' refers to the input resistance of the multiplexer (mux) in the GPAMP. Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tEN GPAMP enable time ENABLE = 0x0 to 0x1, Bandgap reference ON, 0.1% Noninverting, unity gain 12 20 µs tdisable GPAMP disable time 4 ULPCLK Cycles tSETTLE GPAMP settling time CL = 200 pF, Vstep = 0.3V to VDD - 0.3V, 0.1%, ENABLE = 0x1 Noninverting, unity gain 9 µs GPAMP Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCM Common mode voltage range RRI = 0x0 -0.1 VDD–1 V RRI = 0x1 1 VDD-0.2 RRI = 0x2 -0.1 VDD-0.2 Iq Quiescent current, per op-amp IO= 0 mA, RRI = 0x0 97 µA IO= 0 mA, RRI = 0x1 or 0x2 93 GBW Gain-bandwidth product CL = 200pF 0.32 MHz VOS Input offset voltage Noninverting, unity gain, TA = 25℃, VDD = 3.3V CHOPCLKMODE = 0x0 ±0.2 ±6.5 mV CHOPCLKMODE = 0x1 ±0.08 ±0.4 dVOS/dT Input offset voltage temperature drift Noninverting, unity gain CHOPCLKMODE = 0x0 7.7 µV/°C CHOPCLKMODE = 0x1 0.34 Ibias Input bias for muxed I/O pin at SoC 0.1V<Vin<VDD-0.3V, VDD=3.3V, CHOPCLKMODE=0x0 TA = 25°C ±40 pA TA = 125°C ±4000 0.1V<Vin<VDD-0.3V, VDD=3.3V, CHOPCLKMODE=0x1 TA = 25°C ±200 TA = 125°C ±4000 CMRRDC Common mode rejection ratio, DC Over common mode voltage range CHOPCLKMODE = 0x0 48 77 dB CHOPCLKMODE = 0x1 56 105 en Input voltage noise density Noninverting, unity gain f = 1 kHz 43 nV/√Hz f = 10 kHz 19 Rin Input resistance #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376816/SF.OB27_BQRM_SF1 0.65 kΩ Cin Input capacitance Common mode 4 pF Differential 2 AOL Open-loop voltage gain, DC RL = 350 kΩ, 0.3 < Vo < VDD-0.3 82 90 107 dB PM phase margin CL = 200 pF, RL= 350 kΩ 69 70 72 degree SR Slew rate Noninverting, unity gain, CL = 40 pF 0.32 V/µs THDN Total Harmonic Distortion + Noise 0.012 % ILoad Output load current ±4 mA CLoad Output load capacitance 200 pF The term 'Rin' refers to the input resistance of the multiplexer (mux) in the GPAMP. Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCM Common mode voltage range RRI = 0x0 -0.1 VDD–1 V RRI = 0x1 1 VDD-0.2 RRI = 0x2 -0.1 VDD-0.2 Iq Quiescent current, per op-amp IO= 0 mA, RRI = 0x0 97 µA IO= 0 mA, RRI = 0x1 or 0x2 93 GBW Gain-bandwidth product CL = 200pF 0.32 MHz VOS Input offset voltage Noninverting, unity gain, TA = 25℃, VDD = 3.3V CHOPCLKMODE = 0x0 ±0.2 ±6.5 mV CHOPCLKMODE = 0x1 ±0.08 ±0.4 dVOS/dT Input offset voltage temperature drift Noninverting, unity gain CHOPCLKMODE = 0x0 7.7 µV/°C CHOPCLKMODE = 0x1 0.34 Ibias Input bias for muxed I/O pin at SoC 0.1V<Vin<VDD-0.3V, VDD=3.3V, CHOPCLKMODE=0x0 TA = 25°C ±40 pA TA = 125°C ±4000 0.1V<Vin<VDD-0.3V, VDD=3.3V, CHOPCLKMODE=0x1 TA = 25°C ±200 TA = 125°C ±4000 CMRRDC Common mode rejection ratio, DC Over common mode voltage range CHOPCLKMODE = 0x0 48 77 dB CHOPCLKMODE = 0x1 56 105 en Input voltage noise density Noninverting, unity gain f = 1 kHz 43 nV/√Hz f = 10 kHz 19 Rin Input resistance #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376816/SF.OB27_BQRM_SF1 0.65 kΩ Cin Input capacitance Common mode 4 pF Differential 2 AOL Open-loop voltage gain, DC RL = 350 kΩ, 0.3 < Vo < VDD-0.3 82 90 107 dB PM phase margin CL = 200 pF, RL= 350 kΩ 69 70 72 degree SR Slew rate Noninverting, unity gain, CL = 40 pF 0.32 V/µs THDN Total Harmonic Distortion + Noise 0.012 % ILoad Output load current ±4 mA CLoad Output load capacitance 200 pF The term 'Rin' refers to the input resistance of the multiplexer (mux) in the GPAMP. over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCM Common mode voltage range RRI = 0x0 -0.1 VDD–1 V RRI = 0x1 1 VDD-0.2 RRI = 0x2 -0.1 VDD-0.2 Iq Quiescent current, per op-amp IO= 0 mA, RRI = 0x0 97 µA IO= 0 mA, RRI = 0x1 or 0x2 93 GBW Gain-bandwidth product CL = 200pF 0.32 MHz VOS Input offset voltage Noninverting, unity gain, TA = 25℃, VDD = 3.3V CHOPCLKMODE = 0x0 ±0.2 ±6.5 mV CHOPCLKMODE = 0x1 ±0.08 ±0.4 dVOS/dT Input offset voltage temperature drift Noninverting, unity gain CHOPCLKMODE = 0x0 7.7 µV/°C CHOPCLKMODE = 0x1 0.34 Ibias Input bias for muxed I/O pin at SoC 0.1V<Vin<VDD-0.3V, VDD=3.3V, CHOPCLKMODE=0x0 TA = 25°C ±40 pA TA = 125°C ±4000 0.1V<Vin<VDD-0.3V, VDD=3.3V, CHOPCLKMODE=0x1 TA = 25°C ±200 TA = 125°C ±4000 CMRRDC Common mode rejection ratio, DC Over common mode voltage range CHOPCLKMODE = 0x0 48 77 dB CHOPCLKMODE = 0x1 56 105 en Input voltage noise density Noninverting, unity gain f = 1 kHz 43 nV/√Hz f = 10 kHz 19 Rin Input resistance #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376816/SF.OB27_BQRM_SF1 0.65 kΩ Cin Input capacitance Common mode 4 pF Differential 2 AOL Open-loop voltage gain, DC RL = 350 kΩ, 0.3 < Vo < VDD-0.3 82 90 107 dB PM phase margin CL = 200 pF, RL= 350 kΩ 69 70 72 degree SR Slew rate Noninverting, unity gain, CL = 40 pF 0.32 V/µs THDN Total Harmonic Distortion + Noise 0.012 % ILoad Output load current ±4 mA CLoad Output load capacitance 200 pF over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCM Common mode voltage range RRI = 0x0 -0.1 VDD–1 V RRI = 0x1 1 VDD-0.2 RRI = 0x2 -0.1 VDD-0.2 Iq Quiescent current, per op-amp IO= 0 mA, RRI = 0x0 97 µA IO= 0 mA, RRI = 0x1 or 0x2 93 GBW Gain-bandwidth product CL = 200pF 0.32 MHz VOS Input offset voltage Noninverting, unity gain, TA = 25℃, VDD = 3.3V CHOPCLKMODE = 0x0 ±0.2 ±6.5 mV CHOPCLKMODE = 0x1 ±0.08 ±0.4 dVOS/dT Input offset voltage temperature drift Noninverting, unity gain CHOPCLKMODE = 0x0 7.7 µV/°C CHOPCLKMODE = 0x1 0.34 Ibias Input bias for muxed I/O pin at SoC 0.1V<Vin<VDD-0.3V, VDD=3.3V, CHOPCLKMODE=0x0 TA = 25°C ±40 pA TA = 125°C ±4000 0.1V<Vin<VDD-0.3V, VDD=3.3V, CHOPCLKMODE=0x1 TA = 25°C ±200 TA = 125°C ±4000 CMRRDC Common mode rejection ratio, DC Over common mode voltage range CHOPCLKMODE = 0x0 48 77 dB CHOPCLKMODE = 0x1 56 105 en Input voltage noise density Noninverting, unity gain f = 1 kHz 43 nV/√Hz f = 10 kHz 19 Rin Input resistance #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376816/SF.OB27_BQRM_SF1 0.65 kΩ Cin Input capacitance Common mode 4 pF Differential 2 AOL Open-loop voltage gain, DC RL = 350 kΩ, 0.3 < Vo < VDD-0.3 82 90 107 dB PM phase margin CL = 200 pF, RL= 350 kΩ 69 70 72 degree SR Slew rate Noninverting, unity gain, CL = 40 pF 0.32 V/µs THDN Total Harmonic Distortion + Noise 0.012 % ILoad Output load current ±4 mA CLoad Output load capacitance 200 pF PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT VCM Common mode voltage range RRI = 0x0 -0.1 VDD–1 V RRI = 0x1 1 VDD-0.2 RRI = 0x2 -0.1 VDD-0.2 Iq Quiescent current, per op-amp IO= 0 mA, RRI = 0x0 97 µA IO= 0 mA, RRI = 0x1 or 0x2 93 GBW Gain-bandwidth product CL = 200pF 0.32 MHz VOS Input offset voltage Noninverting, unity gain, TA = 25℃, VDD = 3.3V CHOPCLKMODE = 0x0 ±0.2 ±6.5 mV CHOPCLKMODE = 0x1 ±0.08 ±0.4 dVOS/dT Input offset voltage temperature drift Noninverting, unity gain CHOPCLKMODE = 0x0 7.7 µV/°C CHOPCLKMODE = 0x1 0.34 Ibias Input bias for muxed I/O pin at SoC 0.1V<Vin<VDD-0.3V, VDD=3.3V, CHOPCLKMODE=0x0 TA = 25°C ±40 pA TA = 125°C ±4000 0.1V<Vin<VDD-0.3V, VDD=3.3V, CHOPCLKMODE=0x1 TA = 25°C ±200 TA = 125°C ±4000 CMRRDC Common mode rejection ratio, DC Over common mode voltage range CHOPCLKMODE = 0x0 48 77 dB CHOPCLKMODE = 0x1 56 105 en Input voltage noise density Noninverting, unity gain f = 1 kHz 43 nV/√Hz f = 10 kHz 19 Rin Input resistance #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376816/SF.OB27_BQRM_SF1 0.65 kΩ Cin Input capacitance Common mode 4 pF Differential 2 AOL Open-loop voltage gain, DC RL = 350 kΩ, 0.3 < Vo < VDD-0.3 82 90 107 dB PM phase margin CL = 200 pF, RL= 350 kΩ 69 70 72 degree SR Slew rate Noninverting, unity gain, CL = 40 pF 0.32 V/µs THDN Total Harmonic Distortion + Noise 0.012 % ILoad Output load current ±4 mA CLoad Output load capacitance 200 pF VCM Common mode voltage range RRI = 0x0 -0.1 VDD–1 V VCM CMCommon mode voltage rangeRRI = 0x0-0.1VDD–1V RRI = 0x1 1 VDD-0.2 RRI = 0x11VDD-0.2 RRI = 0x2 -0.1 VDD-0.2 RRI = 0x2-0.1VDD-0.2 Iq Quiescent current, per op-amp IO= 0 mA, RRI = 0x0 97 µA Iq qQuiescent current, per op-ampIO= 0 mA, RRI = 0x0O97µA IO= 0 mA, RRI = 0x1 or 0x2 93 IO= 0 mA, RRI = 0x1 or 0x2O93 GBW Gain-bandwidth product CL = 200pF 0.32 MHz GBWGain-bandwidth productCL = 200pFL0.32MHz VOS Input offset voltage Noninverting, unity gain, TA = 25℃, VDD = 3.3V CHOPCLKMODE = 0x0 ±0.2 ±6.5 mV VOS OSInput offset voltageNoninverting, unity gain, TA = 25℃, VDD = 3.3VACHOPCLKMODE = 0x0±0.2±6.5mV CHOPCLKMODE = 0x1 ±0.08 ±0.4 CHOPCLKMODE = 0x1±0.08±0.4 dVOS/dT Input offset voltage temperature drift Noninverting, unity gain CHOPCLKMODE = 0x0 7.7 µV/°C dVOS/dTOSInput offset voltage temperature driftNoninverting, unity gainCHOPCLKMODE = 0x07.7µV/°C CHOPCLKMODE = 0x1 0.34 CHOPCLKMODE = 0x10.34 Ibias Input bias for muxed I/O pin at SoC 0.1V<Vin<VDD-0.3V, VDD=3.3V, CHOPCLKMODE=0x0 TA = 25°C ±40 pA Ibias biasInput bias for muxed I/O pin at SoC 0.1V<Vin<VDD-0.3V, VDD=3.3V, CHOPCLKMODE=0x0inTA = 25°CA±40pA TA = 125°C ±4000 TA = 125°CA±4000 0.1V<Vin<VDD-0.3V, VDD=3.3V, CHOPCLKMODE=0x1 TA = 25°C ±200 0.1V<Vin<VDD-0.3V, VDD=3.3V, CHOPCLKMODE=0x1inTA = 25°CA±200 TA = 125°C ±4000 TA = 125°CA±4000 CMRRDC Common mode rejection ratio, DC Over common mode voltage range CHOPCLKMODE = 0x0 48 77 dB CMRRDC DCCommon mode rejection ratio, DCOver common mode voltage rangeCHOPCLKMODE = 0x04877dB CHOPCLKMODE = 0x1 56 105 CHOPCLKMODE = 0x156105 en Input voltage noise density Noninverting, unity gain f = 1 kHz 43 nV/√Hz en nInput voltage noise densityNoninverting, unity gainf = 1 kHz43nV/√Hz Hz f = 10 kHz 19 f = 10 kHz19 Rin Input resistance #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376816/SF.OB27_BQRM_SF1 0.65 kΩ Rin inInput resistance #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376816/SF.OB27_BQRM_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376816/SF.OB27_BQRM_SF1 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376816/SF.OB27_BQRM_SF10.65kΩ Cin Input capacitance Common mode 4 pF Cin inInput capacitanceCommon mode4pF Differential 2 Differential2 AOL Open-loop voltage gain, DC RL = 350 kΩ, 0.3 < Vo < VDD-0.3 82 90 107 dB AOL OLOpen-loop voltage gain, DCRL = 350 kΩ, 0.3 < Vo < VDD-0.3L8290107dB PM phase margin CL = 200 pF, RL= 350 kΩ 69 70 72 degree PMphase marginCL = 200 pF, RL= 350 kΩLL697072degree SR Slew rate Noninverting, unity gain, CL = 40 pF 0.32 V/µs SRSlew rateNoninverting, unity gain, CL = 40 pFL0.32V/µs THDN Total Harmonic Distortion + Noise 0.012 % THDNTotal Harmonic Distortion + Noise0.012% ILoad Output load current ±4 mA ILoad LoadOutput load current±4mA CLoad Output load capacitance 200 pF CLoad LoadOutput load capacitance200pF The term 'Rin' refers to the input resistance of the multiplexer (mux) in the GPAMP. The term 'Rin' refers to the input resistance of the multiplexer (mux) in the GPAMP. Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tEN GPAMP enable time ENABLE = 0x0 to 0x1, Bandgap reference ON, 0.1% Noninverting, unity gain 12 20 µs tdisable GPAMP disable time 4 ULPCLK Cycles tSETTLE GPAMP settling time CL = 200 pF, Vstep = 0.3V to VDD - 0.3V, 0.1%, ENABLE = 0x1 Noninverting, unity gain 9 µs Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tEN GPAMP enable time ENABLE = 0x0 to 0x1, Bandgap reference ON, 0.1% Noninverting, unity gain 12 20 µs tdisable GPAMP disable time 4 ULPCLK Cycles tSETTLE GPAMP settling time CL = 200 pF, Vstep = 0.3V to VDD - 0.3V, 0.1%, ENABLE = 0x1 Noninverting, unity gain 9 µs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tEN GPAMP enable time ENABLE = 0x0 to 0x1, Bandgap reference ON, 0.1% Noninverting, unity gain 12 20 µs tdisable GPAMP disable time 4 ULPCLK Cycles tSETTLE GPAMP settling time CL = 200 pF, Vstep = 0.3V to VDD - 0.3V, 0.1%, ENABLE = 0x1 Noninverting, unity gain 9 µs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tEN GPAMP enable time ENABLE = 0x0 to 0x1, Bandgap reference ON, 0.1% Noninverting, unity gain 12 20 µs tdisable GPAMP disable time 4 ULPCLK Cycles tSETTLE GPAMP settling time CL = 200 pF, Vstep = 0.3V to VDD - 0.3V, 0.1%, ENABLE = 0x1 Noninverting, unity gain 9 µs PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT tEN GPAMP enable time ENABLE = 0x0 to 0x1, Bandgap reference ON, 0.1% Noninverting, unity gain 12 20 µs tdisable GPAMP disable time 4 ULPCLK Cycles tSETTLE GPAMP settling time CL = 200 pF, Vstep = 0.3V to VDD - 0.3V, 0.1%, ENABLE = 0x1 Noninverting, unity gain 9 µs tEN GPAMP enable time ENABLE = 0x0 to 0x1, Bandgap reference ON, 0.1% Noninverting, unity gain 12 20 µs tEN ENGPAMP enable timeENABLE = 0x0 to 0x1, Bandgap reference ON, 0.1%Noninverting, unity gain1220µs tdisable GPAMP disable time 4 ULPCLK Cycles tdisable disableGPAMP disable time4ULPCLK Cycles tSETTLE GPAMP settling time CL = 200 pF, Vstep = 0.3V to VDD - 0.3V, 0.1%, ENABLE = 0x1 Noninverting, unity gain 9 µs tSETTLE SETTLEGPAMP settling timeCL = 200 pF, Vstep = 0.3V to VDD - 0.3V, 0.1%, ENABLE = 0x1LNoninverting, unity gain9µs OPA Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCM Common mode voltage range RRI = 0x0 -0.1 VDD-1.1 V RRI = 0x1 -0.1 VDD-0.3 VO Voltage output swing from rail range RL = 10kΩ connected to VDD/2 20 68 mV Iq Quiescent current, per op-amp #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376800/SFNBH0LJNI8Z IO= 0mA, RRI = 0x0 GBW = 0x0 100 µA GBW = 0x1 350 IO= 0mA, RRI = 0x1 GBW = 0x0 140 170 GBW = 0x1 450 600 IBCS Burn-out current source current 2 µA GBW Gain-bandwidth product Noninverting, unity gain,CL = 40 pF GBW = 0x0 1.5 MHz GBW = 0x1 6 VOS Input offset voltage Noninverting, unity gain, VDD = 3.3V, TA = 25°C CHOP = 0x0 ±0.4 ±2 mV CHOP = 0x1 or 0x2 ±0.3 Noninverting, unity gain, VDD = 3.3V CHOP = 0x0 ±1.5 ±3.5 CHOP = 0x1 or 0x2 ±0.1 ±0.5 dVOS/dT Input offset voltage temperature drift Noninverting, unity gain, CHOP = 0x0 GBW = 0x0 ±8.5 µV/°C GBW = 0x1 ±6 Noninverting, unity gain, CHOP = 0x1 or 0x2 ±0.5 PSRRDC Power Supply Rejection Ratio, DC Noninverting, unity gain CHOP = 0x0 74 86 dB CHOP = 0x1 or 0x2 74 86 Ibias Input bias current for dedicated OPA input pin 0.1V<Vin<VDD-0.3V, VDD = 3.3V, CHOP=0x0 TA = 25°C ±6 pA TA = 125°C ±0.35 ±0.4 nA 0.1V<Vin<VDD-0.3V, VDD = 3.3V, CHOP=0x1 TA = 25°C ±0.4 nA TA = 125°C ±0.4 ±0.5 nA CMRRDC Common mode rejection ratio, DC RRI = 0x0: 0V<VCM<VDD-1.1VRRI = 0x1: 0V<VCM<VDD-0.3V CHOP = 0x0 89 dB CHOP = 0x1 or 0x2 73 102 en Input voltage noise density GBW = 0x0, Noninverting, unity gain, CHOP = 0x0 f = 1kHz 240 nV/√Hz f = 10kHz 88 Rin Input resistance #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376800/SFN2NS4M4XOF 2.6 kΩ Cin Input capacitance Common mode 3 pF AOL Open-loop voltage gain, DC RL = 20kΩ to GND, 0.3<Vo<VDD-0.3 105 dB PM phase margin CL = 40pF GBW = 0x0 57 degree GBW = 0x1 50 SR Slew rate Noninverting, unity gain, CL = 40 pF GBW = 0x0 1.3 V/µs GBW = 0x1 4.9 THDN Total harmonic distortion + noise Noninverting, unity gain, GBW = 0x0, f = 1.5kHz, Integration BW = 100kHz 0.0034 % Noninverting, unity gain, GBW = 0x1, f = 6kHz, Integration BW = 100kHz 0.004 ILoad Short circuit current GBW = 0x0, TA = 25°C ±9 mA GBW = 0x1, TA = 25°C ±30 CLoad Output load capacitance 40 pF Rin here means the input resistance of mux in OPA. Excluding VBOOST current. VBOOST must be enabled when OPA is enabled. Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tEN OPA enable time ENABLE = 0x0 to 0x1, Bandgap reference ON, 0.1%, Noninverting, unity gain GBW = 0x0 7.3 12 µs GBW = 0x1 4.4 6 tdisable OPA disable time 4 ULPCLK cycles fCHOP OPA Chopping Frequency CHOP = 0x1 GAIN = 0x0 125 kHz GAIN = 0x1 62.5 GAIN = 0x2 31.25 GAIN = 0x3 15.625 GAIN = 0x4 7.8 GAIN = 0x5 3.9 tSETTLE OPA settling time CL = 40 pF, Vstep = 0.3V to VDD-0.3V, 0.1%, ENABLE = 0x1, Noninverting, unity gain GBW = 0x0 2.5 9 µs GBW = 0x1 1.3 5 PGA Mode over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT G Non- inverting gain accuracy Buffer Mode #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376802/SFSHW.CA2PDZ Unity Gain -0.05 +0.05 % GAIN = 0x1 Gain of 2 -0.6 +0.6 % GAIN = 0x2 Gain of 4 –0.8 +0.8 GAIN = 0x3 Gain of 8 –1 +1 GAIN = 0x4 Gain of 16 –1.5 1.5 GAIN = 0x5 Gain of 32 –2.6 +2.6 Inverting gain accuracy GAIN = 0x1 Gain of -1 –0.8 +0.8 GAIN = 0x2 Gain of -3 –1.0 +1.0 GAIN = 0x3 Gain of -7 –1.2 1.2 GAIN = 0x4 Gain of -15 –1.5 1.5 GAIN = 0x5 Gain of -31 –2.7 2.7 RPGA Programmable gain stage resistance GAIN = 0x1 R1 64 kΩ R2 (feedback resistor) 64 GAIN = 0x2 R1 32 R2 (feedback resistor) 96 GAIN = 0x3 R1 16 R2 (feedback resistor) 112 GAIN = 0x4 R1 8 R2 (feedback resistor) 120 GAIN = 0x5 R1 4 R2 (feedback resistor) 124 G/dV Gain supply drift 0.026 0.84 %/V G/dT Gain temperature drift 0.0007 0.014 %/C THD Total harmonic distortion f = 3kHz, RL = 1.5kOhm to VDD/2, GBW = 0x1, GAIN = 0x1 88 dB f = 188Hz, RL = 1.5kOhm to VDD/2, GBW = 0x1, GAIN = 0x5 61 OPA operates with unity gain in buffer mode, providing impedance matching and signal buffering without the amplification. OPA OPA Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCM Common mode voltage range RRI = 0x0 -0.1 VDD-1.1 V RRI = 0x1 -0.1 VDD-0.3 VO Voltage output swing from rail range RL = 10kΩ connected to VDD/2 20 68 mV Iq Quiescent current, per op-amp #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376800/SFNBH0LJNI8Z IO= 0mA, RRI = 0x0 GBW = 0x0 100 µA GBW = 0x1 350 IO= 0mA, RRI = 0x1 GBW = 0x0 140 170 GBW = 0x1 450 600 IBCS Burn-out current source current 2 µA GBW Gain-bandwidth product Noninverting, unity gain,CL = 40 pF GBW = 0x0 1.5 MHz GBW = 0x1 6 VOS Input offset voltage Noninverting, unity gain, VDD = 3.3V, TA = 25°C CHOP = 0x0 ±0.4 ±2 mV CHOP = 0x1 or 0x2 ±0.3 Noninverting, unity gain, VDD = 3.3V CHOP = 0x0 ±1.5 ±3.5 CHOP = 0x1 or 0x2 ±0.1 ±0.5 dVOS/dT Input offset voltage temperature drift Noninverting, unity gain, CHOP = 0x0 GBW = 0x0 ±8.5 µV/°C GBW = 0x1 ±6 Noninverting, unity gain, CHOP = 0x1 or 0x2 ±0.5 PSRRDC Power Supply Rejection Ratio, DC Noninverting, unity gain CHOP = 0x0 74 86 dB CHOP = 0x1 or 0x2 74 86 Ibias Input bias current for dedicated OPA input pin 0.1V<Vin<VDD-0.3V, VDD = 3.3V, CHOP=0x0 TA = 25°C ±6 pA TA = 125°C ±0.35 ±0.4 nA 0.1V<Vin<VDD-0.3V, VDD = 3.3V, CHOP=0x1 TA = 25°C ±0.4 nA TA = 125°C ±0.4 ±0.5 nA CMRRDC Common mode rejection ratio, DC RRI = 0x0: 0V<VCM<VDD-1.1VRRI = 0x1: 0V<VCM<VDD-0.3V CHOP = 0x0 89 dB CHOP = 0x1 or 0x2 73 102 en Input voltage noise density GBW = 0x0, Noninverting, unity gain, CHOP = 0x0 f = 1kHz 240 nV/√Hz f = 10kHz 88 Rin Input resistance #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376800/SFN2NS4M4XOF 2.6 kΩ Cin Input capacitance Common mode 3 pF AOL Open-loop voltage gain, DC RL = 20kΩ to GND, 0.3<Vo<VDD-0.3 105 dB PM phase margin CL = 40pF GBW = 0x0 57 degree GBW = 0x1 50 SR Slew rate Noninverting, unity gain, CL = 40 pF GBW = 0x0 1.3 V/µs GBW = 0x1 4.9 THDN Total harmonic distortion + noise Noninverting, unity gain, GBW = 0x0, f = 1.5kHz, Integration BW = 100kHz 0.0034 % Noninverting, unity gain, GBW = 0x1, f = 6kHz, Integration BW = 100kHz 0.004 ILoad Short circuit current GBW = 0x0, TA = 25°C ±9 mA GBW = 0x1, TA = 25°C ±30 CLoad Output load capacitance 40 pF Rin here means the input resistance of mux in OPA. Excluding VBOOST current. VBOOST must be enabled when OPA is enabled. Electrical Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCM Common mode voltage range RRI = 0x0 -0.1 VDD-1.1 V RRI = 0x1 -0.1 VDD-0.3 VO Voltage output swing from rail range RL = 10kΩ connected to VDD/2 20 68 mV Iq Quiescent current, per op-amp #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376800/SFNBH0LJNI8Z IO= 0mA, RRI = 0x0 GBW = 0x0 100 µA GBW = 0x1 350 IO= 0mA, RRI = 0x1 GBW = 0x0 140 170 GBW = 0x1 450 600 IBCS Burn-out current source current 2 µA GBW Gain-bandwidth product Noninverting, unity gain,CL = 40 pF GBW = 0x0 1.5 MHz GBW = 0x1 6 VOS Input offset voltage Noninverting, unity gain, VDD = 3.3V, TA = 25°C CHOP = 0x0 ±0.4 ±2 mV CHOP = 0x1 or 0x2 ±0.3 Noninverting, unity gain, VDD = 3.3V CHOP = 0x0 ±1.5 ±3.5 CHOP = 0x1 or 0x2 ±0.1 ±0.5 dVOS/dT Input offset voltage temperature drift Noninverting, unity gain, CHOP = 0x0 GBW = 0x0 ±8.5 µV/°C GBW = 0x1 ±6 Noninverting, unity gain, CHOP = 0x1 or 0x2 ±0.5 PSRRDC Power Supply Rejection Ratio, DC Noninverting, unity gain CHOP = 0x0 74 86 dB CHOP = 0x1 or 0x2 74 86 Ibias Input bias current for dedicated OPA input pin 0.1V<Vin<VDD-0.3V, VDD = 3.3V, CHOP=0x0 TA = 25°C ±6 pA TA = 125°C ±0.35 ±0.4 nA 0.1V<Vin<VDD-0.3V, VDD = 3.3V, CHOP=0x1 TA = 25°C ±0.4 nA TA = 125°C ±0.4 ±0.5 nA CMRRDC Common mode rejection ratio, DC RRI = 0x0: 0V<VCM<VDD-1.1VRRI = 0x1: 0V<VCM<VDD-0.3V CHOP = 0x0 89 dB CHOP = 0x1 or 0x2 73 102 en Input voltage noise density GBW = 0x0, Noninverting, unity gain, CHOP = 0x0 f = 1kHz 240 nV/√Hz f = 10kHz 88 Rin Input resistance #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376800/SFN2NS4M4XOF 2.6 kΩ Cin Input capacitance Common mode 3 pF AOL Open-loop voltage gain, DC RL = 20kΩ to GND, 0.3<Vo<VDD-0.3 105 dB PM phase margin CL = 40pF GBW = 0x0 57 degree GBW = 0x1 50 SR Slew rate Noninverting, unity gain, CL = 40 pF GBW = 0x0 1.3 V/µs GBW = 0x1 4.9 THDN Total harmonic distortion + noise Noninverting, unity gain, GBW = 0x0, f = 1.5kHz, Integration BW = 100kHz 0.0034 % Noninverting, unity gain, GBW = 0x1, f = 6kHz, Integration BW = 100kHz 0.004 ILoad Short circuit current GBW = 0x0, TA = 25°C ±9 mA GBW = 0x1, TA = 25°C ±30 CLoad Output load capacitance 40 pF Rin here means the input resistance of mux in OPA. Excluding VBOOST current. VBOOST must be enabled when OPA is enabled. over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCM Common mode voltage range RRI = 0x0 -0.1 VDD-1.1 V RRI = 0x1 -0.1 VDD-0.3 VO Voltage output swing from rail range RL = 10kΩ connected to VDD/2 20 68 mV Iq Quiescent current, per op-amp #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376800/SFNBH0LJNI8Z IO= 0mA, RRI = 0x0 GBW = 0x0 100 µA GBW = 0x1 350 IO= 0mA, RRI = 0x1 GBW = 0x0 140 170 GBW = 0x1 450 600 IBCS Burn-out current source current 2 µA GBW Gain-bandwidth product Noninverting, unity gain,CL = 40 pF GBW = 0x0 1.5 MHz GBW = 0x1 6 VOS Input offset voltage Noninverting, unity gain, VDD = 3.3V, TA = 25°C CHOP = 0x0 ±0.4 ±2 mV CHOP = 0x1 or 0x2 ±0.3 Noninverting, unity gain, VDD = 3.3V CHOP = 0x0 ±1.5 ±3.5 CHOP = 0x1 or 0x2 ±0.1 ±0.5 dVOS/dT Input offset voltage temperature drift Noninverting, unity gain, CHOP = 0x0 GBW = 0x0 ±8.5 µV/°C GBW = 0x1 ±6 Noninverting, unity gain, CHOP = 0x1 or 0x2 ±0.5 PSRRDC Power Supply Rejection Ratio, DC Noninverting, unity gain CHOP = 0x0 74 86 dB CHOP = 0x1 or 0x2 74 86 Ibias Input bias current for dedicated OPA input pin 0.1V<Vin<VDD-0.3V, VDD = 3.3V, CHOP=0x0 TA = 25°C ±6 pA TA = 125°C ±0.35 ±0.4 nA 0.1V<Vin<VDD-0.3V, VDD = 3.3V, CHOP=0x1 TA = 25°C ±0.4 nA TA = 125°C ±0.4 ±0.5 nA CMRRDC Common mode rejection ratio, DC RRI = 0x0: 0V<VCM<VDD-1.1VRRI = 0x1: 0V<VCM<VDD-0.3V CHOP = 0x0 89 dB CHOP = 0x1 or 0x2 73 102 en Input voltage noise density GBW = 0x0, Noninverting, unity gain, CHOP = 0x0 f = 1kHz 240 nV/√Hz f = 10kHz 88 Rin Input resistance #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376800/SFN2NS4M4XOF 2.6 kΩ Cin Input capacitance Common mode 3 pF AOL Open-loop voltage gain, DC RL = 20kΩ to GND, 0.3<Vo<VDD-0.3 105 dB PM phase margin CL = 40pF GBW = 0x0 57 degree GBW = 0x1 50 SR Slew rate Noninverting, unity gain, CL = 40 pF GBW = 0x0 1.3 V/µs GBW = 0x1 4.9 THDN Total harmonic distortion + noise Noninverting, unity gain, GBW = 0x0, f = 1.5kHz, Integration BW = 100kHz 0.0034 % Noninverting, unity gain, GBW = 0x1, f = 6kHz, Integration BW = 100kHz 0.004 ILoad Short circuit current GBW = 0x0, TA = 25°C ±9 mA GBW = 0x1, TA = 25°C ±30 CLoad Output load capacitance 40 pF over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCM Common mode voltage range RRI = 0x0 -0.1 VDD-1.1 V RRI = 0x1 -0.1 VDD-0.3 VO Voltage output swing from rail range RL = 10kΩ connected to VDD/2 20 68 mV Iq Quiescent current, per op-amp #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376800/SFNBH0LJNI8Z IO= 0mA, RRI = 0x0 GBW = 0x0 100 µA GBW = 0x1 350 IO= 0mA, RRI = 0x1 GBW = 0x0 140 170 GBW = 0x1 450 600 IBCS Burn-out current source current 2 µA GBW Gain-bandwidth product Noninverting, unity gain,CL = 40 pF GBW = 0x0 1.5 MHz GBW = 0x1 6 VOS Input offset voltage Noninverting, unity gain, VDD = 3.3V, TA = 25°C CHOP = 0x0 ±0.4 ±2 mV CHOP = 0x1 or 0x2 ±0.3 Noninverting, unity gain, VDD = 3.3V CHOP = 0x0 ±1.5 ±3.5 CHOP = 0x1 or 0x2 ±0.1 ±0.5 dVOS/dT Input offset voltage temperature drift Noninverting, unity gain, CHOP = 0x0 GBW = 0x0 ±8.5 µV/°C GBW = 0x1 ±6 Noninverting, unity gain, CHOP = 0x1 or 0x2 ±0.5 PSRRDC Power Supply Rejection Ratio, DC Noninverting, unity gain CHOP = 0x0 74 86 dB CHOP = 0x1 or 0x2 74 86 Ibias Input bias current for dedicated OPA input pin 0.1V<Vin<VDD-0.3V, VDD = 3.3V, CHOP=0x0 TA = 25°C ±6 pA TA = 125°C ±0.35 ±0.4 nA 0.1V<Vin<VDD-0.3V, VDD = 3.3V, CHOP=0x1 TA = 25°C ±0.4 nA TA = 125°C ±0.4 ±0.5 nA CMRRDC Common mode rejection ratio, DC RRI = 0x0: 0V<VCM<VDD-1.1VRRI = 0x1: 0V<VCM<VDD-0.3V CHOP = 0x0 89 dB CHOP = 0x1 or 0x2 73 102 en Input voltage noise density GBW = 0x0, Noninverting, unity gain, CHOP = 0x0 f = 1kHz 240 nV/√Hz f = 10kHz 88 Rin Input resistance #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376800/SFN2NS4M4XOF 2.6 kΩ Cin Input capacitance Common mode 3 pF AOL Open-loop voltage gain, DC RL = 20kΩ to GND, 0.3<Vo<VDD-0.3 105 dB PM phase margin CL = 40pF GBW = 0x0 57 degree GBW = 0x1 50 SR Slew rate Noninverting, unity gain, CL = 40 pF GBW = 0x0 1.3 V/µs GBW = 0x1 4.9 THDN Total harmonic distortion + noise Noninverting, unity gain, GBW = 0x0, f = 1.5kHz, Integration BW = 100kHz 0.0034 % Noninverting, unity gain, GBW = 0x1, f = 6kHz, Integration BW = 100kHz 0.004 ILoad Short circuit current GBW = 0x0, TA = 25°C ±9 mA GBW = 0x1, TA = 25°C ±30 CLoad Output load capacitance 40 pF PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT VCM Common mode voltage range RRI = 0x0 -0.1 VDD-1.1 V RRI = 0x1 -0.1 VDD-0.3 VO Voltage output swing from rail range RL = 10kΩ connected to VDD/2 20 68 mV Iq Quiescent current, per op-amp #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376800/SFNBH0LJNI8Z IO= 0mA, RRI = 0x0 GBW = 0x0 100 µA GBW = 0x1 350 IO= 0mA, RRI = 0x1 GBW = 0x0 140 170 GBW = 0x1 450 600 IBCS Burn-out current source current 2 µA GBW Gain-bandwidth product Noninverting, unity gain,CL = 40 pF GBW = 0x0 1.5 MHz GBW = 0x1 6 VOS Input offset voltage Noninverting, unity gain, VDD = 3.3V, TA = 25°C CHOP = 0x0 ±0.4 ±2 mV CHOP = 0x1 or 0x2 ±0.3 Noninverting, unity gain, VDD = 3.3V CHOP = 0x0 ±1.5 ±3.5 CHOP = 0x1 or 0x2 ±0.1 ±0.5 dVOS/dT Input offset voltage temperature drift Noninverting, unity gain, CHOP = 0x0 GBW = 0x0 ±8.5 µV/°C GBW = 0x1 ±6 Noninverting, unity gain, CHOP = 0x1 or 0x2 ±0.5 PSRRDC Power Supply Rejection Ratio, DC Noninverting, unity gain CHOP = 0x0 74 86 dB CHOP = 0x1 or 0x2 74 86 Ibias Input bias current for dedicated OPA input pin 0.1V<Vin<VDD-0.3V, VDD = 3.3V, CHOP=0x0 TA = 25°C ±6 pA TA = 125°C ±0.35 ±0.4 nA 0.1V<Vin<VDD-0.3V, VDD = 3.3V, CHOP=0x1 TA = 25°C ±0.4 nA TA = 125°C ±0.4 ±0.5 nA CMRRDC Common mode rejection ratio, DC RRI = 0x0: 0V<VCM<VDD-1.1VRRI = 0x1: 0V<VCM<VDD-0.3V CHOP = 0x0 89 dB CHOP = 0x1 or 0x2 73 102 en Input voltage noise density GBW = 0x0, Noninverting, unity gain, CHOP = 0x0 f = 1kHz 240 nV/√Hz f = 10kHz 88 Rin Input resistance #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376800/SFN2NS4M4XOF 2.6 kΩ Cin Input capacitance Common mode 3 pF AOL Open-loop voltage gain, DC RL = 20kΩ to GND, 0.3<Vo<VDD-0.3 105 dB PM phase margin CL = 40pF GBW = 0x0 57 degree GBW = 0x1 50 SR Slew rate Noninverting, unity gain, CL = 40 pF GBW = 0x0 1.3 V/µs GBW = 0x1 4.9 THDN Total harmonic distortion + noise Noninverting, unity gain, GBW = 0x0, f = 1.5kHz, Integration BW = 100kHz 0.0034 % Noninverting, unity gain, GBW = 0x1, f = 6kHz, Integration BW = 100kHz 0.004 ILoad Short circuit current GBW = 0x0, TA = 25°C ±9 mA GBW = 0x1, TA = 25°C ±30 CLoad Output load capacitance 40 pF VCM Common mode voltage range RRI = 0x0 -0.1 VDD-1.1 V VCM CMCommon mode voltage rangeRRI = 0x0-0.1VDD-1.1V RRI = 0x1 -0.1 VDD-0.3 RRI = 0x1-0.1VDD-0.3 VO Voltage output swing from rail range RL = 10kΩ connected to VDD/2 20 68 mV VO OVoltage output swing from rail rangeRL = 10kΩ connected to VDD/2L2068mV Iq Quiescent current, per op-amp #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376800/SFNBH0LJNI8Z IO= 0mA, RRI = 0x0 GBW = 0x0 100 µA Iq qQuiescent current, per op-amp #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376800/SFNBH0LJNI8Z #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376800/SFNBH0LJNI8ZIO= 0mA, RRI = 0x0OGBW = 0x0100µA GBW = 0x1 350 GBW = 0x1350 IO= 0mA, RRI = 0x1 GBW = 0x0 140 170 IO= 0mA, RRI = 0x1OGBW = 0x0140170 GBW = 0x1 450 600 GBW = 0x1450600 IBCS Burn-out current source current 2 µA IBCS BCSBurn-out current source current 2µA GBW Gain-bandwidth product Noninverting, unity gain,CL = 40 pF GBW = 0x0 1.5 MHz GBWGain-bandwidth productNoninverting, unity gain,CL = 40 pFLGBW = 0x01.5MHz GBW = 0x1 6 GBW = 0x16 VOS Input offset voltage Noninverting, unity gain, VDD = 3.3V, TA = 25°C CHOP = 0x0 ±0.4 ±2 mV VOS OSInput offset voltageNoninverting, unity gain, VDD = 3.3V, TA = 25°CACHOP = 0x0±0.4±2mV CHOP = 0x1 or 0x2 ±0.3 CHOP = 0x1 or 0x2±0.3 Noninverting, unity gain, VDD = 3.3V CHOP = 0x0 ±1.5 ±3.5 Noninverting, unity gain, VDD = 3.3VCHOP = 0x0±1.5±3.5 CHOP = 0x1 or 0x2 ±0.1 ±0.5 CHOP = 0x1 or 0x2±0.1±0.5 dVOS/dT Input offset voltage temperature drift Noninverting, unity gain, CHOP = 0x0 GBW = 0x0 ±8.5 µV/°C dVOS/dTOSInput offset voltage temperature driftNoninverting, unity gain, CHOP = 0x0GBW = 0x0±8.5µV/°C GBW = 0x1 ±6 GBW = 0x1±6 Noninverting, unity gain, CHOP = 0x1 or 0x2 ±0.5 Noninverting, unity gain, CHOP = 0x1 or 0x2±0.5 PSRRDC Power Supply Rejection Ratio, DC Noninverting, unity gain CHOP = 0x0 74 86 dB PSRRDC DCPower Supply Rejection Ratio, DCNoninverting, unity gainCHOP = 0x07486dB CHOP = 0x1 or 0x2 74 86 CHOP = 0x1 or 0x27486 Ibias Input bias current for dedicated OPA input pin 0.1V<Vin<VDD-0.3V, VDD = 3.3V, CHOP=0x0 TA = 25°C ±6 pA Ibias biasInput bias current for dedicated OPA input pin 0.1V<Vin<VDD-0.3V, VDD = 3.3V, CHOP=0x0inTA = 25°CA±6pA TA = 125°C ±0.35 ±0.4 nA TA = 125°CA±0.35±0.4nA 0.1V<Vin<VDD-0.3V, VDD = 3.3V, CHOP=0x1 TA = 25°C ±0.4 nA 0.1V<Vin<VDD-0.3V, VDD = 3.3V, CHOP=0x1inTA = 25°CA±0.4nA TA = 125°C ±0.4 ±0.5 nA TA = 125°CA±0.4±0.5nA CMRRDC Common mode rejection ratio, DC RRI = 0x0: 0V<VCM<VDD-1.1VRRI = 0x1: 0V<VCM<VDD-0.3V CHOP = 0x0 89 dB CMRRDC DCCommon mode rejection ratio, DCRRI = 0x0: 0V<VCM<VDD-1.1VRRI = 0x1: 0V<VCM<VDD-0.3VCMCMCHOP = 0x089dB CHOP = 0x1 or 0x2 73 102 CHOP = 0x1 or 0x273102 en Input voltage noise density GBW = 0x0, Noninverting, unity gain, CHOP = 0x0 f = 1kHz 240 nV/√Hz en nInput voltage noise densityGBW = 0x0, Noninverting, unity gain, CHOP = 0x0f = 1kHz240nV/√Hz Hz f = 10kHz 88 f = 10kHz88 Rin Input resistance #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376800/SFN2NS4M4XOF 2.6 kΩ Rin inInput resistance #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376800/SFN2NS4M4XOF #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376800/SFN2NS4M4XOF2.6kΩ Cin Input capacitance Common mode 3 pF Cin inInput capacitanceCommon mode3pF AOL Open-loop voltage gain, DC RL = 20kΩ to GND, 0.3<Vo<VDD-0.3 105 dB AOL OLOpen-loop voltage gain, DCRL = 20kΩ to GND, 0.3<Vo<VDD-0.3L105dB PM phase margin CL = 40pF GBW = 0x0 57 degree PMphase marginCL = 40pFLGBW = 0x057degree GBW = 0x1 50 GBW = 0x150 SR Slew rate Noninverting, unity gain, CL = 40 pF GBW = 0x0 1.3 V/µs SRSlew rateNoninverting, unity gain, CL = 40 pFLGBW = 0x01.3V/µs GBW = 0x1 4.9 GBW = 0x14.9 THDN Total harmonic distortion + noise Noninverting, unity gain, GBW = 0x0, f = 1.5kHz, Integration BW = 100kHz 0.0034 % THDNTotal harmonic distortion + noiseNoninverting, unity gain, GBW = 0x0, f = 1.5kHz, Integration BW = 100kHz0.0034% Noninverting, unity gain, GBW = 0x1, f = 6kHz, Integration BW = 100kHz 0.004 Noninverting, unity gain, GBW = 0x1, f = 6kHz, Integration BW = 100kHz0.004 ILoad Short circuit current GBW = 0x0, TA = 25°C ±9 mA ILoad LoadShort circuit currentGBW = 0x0, TA = 25°CA±9mA GBW = 0x1, TA = 25°C ±30 GBW = 0x1, TA = 25°CA±30 CLoad Output load capacitance 40 pF CLoad LoadOutput load capacitance40pF Rin here means the input resistance of mux in OPA. Excluding VBOOST current. VBOOST must be enabled when OPA is enabled. Rin here means the input resistance of mux in OPA.inExcluding VBOOST current. VBOOST must be enabled when OPA is enabled. Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tEN OPA enable time ENABLE = 0x0 to 0x1, Bandgap reference ON, 0.1%, Noninverting, unity gain GBW = 0x0 7.3 12 µs GBW = 0x1 4.4 6 tdisable OPA disable time 4 ULPCLK cycles fCHOP OPA Chopping Frequency CHOP = 0x1 GAIN = 0x0 125 kHz GAIN = 0x1 62.5 GAIN = 0x2 31.25 GAIN = 0x3 15.625 GAIN = 0x4 7.8 GAIN = 0x5 3.9 tSETTLE OPA settling time CL = 40 pF, Vstep = 0.3V to VDD-0.3V, 0.1%, ENABLE = 0x1, Noninverting, unity gain GBW = 0x0 2.5 9 µs GBW = 0x1 1.3 5 Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tEN OPA enable time ENABLE = 0x0 to 0x1, Bandgap reference ON, 0.1%, Noninverting, unity gain GBW = 0x0 7.3 12 µs GBW = 0x1 4.4 6 tdisable OPA disable time 4 ULPCLK cycles fCHOP OPA Chopping Frequency CHOP = 0x1 GAIN = 0x0 125 kHz GAIN = 0x1 62.5 GAIN = 0x2 31.25 GAIN = 0x3 15.625 GAIN = 0x4 7.8 GAIN = 0x5 3.9 tSETTLE OPA settling time CL = 40 pF, Vstep = 0.3V to VDD-0.3V, 0.1%, ENABLE = 0x1, Noninverting, unity gain GBW = 0x0 2.5 9 µs GBW = 0x1 1.3 5 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tEN OPA enable time ENABLE = 0x0 to 0x1, Bandgap reference ON, 0.1%, Noninverting, unity gain GBW = 0x0 7.3 12 µs GBW = 0x1 4.4 6 tdisable OPA disable time 4 ULPCLK cycles fCHOP OPA Chopping Frequency CHOP = 0x1 GAIN = 0x0 125 kHz GAIN = 0x1 62.5 GAIN = 0x2 31.25 GAIN = 0x3 15.625 GAIN = 0x4 7.8 GAIN = 0x5 3.9 tSETTLE OPA settling time CL = 40 pF, Vstep = 0.3V to VDD-0.3V, 0.1%, ENABLE = 0x1, Noninverting, unity gain GBW = 0x0 2.5 9 µs GBW = 0x1 1.3 5 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tEN OPA enable time ENABLE = 0x0 to 0x1, Bandgap reference ON, 0.1%, Noninverting, unity gain GBW = 0x0 7.3 12 µs GBW = 0x1 4.4 6 tdisable OPA disable time 4 ULPCLK cycles fCHOP OPA Chopping Frequency CHOP = 0x1 GAIN = 0x0 125 kHz GAIN = 0x1 62.5 GAIN = 0x2 31.25 GAIN = 0x3 15.625 GAIN = 0x4 7.8 GAIN = 0x5 3.9 tSETTLE OPA settling time CL = 40 pF, Vstep = 0.3V to VDD-0.3V, 0.1%, ENABLE = 0x1, Noninverting, unity gain GBW = 0x0 2.5 9 µs GBW = 0x1 1.3 5 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT tEN OPA enable time ENABLE = 0x0 to 0x1, Bandgap reference ON, 0.1%, Noninverting, unity gain GBW = 0x0 7.3 12 µs GBW = 0x1 4.4 6 tdisable OPA disable time 4 ULPCLK cycles fCHOP OPA Chopping Frequency CHOP = 0x1 GAIN = 0x0 125 kHz GAIN = 0x1 62.5 GAIN = 0x2 31.25 GAIN = 0x3 15.625 GAIN = 0x4 7.8 GAIN = 0x5 3.9 tSETTLE OPA settling time CL = 40 pF, Vstep = 0.3V to VDD-0.3V, 0.1%, ENABLE = 0x1, Noninverting, unity gain GBW = 0x0 2.5 9 µs GBW = 0x1 1.3 5 tEN OPA enable time ENABLE = 0x0 to 0x1, Bandgap reference ON, 0.1%, Noninverting, unity gain GBW = 0x0 7.3 12 µs tEN ENOPA enable timeENABLE = 0x0 to 0x1, Bandgap reference ON, 0.1%, Noninverting, unity gainGBW = 0x07.312µs GBW = 0x1 4.4 6 GBW = 0x14.46 tdisable OPA disable time 4 ULPCLK cycles tdisable disableOPA disable time4ULPCLK cycles fCHOP OPA Chopping Frequency CHOP = 0x1 GAIN = 0x0 125 kHz fCHOP CHOPOPA Chopping FrequencyCHOP = 0x1GAIN = 0x0125kHz GAIN = 0x1 62.5 GAIN = 0x162.5 GAIN = 0x2 31.25 GAIN = 0x231.25 GAIN = 0x3 15.625 GAIN = 0x315.625 GAIN = 0x4 7.8 GAIN = 0x47.8 GAIN = 0x5 3.9 GAIN = 0x53.9 tSETTLE OPA settling time CL = 40 pF, Vstep = 0.3V to VDD-0.3V, 0.1%, ENABLE = 0x1, Noninverting, unity gain GBW = 0x0 2.5 9 µs tSETTLE SETTLEOPA settling timeCL = 40 pF, Vstep = 0.3V to VDD-0.3V, 0.1%, ENABLE = 0x1, Noninverting, unity gainLGBW = 0x02.59µs GBW = 0x1 1.3 5 GBW = 0x11.35 PGA Mode over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT G Non- inverting gain accuracy Buffer Mode #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376802/SFSHW.CA2PDZ Unity Gain -0.05 +0.05 % GAIN = 0x1 Gain of 2 -0.6 +0.6 % GAIN = 0x2 Gain of 4 –0.8 +0.8 GAIN = 0x3 Gain of 8 –1 +1 GAIN = 0x4 Gain of 16 –1.5 1.5 GAIN = 0x5 Gain of 32 –2.6 +2.6 Inverting gain accuracy GAIN = 0x1 Gain of -1 –0.8 +0.8 GAIN = 0x2 Gain of -3 –1.0 +1.0 GAIN = 0x3 Gain of -7 –1.2 1.2 GAIN = 0x4 Gain of -15 –1.5 1.5 GAIN = 0x5 Gain of -31 –2.7 2.7 RPGA Programmable gain stage resistance GAIN = 0x1 R1 64 kΩ R2 (feedback resistor) 64 GAIN = 0x2 R1 32 R2 (feedback resistor) 96 GAIN = 0x3 R1 16 R2 (feedback resistor) 112 GAIN = 0x4 R1 8 R2 (feedback resistor) 120 GAIN = 0x5 R1 4 R2 (feedback resistor) 124 G/dV Gain supply drift 0.026 0.84 %/V G/dT Gain temperature drift 0.0007 0.014 %/C THD Total harmonic distortion f = 3kHz, RL = 1.5kOhm to VDD/2, GBW = 0x1, GAIN = 0x1 88 dB f = 188Hz, RL = 1.5kOhm to VDD/2, GBW = 0x1, GAIN = 0x5 61 OPA operates with unity gain in buffer mode, providing impedance matching and signal buffering without the amplification. PGA Mode over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT G Non- inverting gain accuracy Buffer Mode #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376802/SFSHW.CA2PDZ Unity Gain -0.05 +0.05 % GAIN = 0x1 Gain of 2 -0.6 +0.6 % GAIN = 0x2 Gain of 4 –0.8 +0.8 GAIN = 0x3 Gain of 8 –1 +1 GAIN = 0x4 Gain of 16 –1.5 1.5 GAIN = 0x5 Gain of 32 –2.6 +2.6 Inverting gain accuracy GAIN = 0x1 Gain of -1 –0.8 +0.8 GAIN = 0x2 Gain of -3 –1.0 +1.0 GAIN = 0x3 Gain of -7 –1.2 1.2 GAIN = 0x4 Gain of -15 –1.5 1.5 GAIN = 0x5 Gain of -31 –2.7 2.7 RPGA Programmable gain stage resistance GAIN = 0x1 R1 64 kΩ R2 (feedback resistor) 64 GAIN = 0x2 R1 32 R2 (feedback resistor) 96 GAIN = 0x3 R1 16 R2 (feedback resistor) 112 GAIN = 0x4 R1 8 R2 (feedback resistor) 120 GAIN = 0x5 R1 4 R2 (feedback resistor) 124 G/dV Gain supply drift 0.026 0.84 %/V G/dT Gain temperature drift 0.0007 0.014 %/C THD Total harmonic distortion f = 3kHz, RL = 1.5kOhm to VDD/2, GBW = 0x1, GAIN = 0x1 88 dB f = 188Hz, RL = 1.5kOhm to VDD/2, GBW = 0x1, GAIN = 0x5 61 OPA operates with unity gain in buffer mode, providing impedance matching and signal buffering without the amplification. over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT G Non- inverting gain accuracy Buffer Mode #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376802/SFSHW.CA2PDZ Unity Gain -0.05 +0.05 % GAIN = 0x1 Gain of 2 -0.6 +0.6 % GAIN = 0x2 Gain of 4 –0.8 +0.8 GAIN = 0x3 Gain of 8 –1 +1 GAIN = 0x4 Gain of 16 –1.5 1.5 GAIN = 0x5 Gain of 32 –2.6 +2.6 Inverting gain accuracy GAIN = 0x1 Gain of -1 –0.8 +0.8 GAIN = 0x2 Gain of -3 –1.0 +1.0 GAIN = 0x3 Gain of -7 –1.2 1.2 GAIN = 0x4 Gain of -15 –1.5 1.5 GAIN = 0x5 Gain of -31 –2.7 2.7 RPGA Programmable gain stage resistance GAIN = 0x1 R1 64 kΩ R2 (feedback resistor) 64 GAIN = 0x2 R1 32 R2 (feedback resistor) 96 GAIN = 0x3 R1 16 R2 (feedback resistor) 112 GAIN = 0x4 R1 8 R2 (feedback resistor) 120 GAIN = 0x5 R1 4 R2 (feedback resistor) 124 G/dV Gain supply drift 0.026 0.84 %/V G/dT Gain temperature drift 0.0007 0.014 %/C THD Total harmonic distortion f = 3kHz, RL = 1.5kOhm to VDD/2, GBW = 0x1, GAIN = 0x1 88 dB f = 188Hz, RL = 1.5kOhm to VDD/2, GBW = 0x1, GAIN = 0x5 61 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT G Non- inverting gain accuracy Buffer Mode #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376802/SFSHW.CA2PDZ Unity Gain -0.05 +0.05 % GAIN = 0x1 Gain of 2 -0.6 +0.6 % GAIN = 0x2 Gain of 4 –0.8 +0.8 GAIN = 0x3 Gain of 8 –1 +1 GAIN = 0x4 Gain of 16 –1.5 1.5 GAIN = 0x5 Gain of 32 –2.6 +2.6 Inverting gain accuracy GAIN = 0x1 Gain of -1 –0.8 +0.8 GAIN = 0x2 Gain of -3 –1.0 +1.0 GAIN = 0x3 Gain of -7 –1.2 1.2 GAIN = 0x4 Gain of -15 –1.5 1.5 GAIN = 0x5 Gain of -31 –2.7 2.7 RPGA Programmable gain stage resistance GAIN = 0x1 R1 64 kΩ R2 (feedback resistor) 64 GAIN = 0x2 R1 32 R2 (feedback resistor) 96 GAIN = 0x3 R1 16 R2 (feedback resistor) 112 GAIN = 0x4 R1 8 R2 (feedback resistor) 120 GAIN = 0x5 R1 4 R2 (feedback resistor) 124 G/dV Gain supply drift 0.026 0.84 %/V G/dT Gain temperature drift 0.0007 0.014 %/C THD Total harmonic distortion f = 3kHz, RL = 1.5kOhm to VDD/2, GBW = 0x1, GAIN = 0x1 88 dB f = 188Hz, RL = 1.5kOhm to VDD/2, GBW = 0x1, GAIN = 0x5 61 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT G Non- inverting gain accuracy Buffer Mode #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376802/SFSHW.CA2PDZ Unity Gain -0.05 +0.05 % GAIN = 0x1 Gain of 2 -0.6 +0.6 % GAIN = 0x2 Gain of 4 –0.8 +0.8 GAIN = 0x3 Gain of 8 –1 +1 GAIN = 0x4 Gain of 16 –1.5 1.5 GAIN = 0x5 Gain of 32 –2.6 +2.6 Inverting gain accuracy GAIN = 0x1 Gain of -1 –0.8 +0.8 GAIN = 0x2 Gain of -3 –1.0 +1.0 GAIN = 0x3 Gain of -7 –1.2 1.2 GAIN = 0x4 Gain of -15 –1.5 1.5 GAIN = 0x5 Gain of -31 –2.7 2.7 RPGA Programmable gain stage resistance GAIN = 0x1 R1 64 kΩ R2 (feedback resistor) 64 GAIN = 0x2 R1 32 R2 (feedback resistor) 96 GAIN = 0x3 R1 16 R2 (feedback resistor) 112 GAIN = 0x4 R1 8 R2 (feedback resistor) 120 GAIN = 0x5 R1 4 R2 (feedback resistor) 124 G/dV Gain supply drift 0.026 0.84 %/V G/dT Gain temperature drift 0.0007 0.014 %/C THD Total harmonic distortion f = 3kHz, RL = 1.5kOhm to VDD/2, GBW = 0x1, GAIN = 0x1 88 dB f = 188Hz, RL = 1.5kOhm to VDD/2, GBW = 0x1, GAIN = 0x5 61 G Non- inverting gain accuracy Buffer Mode #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376802/SFSHW.CA2PDZ Unity Gain -0.05 +0.05 % GNon- inverting gain accuracyBuffer Mode #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376802/SFSHW.CA2PDZ #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376802/SFSHW.CA2PDZUnity Gain-0.05+0.05% GAIN = 0x1 Gain of 2 -0.6 +0.6 % GAIN = 0x1Gain of 2-0.6+0.6% GAIN = 0x2 Gain of 4 –0.8 +0.8 GAIN = 0x2Gain of 4–0.8+0.8 GAIN = 0x3 Gain of 8 –1 +1 GAIN = 0x3Gain of 8–1+1 GAIN = 0x4 Gain of 16 –1.5 1.5 GAIN = 0x4Gain of 16–1.51.5 GAIN = 0x5 Gain of 32 –2.6 +2.6 GAIN = 0x5Gain of 32–2.6+2.6 Inverting gain accuracy GAIN = 0x1 Gain of -1 –0.8 +0.8 Inverting gain accuracyGAIN = 0x1Gain of -1–0.8+0.8 GAIN = 0x2 Gain of -3 –1.0 +1.0 GAIN = 0x2Gain of -3–1.0+1.0 GAIN = 0x3 Gain of -7 –1.2 1.2 GAIN = 0x3Gain of -7–1.21.2 GAIN = 0x4 Gain of -15 –1.5 1.5 GAIN = 0x4Gain of -15–1.51.5 GAIN = 0x5 Gain of -31 –2.7 2.7 GAIN = 0x5Gain of -31–2.72.7 RPGA Programmable gain stage resistance GAIN = 0x1 R1 64 kΩ RPGA PGAProgrammable gain stage resistanceGAIN = 0x1 R164kΩ R2 (feedback resistor) 64 R2 (feedback resistor)64 GAIN = 0x2 R1 32 GAIN = 0x2 R132 R2 (feedback resistor) 96 R2 (feedback resistor)96 GAIN = 0x3 R1 16 GAIN = 0x3 R116 R2 (feedback resistor) 112 R2 (feedback resistor)112 GAIN = 0x4 R1 8 GAIN = 0x4 R18 R2 (feedback resistor) 120 R2 (feedback resistor)120 GAIN = 0x5 R1 4 GAIN = 0x5 R14 R2 (feedback resistor) 124 R2 (feedback resistor)124 G/dV Gain supply drift 0.026 0.84 %/V G/dVGain supply drift0.0260.84%/V G/dT Gain temperature drift 0.0007 0.014 %/C G/dTGain temperature drift0.00070.014%/C THD Total harmonic distortion f = 3kHz, RL = 1.5kOhm to VDD/2, GBW = 0x1, GAIN = 0x1 88 dB THDTotal harmonic distortionf = 3kHz, RL = 1.5kOhm to VDD/2, GBW = 0x1, GAIN = 0x1 L88dB f = 188Hz, RL = 1.5kOhm to VDD/2, GBW = 0x1, GAIN = 0x5 61 f = 188Hz, RL = 1.5kOhm to VDD/2, GBW = 0x1, GAIN = 0x5 L61 OPA operates with unity gain in buffer mode, providing impedance matching and signal buffering without the amplification. OPA operates with unity gain in buffer mode, providing impedance matching and signal buffering without the amplification. I2C I2C Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS Standard mode Fast mode Fast mode plus UNIT MIN MAX MIN MAX MIN MAX fI2C I2C input clock frequency I2C in Power Domain0 2 32 8 32 20 32 MHz fSCL SCL clock frequency 0.1 0.4 1 MHz tHD,STA Hold time (repeated) START 4 0.6 0.26 us tLOW Low period of the SCL clock 4.7 1.3 0.5 us tHIGH High period of the SCL clock 4 0.6 0.26 us tSU,STA Setup time for a repeated START 4.7 0.6 0.26 us tHD,DAT Data hold time 0 0 0 ns tSU,DAT Data setup time 250 100 50 ns tSU,STO Setup time for STOP 4 0.6 0.26 us tBUF Bus free time between a STOP and START condition 4.7 1.3 0.5 us tVD;DAT Data valid time 3.45 0.9 0.45 us tVD;ACK Data valid acknowledge time 3.45 0.9 0.45 us I2C Filter over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT fSP Pulse duration of spikes suppressed by input filter AGFSELx = 0 6 ns AGFSELx = 1 14 35 ns AGFSELx = 2 22 60 ns AGFSELx = 3 35 90 ns I²C Timing Diagram I2C Timing Diagram I2C I2C Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS Standard mode Fast mode Fast mode plus UNIT MIN MAX MIN MAX MIN MAX fI2C I2C input clock frequency I2C in Power Domain0 2 32 8 32 20 32 MHz fSCL SCL clock frequency 0.1 0.4 1 MHz tHD,STA Hold time (repeated) START 4 0.6 0.26 us tLOW Low period of the SCL clock 4.7 1.3 0.5 us tHIGH High period of the SCL clock 4 0.6 0.26 us tSU,STA Setup time for a repeated START 4.7 0.6 0.26 us tHD,DAT Data hold time 0 0 0 ns tSU,DAT Data setup time 250 100 50 ns tSU,STO Setup time for STOP 4 0.6 0.26 us tBUF Bus free time between a STOP and START condition 4.7 1.3 0.5 us tVD;DAT Data valid time 3.45 0.9 0.45 us tVD;ACK Data valid acknowledge time 3.45 0.9 0.45 us I2C Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS Standard mode Fast mode Fast mode plus UNIT MIN MAX MIN MAX MIN MAX fI2C I2C input clock frequency I2C in Power Domain0 2 32 8 32 20 32 MHz fSCL SCL clock frequency 0.1 0.4 1 MHz tHD,STA Hold time (repeated) START 4 0.6 0.26 us tLOW Low period of the SCL clock 4.7 1.3 0.5 us tHIGH High period of the SCL clock 4 0.6 0.26 us tSU,STA Setup time for a repeated START 4.7 0.6 0.26 us tHD,DAT Data hold time 0 0 0 ns tSU,DAT Data setup time 250 100 50 ns tSU,STO Setup time for STOP 4 0.6 0.26 us tBUF Bus free time between a STOP and START condition 4.7 1.3 0.5 us tVD;DAT Data valid time 3.45 0.9 0.45 us tVD;ACK Data valid acknowledge time 3.45 0.9 0.45 us over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS Standard mode Fast mode Fast mode plus UNIT MIN MAX MIN MAX MIN MAX fI2C I2C input clock frequency I2C in Power Domain0 2 32 8 32 20 32 MHz fSCL SCL clock frequency 0.1 0.4 1 MHz tHD,STA Hold time (repeated) START 4 0.6 0.26 us tLOW Low period of the SCL clock 4.7 1.3 0.5 us tHIGH High period of the SCL clock 4 0.6 0.26 us tSU,STA Setup time for a repeated START 4.7 0.6 0.26 us tHD,DAT Data hold time 0 0 0 ns tSU,DAT Data setup time 250 100 50 ns tSU,STO Setup time for STOP 4 0.6 0.26 us tBUF Bus free time between a STOP and START condition 4.7 1.3 0.5 us tVD;DAT Data valid time 3.45 0.9 0.45 us tVD;ACK Data valid acknowledge time 3.45 0.9 0.45 us over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS Standard mode Fast mode Fast mode plus UNIT MIN MAX MIN MAX MIN MAX fI2C I2C input clock frequency I2C in Power Domain0 2 32 8 32 20 32 MHz fSCL SCL clock frequency 0.1 0.4 1 MHz tHD,STA Hold time (repeated) START 4 0.6 0.26 us tLOW Low period of the SCL clock 4.7 1.3 0.5 us tHIGH High period of the SCL clock 4 0.6 0.26 us tSU,STA Setup time for a repeated START 4.7 0.6 0.26 us tHD,DAT Data hold time 0 0 0 ns tSU,DAT Data setup time 250 100 50 ns tSU,STO Setup time for STOP 4 0.6 0.26 us tBUF Bus free time between a STOP and START condition 4.7 1.3 0.5 us tVD;DAT Data valid time 3.45 0.9 0.45 us tVD;ACK Data valid acknowledge time 3.45 0.9 0.45 us PARAMETERS TEST CONDITIONS Standard mode Fast mode Fast mode plus UNIT MIN MAX MIN MAX MIN MAX PARAMETERS TEST CONDITIONS Standard mode Fast mode Fast mode plus UNIT PARAMETERSTEST CONDITIONSStandard modeFast modeFast mode plusUNIT MIN MAX MIN MAX MIN MAX MINMAXMINMAXMINMAX fI2C I2C input clock frequency I2C in Power Domain0 2 32 8 32 20 32 MHz fSCL SCL clock frequency 0.1 0.4 1 MHz tHD,STA Hold time (repeated) START 4 0.6 0.26 us tLOW Low period of the SCL clock 4.7 1.3 0.5 us tHIGH High period of the SCL clock 4 0.6 0.26 us tSU,STA Setup time for a repeated START 4.7 0.6 0.26 us tHD,DAT Data hold time 0 0 0 ns tSU,DAT Data setup time 250 100 50 ns tSU,STO Setup time for STOP 4 0.6 0.26 us tBUF Bus free time between a STOP and START condition 4.7 1.3 0.5 us tVD;DAT Data valid time 3.45 0.9 0.45 us tVD;ACK Data valid acknowledge time 3.45 0.9 0.45 us fI2C I2C input clock frequency I2C in Power Domain0 2 32 8 32 20 32 MHz fI2C I2CI2C input clock frequencyI2C in Power Domain02328322032MHz fSCL SCL clock frequency 0.1 0.4 1 MHz fSCL SCLSCL clock frequency0.10.41MHz tHD,STA Hold time (repeated) START 4 0.6 0.26 us tHD,STA HD,STAHold time (repeated) START40.60.26us tLOW Low period of the SCL clock 4.7 1.3 0.5 us tLOW LOWLow period of the SCL clock4.71.30.5us tHIGH High period of the SCL clock 4 0.6 0.26 us tHIGH HIGHHigh period of the SCL clock40.60.26us tSU,STA Setup time for a repeated START 4.7 0.6 0.26 us tSU,STA SU,STASetup time for a repeated START4.70.60.26us tHD,DAT Data hold time 0 0 0 ns tHD,DAT HD,DATData hold time000ns tSU,DAT Data setup time 250 100 50 ns tSU,DAT SU,DATData setup time25010050ns tSU,STO Setup time for STOP 4 0.6 0.26 us tSU,STO SU,STOSetup time for STOP40.60.26us tBUF Bus free time between a STOP and START condition 4.7 1.3 0.5 us tBUF BUFBus free time between a STOP and START condition4.71.30.5us tVD;DAT Data valid time 3.45 0.9 0.45 us tVD;DAT VD;DATData valid time3.450.90.45us tVD;ACK Data valid acknowledge time 3.45 0.9 0.45 us tVD;ACK VD;ACKData valid acknowledge time3.450.90.45us I2C Filter over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT fSP Pulse duration of spikes suppressed by input filter AGFSELx = 0 6 ns AGFSELx = 1 14 35 ns AGFSELx = 2 22 60 ns AGFSELx = 3 35 90 ns I2C Filter over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT fSP Pulse duration of spikes suppressed by input filter AGFSELx = 0 6 ns AGFSELx = 1 14 35 ns AGFSELx = 2 22 60 ns AGFSELx = 3 35 90 ns over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT fSP Pulse duration of spikes suppressed by input filter AGFSELx = 0 6 ns AGFSELx = 1 14 35 ns AGFSELx = 2 22 60 ns AGFSELx = 3 35 90 ns over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT fSP Pulse duration of spikes suppressed by input filter AGFSELx = 0 6 ns AGFSELx = 1 14 35 ns AGFSELx = 2 22 60 ns AGFSELx = 3 35 90 ns PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT PARAMETERSTEST CONDITIONSMINTYPMAXUNIT fSP Pulse duration of spikes suppressed by input filter AGFSELx = 0 6 ns AGFSELx = 1 14 35 ns AGFSELx = 2 22 60 ns AGFSELx = 3 35 90 ns fSP Pulse duration of spikes suppressed by input filter AGFSELx = 0 6 ns fSP SPPulse duration of spikes suppressed by input filterAGFSELx = 06ns AGFSELx = 1 14 35 ns AGFSELx = 11435ns AGFSELx = 2 22 60 ns AGFSELx = 22260ns AGFSELx = 3 35 90 ns AGFSELx = 33590ns I²C Timing Diagram I2C Timing Diagram I²C Timing Diagram2 I2C Timing Diagram I2C Timing Diagram I2C Timing Diagram I2C Timing Diagram SPI SPI over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT SPI fSPI SPI clock frequency Clock max speed = 32MHz1.62 < VDD < 3.6VController mode 16 MHz fSPI SPI clock frequency Clock max speed = 32MHz1.62 < VDD < 3.6VPeripheral mode 16 MHz DCSCK SCK Duty Cycle 40 50 60 % Controller tSCLK_H/L SCLK High or Low time (tSPI/2) - 1 tSPI / 2 (tSPI/2) + 1 ns tSU.CI POCI input data setup time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFE3FRNWR5LF 2.7 < VDD < 3.6V, delayed sampling enabled 1 ns 1.62 < VDD < 2.7V, delayed sampling enabled 1 tSU.CI POCI input data setup time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFE3FRNWR5LF 2.7 < VDD < 3.6V, no delayed sampling 27 ns 1.62 < VDD < 2.7V, no delayed sampling 35 tHD.CI POCI input data hold time 9 ns tVALID.CO PICO output data valid time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFR2FE1H6R5J 10 ns tHD.CO PICO output data hold time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFGGI3_DYZFT 1 ns Peripheral tCS.LEAD CS lead-time, CS active to clock 8 ns tCS.LAG CS lag time, Last clock to CS inactive 1 ns tCS.ACC CS access time, CS active to POCI data out 23 ns tCS.DIS CS disable time, CS inactive to POCI high impedance 19 ns tSU.PI PICO input data setup time 7 ns tHD.PI PICO input data hold time 31.25 ns tVALID.PO POCI output data valid time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFR2FE1H6R5J 2.7 < VDD < 3.6V 24 ns tVALID.PO POCI output data valid time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFR2FE1H6R5J 1.62 < VDD < 2.7V 31 ns tHD.PO POCI output data hold time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFGGI3_DYZFT 5 ns The POCI input data setup time can be fully compensated when delayed sampling feature is enabled. Specifies the time to drive the next valid data to the output after the output changing SCLK clock edge Specifies how long data on the output is valid after the output changing SCLK clock edge SPI Timing Diagram SPI Timing Diagram - Controller Mode SPI Timing Diagram - Peripheral Mode SPI SPI over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT SPI fSPI SPI clock frequency Clock max speed = 32MHz1.62 < VDD < 3.6VController mode 16 MHz fSPI SPI clock frequency Clock max speed = 32MHz1.62 < VDD < 3.6VPeripheral mode 16 MHz DCSCK SCK Duty Cycle 40 50 60 % Controller tSCLK_H/L SCLK High or Low time (tSPI/2) - 1 tSPI / 2 (tSPI/2) + 1 ns tSU.CI POCI input data setup time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFE3FRNWR5LF 2.7 < VDD < 3.6V, delayed sampling enabled 1 ns 1.62 < VDD < 2.7V, delayed sampling enabled 1 tSU.CI POCI input data setup time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFE3FRNWR5LF 2.7 < VDD < 3.6V, no delayed sampling 27 ns 1.62 < VDD < 2.7V, no delayed sampling 35 tHD.CI POCI input data hold time 9 ns tVALID.CO PICO output data valid time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFR2FE1H6R5J 10 ns tHD.CO PICO output data hold time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFGGI3_DYZFT 1 ns Peripheral tCS.LEAD CS lead-time, CS active to clock 8 ns tCS.LAG CS lag time, Last clock to CS inactive 1 ns tCS.ACC CS access time, CS active to POCI data out 23 ns tCS.DIS CS disable time, CS inactive to POCI high impedance 19 ns tSU.PI PICO input data setup time 7 ns tHD.PI PICO input data hold time 31.25 ns tVALID.PO POCI output data valid time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFR2FE1H6R5J 2.7 < VDD < 3.6V 24 ns tVALID.PO POCI output data valid time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFR2FE1H6R5J 1.62 < VDD < 2.7V 31 ns tHD.PO POCI output data hold time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFGGI3_DYZFT 5 ns The POCI input data setup time can be fully compensated when delayed sampling feature is enabled. Specifies the time to drive the next valid data to the output after the output changing SCLK clock edge Specifies how long data on the output is valid after the output changing SCLK clock edge SPI over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT SPI fSPI SPI clock frequency Clock max speed = 32MHz1.62 < VDD < 3.6VController mode 16 MHz fSPI SPI clock frequency Clock max speed = 32MHz1.62 < VDD < 3.6VPeripheral mode 16 MHz DCSCK SCK Duty Cycle 40 50 60 % Controller tSCLK_H/L SCLK High or Low time (tSPI/2) - 1 tSPI / 2 (tSPI/2) + 1 ns tSU.CI POCI input data setup time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFE3FRNWR5LF 2.7 < VDD < 3.6V, delayed sampling enabled 1 ns 1.62 < VDD < 2.7V, delayed sampling enabled 1 tSU.CI POCI input data setup time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFE3FRNWR5LF 2.7 < VDD < 3.6V, no delayed sampling 27 ns 1.62 < VDD < 2.7V, no delayed sampling 35 tHD.CI POCI input data hold time 9 ns tVALID.CO PICO output data valid time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFR2FE1H6R5J 10 ns tHD.CO PICO output data hold time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFGGI3_DYZFT 1 ns Peripheral tCS.LEAD CS lead-time, CS active to clock 8 ns tCS.LAG CS lag time, Last clock to CS inactive 1 ns tCS.ACC CS access time, CS active to POCI data out 23 ns tCS.DIS CS disable time, CS inactive to POCI high impedance 19 ns tSU.PI PICO input data setup time 7 ns tHD.PI PICO input data hold time 31.25 ns tVALID.PO POCI output data valid time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFR2FE1H6R5J 2.7 < VDD < 3.6V 24 ns tVALID.PO POCI output data valid time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFR2FE1H6R5J 1.62 < VDD < 2.7V 31 ns tHD.PO POCI output data hold time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFGGI3_DYZFT 5 ns The POCI input data setup time can be fully compensated when delayed sampling feature is enabled. Specifies the time to drive the next valid data to the output after the output changing SCLK clock edge Specifies how long data on the output is valid after the output changing SCLK clock edge over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT SPI fSPI SPI clock frequency Clock max speed = 32MHz1.62 < VDD < 3.6VController mode 16 MHz fSPI SPI clock frequency Clock max speed = 32MHz1.62 < VDD < 3.6VPeripheral mode 16 MHz DCSCK SCK Duty Cycle 40 50 60 % Controller tSCLK_H/L SCLK High or Low time (tSPI/2) - 1 tSPI / 2 (tSPI/2) + 1 ns tSU.CI POCI input data setup time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFE3FRNWR5LF 2.7 < VDD < 3.6V, delayed sampling enabled 1 ns 1.62 < VDD < 2.7V, delayed sampling enabled 1 tSU.CI POCI input data setup time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFE3FRNWR5LF 2.7 < VDD < 3.6V, no delayed sampling 27 ns 1.62 < VDD < 2.7V, no delayed sampling 35 tHD.CI POCI input data hold time 9 ns tVALID.CO PICO output data valid time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFR2FE1H6R5J 10 ns tHD.CO PICO output data hold time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFGGI3_DYZFT 1 ns Peripheral tCS.LEAD CS lead-time, CS active to clock 8 ns tCS.LAG CS lag time, Last clock to CS inactive 1 ns tCS.ACC CS access time, CS active to POCI data out 23 ns tCS.DIS CS disable time, CS inactive to POCI high impedance 19 ns tSU.PI PICO input data setup time 7 ns tHD.PI PICO input data hold time 31.25 ns tVALID.PO POCI output data valid time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFR2FE1H6R5J 2.7 < VDD < 3.6V 24 ns tVALID.PO POCI output data valid time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFR2FE1H6R5J 1.62 < VDD < 2.7V 31 ns tHD.PO POCI output data hold time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFGGI3_DYZFT 5 ns over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT SPI fSPI SPI clock frequency Clock max speed = 32MHz1.62 < VDD < 3.6VController mode 16 MHz fSPI SPI clock frequency Clock max speed = 32MHz1.62 < VDD < 3.6VPeripheral mode 16 MHz DCSCK SCK Duty Cycle 40 50 60 % Controller tSCLK_H/L SCLK High or Low time (tSPI/2) - 1 tSPI / 2 (tSPI/2) + 1 ns tSU.CI POCI input data setup time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFE3FRNWR5LF 2.7 < VDD < 3.6V, delayed sampling enabled 1 ns 1.62 < VDD < 2.7V, delayed sampling enabled 1 tSU.CI POCI input data setup time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFE3FRNWR5LF 2.7 < VDD < 3.6V, no delayed sampling 27 ns 1.62 < VDD < 2.7V, no delayed sampling 35 tHD.CI POCI input data hold time 9 ns tVALID.CO PICO output data valid time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFR2FE1H6R5J 10 ns tHD.CO PICO output data hold time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFGGI3_DYZFT 1 ns Peripheral tCS.LEAD CS lead-time, CS active to clock 8 ns tCS.LAG CS lag time, Last clock to CS inactive 1 ns tCS.ACC CS access time, CS active to POCI data out 23 ns tCS.DIS CS disable time, CS inactive to POCI high impedance 19 ns tSU.PI PICO input data setup time 7 ns tHD.PI PICO input data hold time 31.25 ns tVALID.PO POCI output data valid time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFR2FE1H6R5J 2.7 < VDD < 3.6V 24 ns tVALID.PO POCI output data valid time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFR2FE1H6R5J 1.62 < VDD < 2.7V 31 ns tHD.PO POCI output data hold time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFGGI3_DYZFT 5 ns PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT PARAMETERSTEST CONDITIONSMINTYPMAXUNIT SPI fSPI SPI clock frequency Clock max speed = 32MHz1.62 < VDD < 3.6VController mode 16 MHz fSPI SPI clock frequency Clock max speed = 32MHz1.62 < VDD < 3.6VPeripheral mode 16 MHz DCSCK SCK Duty Cycle 40 50 60 % Controller tSCLK_H/L SCLK High or Low time (tSPI/2) - 1 tSPI / 2 (tSPI/2) + 1 ns tSU.CI POCI input data setup time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFE3FRNWR5LF 2.7 < VDD < 3.6V, delayed sampling enabled 1 ns 1.62 < VDD < 2.7V, delayed sampling enabled 1 tSU.CI POCI input data setup time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFE3FRNWR5LF 2.7 < VDD < 3.6V, no delayed sampling 27 ns 1.62 < VDD < 2.7V, no delayed sampling 35 tHD.CI POCI input data hold time 9 ns tVALID.CO PICO output data valid time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFR2FE1H6R5J 10 ns tHD.CO PICO output data hold time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFGGI3_DYZFT 1 ns Peripheral tCS.LEAD CS lead-time, CS active to clock 8 ns tCS.LAG CS lag time, Last clock to CS inactive 1 ns tCS.ACC CS access time, CS active to POCI data out 23 ns tCS.DIS CS disable time, CS inactive to POCI high impedance 19 ns tSU.PI PICO input data setup time 7 ns tHD.PI PICO input data hold time 31.25 ns tVALID.PO POCI output data valid time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFR2FE1H6R5J 2.7 < VDD < 3.6V 24 ns tVALID.PO POCI output data valid time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFR2FE1H6R5J 1.62 < VDD < 2.7V 31 ns tHD.PO POCI output data hold time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFGGI3_DYZFT 5 ns SPI SPI fSPI SPI clock frequency Clock max speed = 32MHz1.62 < VDD < 3.6VController mode 16 MHz fSPI SPISPI clock frequencyClock max speed = 32MHz1.62 < VDD < 3.6VController mode16MHz fSPI SPI clock frequency Clock max speed = 32MHz1.62 < VDD < 3.6VPeripheral mode 16 MHz fSPI SPISPI clock frequencyClock max speed = 32MHz1.62 < VDD < 3.6VPeripheral mode16MHz DCSCK SCK Duty Cycle 40 50 60 % DCSCK SCKSCK Duty Cycle405060% Controller Controller tSCLK_H/L SCLK High or Low time (tSPI/2) - 1 tSPI / 2 (tSPI/2) + 1 ns tSCLK_H/L SCLK_H/LSCLK High or Low time (tSPI/2) - 1tSPI / 2(tSPI/2) + 1ns tSU.CI POCI input data setup time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFE3FRNWR5LF 2.7 < VDD < 3.6V, delayed sampling enabled 1 ns tSU.CI SU.CIPOCI input data setup time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFE3FRNWR5LF #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFE3FRNWR5LF2.7 < VDD < 3.6V, delayed sampling enabled1ns 1.62 < VDD < 2.7V, delayed sampling enabled 1 1.62 < VDD < 2.7V, delayed sampling enabled1 tSU.CI POCI input data setup time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFE3FRNWR5LF 2.7 < VDD < 3.6V, no delayed sampling 27 ns tSU.CI SU.CIPOCI input data setup time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFE3FRNWR5LF #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFE3FRNWR5LF2.7 < VDD < 3.6V, no delayed sampling27ns 1.62 < VDD < 2.7V, no delayed sampling 35 1.62 < VDD < 2.7V, no delayed sampling35 tHD.CI POCI input data hold time 9 ns tHD.CI HD.CIPOCI input data hold time9ns tVALID.CO PICO output data valid time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFR2FE1H6R5J 10 ns tVALID.CO VALID.COPICO output data valid time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFR2FE1H6R5J #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFR2FE1H6R5J10ns tHD.CO PICO output data hold time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFGGI3_DYZFT 1 ns tHD.CO HD.COPICO output data hold time #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFGGI3_DYZFT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFGGI3_DYZFT1ns Peripheral Peripheral tCS.LEAD CS lead-time, CS active to clock 8 ns tCS.LEAD CS.LEADCS lead-time, CS active to clock8ns tCS.LAG CS lag time, Last clock to CS inactive 1 ns tCS.LAG CS.LAGCS lag time, Last clock to CS inactive1ns tCS.ACC CS access time, CS active to POCI data out 23 ns tCS.ACC CS.ACCCS access time, CS active to POCI data out23ns tCS.DIS CS disable time, CS inactive to POCI high impedance 19 ns tCS.DIS CS.DISCS disable time, CS inactive to POCI high impedance19ns tSU.PI PICO input data setup time 7 ns tSU.PI SU.PIPICO input data setup time7ns tHD.PI PICO input data hold time 31.25 ns tHD.PI HD.PIPICO input data hold time31.25ns tVALID.PO POCI output data valid time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFR2FE1H6R5J 2.7 < VDD < 3.6V 24 ns tVALID.PO VALID.POPOCI output data valid time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFR2FE1H6R5J #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFR2FE1H6R5J2.7 < VDD < 3.6V24ns tVALID.PO POCI output data valid time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFR2FE1H6R5J 1.62 < VDD < 2.7V 31 ns tVALID.PO VALID.POPOCI output data valid time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFR2FE1H6R5J #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFR2FE1H6R5J1.62 < VDD < 2.7V31ns tHD.PO POCI output data hold time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFGGI3_DYZFT 5 ns tHD.PO HD.POPOCI output data hold time#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFGGI3_DYZFT #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000376808/SFGGI3_DYZFT5ns The POCI input data setup time can be fully compensated when delayed sampling feature is enabled. Specifies the time to drive the next valid data to the output after the output changing SCLK clock edge Specifies how long data on the output is valid after the output changing SCLK clock edge The POCI input data setup time can be fully compensated when delayed sampling feature is enabled.Specifies the time to drive the next valid data to the output after the output changing SCLK clock edgeSpecifies how long data on the output is valid after the output changing SCLK clock edge SPI Timing Diagram SPI Timing Diagram - Controller Mode SPI Timing Diagram - Peripheral Mode SPI Timing Diagram SPI Timing Diagram - Controller Mode SPI Timing Diagram - Peripheral Mode SPI Timing Diagram - Controller Mode SPI Timing Diagram - Peripheral Mode SPI Timing Diagram - Controller Mode SPI Timing Diagram - Controller Mode SPI Timing Diagram - Peripheral Mode SPI Timing Diagram - Peripheral Mode UART over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT fUART UART input clock frequency 32 MHz fBITCLK BITCLK clock frequency(equals baud rate in MBaud) 4 MHz tSP Pulse duration of spikes suppressed by input filter AGFSELx = 0 6 ns AGFSELx = 1 14 35 ns AGFSELx = 2 22 60 ns AGFSELx = 3 35 90 ns UART over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT fUART UART input clock frequency 32 MHz fBITCLK BITCLK clock frequency(equals baud rate in MBaud) 4 MHz tSP Pulse duration of spikes suppressed by input filter AGFSELx = 0 6 ns AGFSELx = 1 14 35 ns AGFSELx = 2 22 60 ns AGFSELx = 3 35 90 ns over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT fUART UART input clock frequency 32 MHz fBITCLK BITCLK clock frequency(equals baud rate in MBaud) 4 MHz tSP Pulse duration of spikes suppressed by input filter AGFSELx = 0 6 ns AGFSELx = 1 14 35 ns AGFSELx = 2 22 60 ns AGFSELx = 3 35 90 ns over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT fUART UART input clock frequency 32 MHz fBITCLK BITCLK clock frequency(equals baud rate in MBaud) 4 MHz tSP Pulse duration of spikes suppressed by input filter AGFSELx = 0 6 ns AGFSELx = 1 14 35 ns AGFSELx = 2 22 60 ns AGFSELx = 3 35 90 ns PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT PARAMETERSTEST CONDITIONSMINTYPMAXUNIT fUART UART input clock frequency 32 MHz fBITCLK BITCLK clock frequency(equals baud rate in MBaud) 4 MHz tSP Pulse duration of spikes suppressed by input filter AGFSELx = 0 6 ns AGFSELx = 1 14 35 ns AGFSELx = 2 22 60 ns AGFSELx = 3 35 90 ns fUART UART input clock frequency 32 MHz fUART UARTUART input clock frequency32MHz fBITCLK BITCLK clock frequency(equals baud rate in MBaud) 4 MHz fBITCLK BITCLKBITCLK clock frequency(equals baud rate in MBaud)4MHz tSP Pulse duration of spikes suppressed by input filter AGFSELx = 0 6 ns tSP SPPulse duration of spikes suppressed by input filterAGFSELx = 06ns AGFSELx = 1 14 35 ns AGFSELx = 11435ns AGFSELx = 2 22 60 ns AGFSELx = 22260ns AGFSELx = 3 35 90 ns AGFSELx = 33590ns TIMx over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT tres Timer resolution time fTIMxCLK = 32MHz 31.25 ns 1 tTIMxCLK tres Timer resolution time TIMx with 16bit counter 16 bit tCOUNTER 16-bit counter clock period fTIMxCLK = 32MHz 0.03125 2048 us 1 65536 tTIMxCLK TIMx over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT tres Timer resolution time fTIMxCLK = 32MHz 31.25 ns 1 tTIMxCLK tres Timer resolution time TIMx with 16bit counter 16 bit tCOUNTER 16-bit counter clock period fTIMxCLK = 32MHz 0.03125 2048 us 1 65536 tTIMxCLK over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT tres Timer resolution time fTIMxCLK = 32MHz 31.25 ns 1 tTIMxCLK tres Timer resolution time TIMx with 16bit counter 16 bit tCOUNTER 16-bit counter clock period fTIMxCLK = 32MHz 0.03125 2048 us 1 65536 tTIMxCLK over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT tres Timer resolution time fTIMxCLK = 32MHz 31.25 ns 1 tTIMxCLK tres Timer resolution time TIMx with 16bit counter 16 bit tCOUNTER 16-bit counter clock period fTIMxCLK = 32MHz 0.03125 2048 us 1 65536 tTIMxCLK PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT PARAMETERSTEST CONDITIONSMINTYPMAXUNIT tres Timer resolution time fTIMxCLK = 32MHz 31.25 ns 1 tTIMxCLK tres Timer resolution time TIMx with 16bit counter 16 bit tCOUNTER 16-bit counter clock period fTIMxCLK = 32MHz 0.03125 2048 us 1 65536 tTIMxCLK tres Timer resolution time fTIMxCLK = 32MHz 31.25 ns tres resTimer resolution timefTIMxCLK = 32MHzTIMxCLK31.25ns 1 tTIMxCLK 1tTIMxCLK TIMxCLK tres Timer resolution time TIMx with 16bit counter 16 bit tres resTimer resolution timeTIMx with 16bit counter16bit tCOUNTER 16-bit counter clock period fTIMxCLK = 32MHz 0.03125 2048 us tCOUNTER COUNTER16-bit counter clock periodfTIMxCLK = 32MHzTIMxCLK0.031252048us 1 65536 tTIMxCLK 165536tTIMxCLK TIMxCLK Emulation and Debug SWD Timing over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSWD SWD frequency 10 MHz Emulation and Debug SWD Timing over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSWD SWD frequency 10 MHz SWD Timing over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSWD SWD frequency 10 MHz over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSWD SWD frequency 10 MHz over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fSWD SWD frequency 10 MHz PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PARAMETERTEST CONDITIONSMINTYPMAXUNIT fSWD SWD frequency 10 MHz fSWD SWD frequency 10 MHz fSWD SWDSWD frequency10MHz Detailed Description The following sections describe all of the components that make up the devices in this data sheet. The peripherals integrated into these devices are configured by software through Memory Mapped Registers (MMRs). For more details, see the corresponding chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . CPU The CPU subsystem (MCPUSS) implements an Arm Cortex-M0+ CPU, an instruction prefetch and cache, a system timer, and interrupt management features. The Arm Cortex-M0+ is a cost-optimized 32-bit CPU that delivers high performance and low power to embedded applications. Key features of the CPU Sub System include: Arm Cortex-M0+ CPU supports clock frequencies from 32 kHz to 32 MHz ARMv6-M Thumb instruction set (little endian) with single-cycle 32×32 multiply instruction Single-cycle access to GPIO registers through Arm single-cycle IO port Prefetch logic to improve sequential code execution, and I-cache with 2 64-bit cache lines System timer (SysTick) with 24-bit down counter and automatic reload Nested vectored interrupt controller (NVIC) with 4 programmable priority levels and tail chaining Interrupt groups for expanding the total interrupt sources, with jump index for low interrupt latency Operating Modes MSPM0L MCUs provide five main operating modes (power modes) to allow for optimization of the device power consumption based on application requirements. In order of decreasing power, the modes are: RUN, SLEEP, STOP, STANDBY, and SHUTDOWN. The CPU is active executing code in RUN mode. Peripheral interrupt events can wake the device from SLEEP, STOP, or STANDBY mode to the RUN mode. SHUTDOWN mode completely disables the internal core regulator to minimize power consumption, and wake is only possible via NRST, SWD, or a logic level match on certain IOs. RUN, SLEEP, STOP, and STANDBY modes also include several configurable policy options (for example, RUN.x) for balancing performance with power consumption. To further balance performance and power consumption, MSPM0L devices implement two power domains: PD1 (for the CPU, memories, and high performance peripherals), and PD0 (for low speed, low power peripherals). PD1 is always powered in RUN and SLEEP modes, but is disabled in all other modes. PD0 is always powered in RUN, SLEEP, STOP, and STANDBY modes. PD1 and PD0 are both disabled in SHUTDOWN mode. Functionality by Operating Mode Supported functionality in each operating mode is given in #GUID-977123ED-F95F-428C-8E94-CA9378F25E84/GUID-1905293B-066A-4864-B43E-7BB9C5D7A0C9. Functional key: EN: The function is enabled in the specified mode. DIS: The function is disabled (either clock or power gated) in the specified mode, but the function's configuration is retained. OPT: The function is optional in the specified mode, and remains enabled if configured to be enabled. NS: The function is not automatically disabled in the specified mode, but its use is not supported. OFF: The function is fully powered off in the specified mode, and no configuration information is retained. Supported Functionality by Operating Mode Operating Mode RUN SLEEP STOP STANDBY SHUTDOWN RUN0 RUN1 RUN2 SLEEP0 SLEEP1 SLEEP2 STOP0 STOP1 STOP2 STANDBY0 STANDBY1 Oscillators SYSOSC EN EN DIS EN EN DIS OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB EN DIS DIS DIS OFF LFOSC EN OFF Clocks CPUCLK 32M 32k 32k DIS OFF MCLK to PD1 32M 32k 32k 32M 32k 32k DIS OFF ULPCLK to PD0 32M 32k 32k 32M 32k 32k 4M#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB 4M 32k DIS OFF ULPCLK to TIMG0/1 32M 32k 32k 32M 32k 32k 4M#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB 4M 32k OFF MFCLK OPT DIS OPT DIS OPT DIS OFF LFCLK 32k DIS OFF LFCLK to TIMG0/1 32k OFF MCLK Monitor OPT DIS OFF PMU POR Monitor EN BOR Monitor EN OFF Core Regulator FULL DRIVE REDUCED DRIVE LOW DRIVE OFF Core Functions CPU EN DIS OFF DMA OPT NS (triggers supported) OFF Flash EN DIS OFF SRAM EN DIS OFF PD1 Peripherals SPI0 OPT DIS OFF CRC OPT DIS OFF PD0 Peripherals TIMG0/1 OPT OFF TIMG2/4 OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF UART0/1 OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF I2C0/1 OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF GPIOA OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF WWDT0 OPT DIS OFF Analog ADC0 OPT NS (triggers supported) OFF OPA0/1 OPT NS OPT NS OPT NS OFF GPAMP OPT NS OFF COMP0 OPT OPT (ULP) OPT OPT (ULP) OPT OPT (ULP) OFF IOMUX and IO Wakeup EN DIS w/ WAKE Wake Sources N/A ANY IRQ PD0 IRQ IOMUX, NRST, SWD If STOP0 is entered from RUN1 (SYSOSC enabled but MCLK sourced from LFCLK), SYSOSC remains enabled as in RUN1 and ULPCLK remains at 32 kHz as in RUN1. If STOP0 is entered from RUN2 (SYSOSC was disabled and MCLK was sourced from LFCLK), SYSOSC remains disabled as in RUN2 and ULPCLK remains at 32 kHz as in RUN2. When using the STANDBY1 policy for STANDBY, only TIMG0 and TIMG1 are clocked. Other PD0 peripherals can generate an asynchronous fast clock request upon external activity but are not actively clocked. Power Management Unit (PMU) The power management unit (PMU) generates the internally regulated core supplies for the device and provides supervision of the external supply (VDD). The PMU also contains the bandgap voltage reference used by the PMU itself as well as analog peripherals. Key features of the PMU include: Power-on reset (POR) supply monitor Brownout reset (BOR) supply monitor with early warning capability using three programmable thresholds Core regulator with support for RUN, SLEEP, STOP, and STANDBY operating modes to dynamically balance performance with power consumption Parity-protected trim to immediately generate a power-on reset (POR) in the event that a power management trim is corrupted For more details, see the PMU chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . Clock Module (CKM) The clock module provides the following oscillators: LFOSC: Internal low-frequency oscillator (32 kHz) SYSOSC: Internal high-frequency oscillator (4 MHz or 32 MHz with factory trim, 16 MHz or 24 MHz with user trim) The following clocks are distributed by the clock module for use by the processor, bus, and peripherals: MCLK: Main system clock for PD1 peripherals, derived from SYSOSC or LFCLK, active in RUN and SLEEP modes CPUCLK: Clock for the processor (derived from MCLK), active in RUN mode ULPCLK: Ultra-low power clock for PD0 peripherals, active in RUN, SLEEP, STOP, and STANDBY modes MFCLK: 4-MHz fixed mid-frequency clock for peripherals, available in RUN, SLEEP, and STOP modes LFCLK: 32-kHz fixed low-frequency clock for peripherals or MCLK, active in RUN, SLEEP, STOP, and STANDBY modes ADCCLK: ADC clock, available in RUN, SLEEP and STOP modes CLK_OUT: Used to output a clock externally, available in RUN, SLEEP, STOP, and STANDBY modes For more details, see the CKM chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . DMA The direct memory access (DMA) controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA can be used to move data from ADC conversion memory to SRAM. The DMA reduces system power consumption by allowing the CPU to remain in low power mode, without having to awaken to move data to or from a peripheral. The DMA in these devices support the following key features: 3 independent DMA transfer channels 1 full-feature channel (DMA0), supporting repeated transfer modes 2 basic channels (DMA1, DMA2), supporting single transfer modes Configurable DMA channel priorities Byte (8-bit), short word (16-bit), word (32-bit) and long word (64-bit) or mixed byte and word transfer capability Transfer counter block size supports up to 64k transfers of any data type Configurable DMA transfer trigger selection Active channel interruption to service other channels Early interrupt generation for ping-pong buffer architecture Cascading channels upon completion of activity on another channel Stride mode to support data re-organization #GUID-2419372E-9A40-4FA9-808F-2DF8632C5F3E/TABLE_KL4_T4S_CQB lists the available triggers for the DMA which are configured using the DMATCTL.DMATSEL control bits in the DMA memory mapped registers. DMA Trigger Mapping TRIGGER 0:6 SOURCE TRIGGER 7:13 SOURCE 0 Software 7 I2C1 Publisher 2 1 Generic Subscriber 0 (FSUB_0) 8 SPI0 Publisher 1 2 Generic Subscriber 1 (FSUB_1) 9 SPI0 Publisher 2 3 ADC0 Publisher 2 10 UART0 Publisher 1 4 I2C0 Publisher 1 11 UART0 Publisher 2 5 I2C0 Publisher 2 12 UART1 Publisher 1 6 I2C1 Publisher 1 13 UART1 Publisher 2 Events The event manager transfers digital events from one entity (for example, a peripheral) to another (for example, a second peripheral, the DMA or the CPU). The event manager implements event transfer through a defined set of event publishers (generators) and subscribers (receivers) that are interconnected through an event fabric containing a combination of static and programmable routes. Events that are transferred by the event manager include: Peripheral event transferred to the CPU as an interrupt request (IRQ) (Static Event) Example: GPIO interrupt is sent to the CPU Peripheral event transferred to the DMA as a DMA trigger (DMA Event) Example: UART data receive trigger to DMA to request a DMA transfer Peripheral event transferred to another peripheral to directly trigger an action in hardware (Generic Event) Example: TIMx timer peripheral publishes a periodic event to the ADC subscriber port, and the ADC uses the event to trigger start-of-sampling For more details, see the Event chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . Generic Event Channels A generic route is either a point-to-point (1:1) route or a point-to-two (1:2) splitter route in which the peripheral publishing the event is configured to use one of several available generic route channels to publish the event to another entity (or entities, in the case of a splitter route). An entity can be another peripheral, a generic DMA trigger event, or a generic CPU event. CHANID Generic Route Channel Selection Channel Type 0 No generic event channel selected N/A 1 Generic event channel 1 selected 1 : 1 2 Generic event channel 2 selected 1 : 1 3 Generic event channel 3 selected 1 : 2 (splitter) Memory Memory Organization The following table summarizes the memory map of the devices. For more information about the memory region detail, see the Platform Memory Map chapter in the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . Memory Organization Memory Region Subregion MSPM0L1304 MSPM0L1305 MSPM0L1306 Code (Flash) MAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 16KB - 8B0x0000.0000 to 0x0000.3FF8 32KB - 8B#GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC 0x0000.0000 to 0x0000.7FF8 64KB - 8B#GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC 0x0000.0000 to 0x0000.FFF8 Aliased MAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 0x0040.0000 to 0x0040.3FF8 0x0040.0000 to 0x0040.7FF8 0x0040.0000 to 0x0040.FFF8 SRAM (SRAM) SRAM 2KB0x2000.0000 to 0x2000.0800 4KB0x2000.0000 to 0x2000.1000 4KB0x2000.0000 to 0x2000.1000 Aliased SRAM#GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE 0x2000.0000 to 0x2000.0800 0x2000.0000 to 0x2000.1000 0x2000.0000 to 0x2000.1000 Peripheral Peripherals 0x4000.0000 to 0x40FF.FFFF 0x4000.0000 to 0x40FF.FFFF 0x4000.0000 to 0x40FF.FFFF MAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 0x0000.0000 to 0x0000.3FF8 0x0000.0000 to 0x0000.7FF8 0x0000.0000 to 0x0000.FFF8 Aliased MAIN#GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 0x0040.0000 to 0x0040.3FF8 0x0040.0000 to 0x0040.7FF8 0x0040.0000 to 0x0040.FFF8 NONMAIN 512 bytes0x41C0.0000 to 0x41C0.0200 512 bytes0x41C0.0000 to 0x41C0.0200 512 bytes0x41C0.0000 to 0x41C0.0200 Aliased NONMAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE 0x41C1.0000 to 0x41C1.0200 0x41C1.0000 to 0x41C1.0200 0x41C1.0000 to 0x41C1.0200 FACTORY 0x41C4.0000 to 0x41C4.0080 0x41C4.0000 to 0x41C4.0080 0x41C4.0000 to 0x41C4.0080 Aliased FACTORY #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE 0x41C5.0000 to 0x41C5.0080 0x41C5.0000 to 0x41C5.0080 0x41C5.0000 to 0x41C5.0080 Subsystem 0x6000.0000 to 0x7FFF.FFFF 0x6000.0000 to 0x7FFF.FFFF 0x6000.0000 to 0x7FFF.FFFF System PPB 0xE000.0000 to 0xE00F.FFFF 0xE000.0000 to 0xE00F.FFFF 0xE000.0000 to 0xE00F.FFFF First 32KB flash memory (address 0x0000.0000 to 0x0000.8000) has up to 100000 program and erase cycles. Aliased memory reads the same as the corresponding memory region. Aliased memory is included to keep the compatibility with devices that have ECC. CPU access to one of the last 8 bytes of a flash region will cause a hard fault. This occurs because the prefetch logic tries to read one flash word (64 bits) ahead, resulting in a read attempt to an invalid memory location. Peripheral File Map #GUID-75EA9B50-3030-49EE-B191-0EF3DCD84C4A/TABLE_AXS_5GM_CRB lists the available peripherals and the register base address for each. Peripherals Summary Peripheral Name Base Address Size ADC0 0x40004000 0x2000 COMP0 0x40008000 0x2000 OPA0 0x40020000 0x2000 OPA1 0x40022000 0x2000 VREF 0x40030000 0x2000 WWDT0 0x40080000 0x2000 TIMG0 0x40084000 0x2000 TIMG1 0x40086000 0x2000 TIMG2 0x40088000 0x2000 TIMG4 0x4008C000 0x2000 GPIO0 0x400A0000 0x2000 SYSCTL 0x400AF000 0x3000 DEBUGSS 0x400C7000 0x2000 EVENT 0x400C9000 0x3000 NVMNW 0x400CD000 0x2000 I2C0 0x400F0000 0x2000 I2C1 0x400F2000 0x2000 UART1 0x40100000 0x2000 UART0 0x40108000 0x2000 MCPUSS 0x40400000 0x2000 WUC 0x40424000 0x1000 IOMUX 0x40428000 0x2000 DMA 0x4042A000 0x2000 CRC 0x40440000 0x2000 SPI0 0x40468000 0x2000 ADC0 (1) 0x4055A000 0x1000 (1) Aliased region of ADC0 memory-mapped registers. Peripheral Interrupt Vector #GUID-E85B0824-C3C2-42E1-ABB9-E274B22E95FC/TABLE_AXS_5GM_CRB shows the IRQ number and the interrupt group number for each peripherals in this device. Interrupt Vector Number Peripheral Name NVIC IRQ Group IIDX WWDT0 0 0 DEBUGSS 0 2 NVMNW 0 3 EVENT SUB PORT0 0 4 EVENT SUB PORT1 0 5 SYSCTL 0 6 GPIO0 1 0 COMP0 1 2 TIMG1 2 – ADC 4 – SPI0 9 – UART1 13 – UART0 15 – TIMG0 16 – TIMG2 18 – TIMG4 20 – I2C0 24 – I2C1 25 – DMA 31 – Flash Memory A single bank of nonvolatile flash memory is provided for storing executable program code and application data. Key features of the flash include: In-circuit program and erase operations supported across the entire recommended supply range Small 1KB sector sizes (minimum erase resolution of 1KB) Up to 100000 program and erase cycles on the lower 32KB of the flash memory, with up to 10000 program and erase cycles on the remaining flash memory (devices with 32KB or less support 100000 cycles on the entire flash memory) For a complete description of the flash memory, see the NVM chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . SRAM MSPM0Lxx MCUs include a low-power high-performance SRAM memory with zero wait state access across the supported CPU frequency range of the device. SRAM memory can be used for storing volatile information such as the call stack, heap, global data, and code. The SRAM memory content is fully retained in run, sleep, stop, and standby operating modes and is lost in shutdown mode. A write protection mechanism is provided to allow the application to prevent unintended modifications to a portion of the SRAM memory. SRAM write protection is useful when placing executable code into SRAM to provide a level of protection against unintentional overwrites of code by either the CPU or DMA. Placing code in SRAM can improve performance of critical loops by enabling zero wait state operation and lower power consumption. GPIO The general purpose input/output (GPIO) peripheral lets the application write data out and read data in through the device pins. Through the use of the Port A GPIO peripheral, these devices support up to 28 GPIO pins. The key features of the GPIO module include: 0 wait state MMR access from CPU Set, clear, or toggle multiple bits without the need of a read-modify-write construct in software "FastWake" feature enables low-power wakeup from STOP and STANDBY modes for any GPIO port User controlled input filtering IOMUX The IOMUX peripheral enables IO pad configuration and controls digital data flow to and from the device pins. The key features of the IOMUX include: IO pad configuration registers allow for programmable drive strength, speed, pullup or pulldown, and more Digital pin muxing allows for multiple peripheral signals to be routed to the same IO pad Pin functions and capabilities are user-configured using the PINCM register For more details, see the IOMUX chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . ADC The 12-bit analog-to-digital converter (ADC) module in these devices support fast 12-bit conversions with single-ended inputs. ADC features include: 12-bit output resolution at up to 1.68 Msps with greater than 11-bit ENOB HW averaging enables 14-bit conversion resolution at 105ksps Up to 10 external input channels Internal channels for temperature sensing, supply monitoring, and analog signal chain (interconnection with OPA, GPAMP, and others) Software selectable reference: Configurable internal dedicated ADC reference voltage of 1.4 V and 2.5 V (VREF) MCU supply voltage (VDD) External reference supplied to the ADC through the VREF+ and VREF- pins Operates in RUN, SLEEP, and STOP modes and supports triggers from STANDBY mode ADC0 Channel Mapping CHANNEL[0:7] SIGNAL NAME CHANNEL[8:15] SIGNAL NAME #GUID-2F456BA4-610F-47CC-869A-A4BC7D8436F6/LI_LYD_D5B_ZPB #GUID-2F456BA4-610F-47CC-869A-A4BC7D8436F6/GUID-CE37C01A-86CC-4266-8B64-2AEFEFEC39DC 0 A0 8 A8 1 A1 9 A9 2 A2 10 – 3 A3 11 Temperature Sensor 4 A4 12 OPA0 output 5 A5 13 OPA1 output 6 A6 14 GPAMP output 7 A7 15 Supply/Battery Monitor Italicized signal names are internal to the SoC. These signals are used for internal peripheral interconnections. For more information about device analog connections see . For more details, see the ADC chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . Temperature Sensor The temperature sensor provides a voltage output that changes linearly with device temperature. The temperature sensor output is internally connected to one of ADC input channels to enable a temperature-to-digital conversion. A unit-specific single-point calibration value for the temperature sensor is provided in the factory constants memory region. This calibration value represents the ADC conversion result (in ADC code format) corresponding to the temperature sensor being measured in 12-bit mode with VDD = 3.3V at the factory trim temperature (TSTRIM). The ADC and VREF configuration for the above measurement is as the following: RES=0 (12-bit mode), VRSEL=0h (VDD), ADC tSample=12.5µs. This calibration value can be used with the temperature sensor temperature coefficient (TSc) to estimate the device temperature. See the temperature sensor section of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual for guidance on estimating the device temperature with the factory trim value. VREF The voltage reference module (VREF) in these devices contains a configurable voltage reference buffer dedicated for the on-board ADC. The devices also support connection of an external reference for applications in which higher accuracy is required. VREF features include: 1.4-V and 2.5-V user-selectable internal reference for ADC Internal reference supports ADC operation up to 200 ksps Support for bringing in an external reference for the ADC as well as for other analog peripherals on the VREF+ and VREF- device pins (24, 28, and 32-pin packages only) For more details, see the VREF chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . COMP The comparator peripheral in the device compares the voltage levels on two inputs terminals and provides a digital output based on this comparison. The COMP supports the following key features: Programmable hysteresis Programmable reference voltage: Integrated 8-bit reference DAC, the output can also can connect to OPA input terminal internally as an output buffer. Configurable operation modes: High-speed mode (for the lowest propagation delay in timing-critical applications) Low-power mode (for monitoring slow-moving signals at the lowest power consumption) Programmable output glitch filter delay "Support output wake up device from all but the lowest low-power mode The IPSEL and IMSEL bits in comparator registers can be used to select the comparator channel inputs from device pins or from internal analog modules. COMP0 Input Channel Selection GUID-B2DFDAAE-EEC7-413E-B4AC-C1D0E3C5053E.html#unique_87_Connect_42_GUID-FA5669C8-C5A2-4D62-8FAF-5B607680FE12 IPSEL / IMSEL Bits Positive Terminal Input Negative Terminal Input 0x0 COMP0_IN0+ COMP0_IN0- 0x1 COMP0_IN1+ COMP0_IN1- 0x6 OPA1 output OPA0 output For more information about device analog connections, see . COMP0 Blanking Source Table CTL2.BLANKSRC Blanking Source Selected 0x0 Blanking source disabled 0x1 TIMG0.CC1 0x2 TIMG1.CC1 0x3 TIMG2.CC1 For more details, see the COMP chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . CRC The cyclical redundancy check (CRC) module provides a signature for an input data sequence. Key features of the CRC module include: Support for 16-bit CRC based on CRC16-CCITT Support for 32-bit CRC based on CRC32-ISO3309 Support for bit reversal For more details, see the CRC chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . GPAMP The general-purpose amplifier (GPAMP) peripheral is a chopper-stabilized general-purpose operational amplifier with rail-to-rail input and output. The GPAMP supports the following features: Software selectable chopper stabilization Rail-to-rail input and output Programmable internal unity gain feedback loop For more details, see the ADC chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . OPA The zero-drift op amps (OPAs) in these devices, OPA0 and OPA1, are chopper stabilized operational amplifiers with rail-to-rail input/output and a programmable gain stage feedback loop. The OPA peripherals support the following key features: Software-selectable zero-drift chopper stabilization for improved accuracy and drift performance Factory trimming to remove offset error Burnout current source (BCS) integrated to monitor sensor health Programmable gain amplifier (PGA) up to 32x The OPA features configurable input muxes P-MUX, N-MUX, and M-MUX to support various analog signal chain amplifier configurations that include general purpose, inverting, noninverting, unity gain, cascade, noninverting cascade, difference, and more. The following tables list the input channel mapping for each OPA. For more information about device analog connections, see For more details, see the OPA chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . I2C The inter-integrated circuit interface (I2C) peripherals in these devices provide bidirectional data transfer with other I2C devices on the bus and support the following key features: 7-bit and 10-bit addressing mode with multiple 7-bit target addresses Multiple-controller transmitter or receiver mode Target receiver or transmitter mode with configurable clock stretching Support Standard-mode (Sm), with a bit rate up to 100 kbit/s Support Fast-mode (Fm), with a bit rate up to 400 kbit/s Support Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s Supported on open drain IOs only (ODIO) Separated transmit and receive FIFOs support DMA data transfer Support SMBus 3.0 with PEC, ARP, timeout detection and host support Wakeup from low power mode on address match Support analog and digital glitch filter for input signal glitch suppression 8-entry transmit and receive FIFOs For more details, see the I2C chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . SPI The serial peripheral interface (SPI) peripherals in these devices support the following key features: Support ULPCLK/2 bit rate and up to 16Mbits/s in both controller and peripheral mode Configurable as a controller or a peripheral Configurable chip select for both controller and peripheral Programmable clock prescaler and bit rate Programmable data frame size from 4 bits to 16 bits (controller mode) and 7 bits to 16 bit (peripheral mode) Supports PACKEN feature that allows the packing of 2 16 bit FIFO entries into a 32-bit value to improve CPU performance Transmit and receive FIFOs (4 entries each with 16 bits per entry) supporting DMA data transfer Supports TI mode, Motorola mode and National Microwire format For more details, see the SPI chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . UART The UART peripherals provide the following key features: Standard asynchronous communication bits for start, stop, and parity Fully programmable serial interface 5, 6, 7 or 8 data bits Even, odd, stick, or no-parity bit generation and detection 1 or 2 stop bit generation Line-break detection Glitch filter on the input signals Programmable baud rate generation with oversampling by 16, 8 or 3 Local Interconnect Network (LIN) mode support Separated transmit and receive FIFOs support DAM data transfer Support transmit and receive loopback mode operation See #GUID-EB789472-7BE7-4F51-B659-FEED65B095DE/TABLE_DZ1_1M5_1RB for detail information on supported protocols UART Features UART Features UART0 (Extend) UART1 (Main) Active in Stop and Standby Mode Yes Yes Separate transmit and receive FIFOs Yes Yes Support hardware flow control Yes Yes Support 9-bit configuration Yes Yes Support LIN mode Yes - Support DALI Yes - Support IrDA Yes - Support ISO7816 Smart Card Yes - Support Manchester coding Yes - FIFO Depth 4 entries 4 entries For more details, see the UART chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . WWDT The windowed watchdog timer (WWDT) can be used to supervise the operation of the device, specifically code execution. The WWDT can be used to generate a reset or an interrupt if the application software does not successfully reset the watchdog within a specified window of time. Key features of the WWDT include: 25-bit counter Programmable clock divider Eight software selectable watchdog timer periods Eight software selectable window sizes Support for stopping the WWDT automatically when entering a sleep mode Interval timer mode for applications which do not require watchdog functionality For more details, see the WWDT chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . Timers (TIMx) The timer peripherals in these devices support the following key features. For specific configuration, see #GUID-3E3CAD8F-A052-4B0B-AB71-00B63C0F6173/TABLE_ZXW_LBJ_34B. Specific features for the general-purpose timer (TIMGx) include: 16-bit timers with up, down or up-down counting modes, with repeat-reload mode Selectable and configurable clock source 8-bit programmable prescaler to divide the counter clock frequency Two independent channels for Output compare Input capture PWM output One-shot mode Support quadrature encoder interface (QEI) for positioning and movement sensing Support synchronization and cross trigger among different TIMx instances in the same power domain Support interrupt/DMA trigger generation and cross peripherals (such as ADC) trigger capability Cross-trigger event logic for Hall sensor inputs Different TIMG Configurations TIM Name Power Domain Resolution Prescaler Capture/ Compare Channels External PWM Channels Phase Load Shadow Load Shadow CC TIMG0 PD0 16-bit 8-bit 2 2 - - - TIMG1 PD0 16-bit 8-bit 2 2 - - - TIMG2 PD0 16-bit 8-bit 2 2 - - - TIMG4 PD0 16-bit 8-bit 2 2 - Yes Yes TIMG Cross Trigger Map TSEL.ETSEL Selection TIMG0 TIMG1 TIMG2 TIMG4 0 TIMG0.TRIG0 TIMG0.TRIG0 TIMG0.TRIG0 TIMG0.TRIG0 1 TIMG1.TRIG0 TIMG1.TRIG0 TIMG1.TRIG0 TIMG1.TRIG0 2 TIMG2.TRIG0 TIMG2.TRIG0 TIMG2.TRIG0 TIMG2.TRIG0 3 TIMG4.TRIG0 TIMG4.TRIG0 TIMG4.TRIG0 TIMG4.TRIG0 4 to 15 Reserved 16 Event Subscriber Port 0 (FSUB0) 17 Event Subscriber Port 1 (FSUB1) 18to 31 Reserved For more details, see the timer chapters of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . Device Analog Connections shows the internal analog connection of the device. Analog Connections Input/Output Diagrams The IOMUX manages the selection of which peripheral function is to be used on a digital IO and provides the controls for the output driver, input path, and the wake-up logic for wakeup from SHUTDOWN mode. For more information, see the IOMUX section of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The mixed-signal IO pin slice diagram for a full featured IO pin is shown in . Not all pins have analog functions, wake-up logic, drive strength control, and pullup or pulldown resistors available. See the device-specific data sheet for detailed information on what features are supported for a specific pin. Superset Input/Output Diagram Serial Wire Debug Interface A serial wire debug (SWD) two-wire interface is provided via an Arm compatible serial wire debug port (SW-DP) to enable access to multiple debug functions within the device. For a complete description of the debug functionality offered on MSPM0 devices, see the debug chapter of the technical reference manual. Serial Wire Debug Pin Requirements and Functions DEVICE SIGNAL DIRECTION SWD FUNCTION SWCLK Input Serial wire clock from debug probe SWDIO Input/Output Bi-directional (shared) serial wire data Bootstrap Loader (BSL) The bootstrap loader (BSL) enables configuration of the device as well as programming of the device memory through a UART or I2C serial interface. Access to the device memory and configuration through the BSL is protected by a 256-bit user-defined password, and it is possible to completely disable the BSL in the device configuration, if desired. The BSL is enabled by default from TI to support use of the BSL for production programming. A minimum of two pins are required to use the BSL: the BSLRX and BSLTX signals (for UART), or the BSLSCL and BSLSDA signals (for I2C). Additionally, one or two additional pins (BSL_invoke and NRST) may be used for controlled invocation of the bootloader by an external host. If enabled, the BSL may be invoked (started) in the following ways: The BSL is invoked during the boot process if the BSL_invoke pin state matches the defined BSL_invoke logic level. If the device fast boot mode is enabled, this invocation check is skipped. An external host can force the device into the BSL by asserting the invoke condition and applying a reset pulse to the NRST pin to trigger a BOOTRST, after which the device will verify the invoke condition during the reboot process and start the BSL if the invoke condition matches the expected logic level. The BSL is automatically invoked during the boot process if the reset vector and stack pointer are left unprogrammed. As a result, a blank device from TI will invoke the BSL during the boot process without any need to provide a hardware invoke condition on the BSL_invoke pin. This enables production programming using just the serial interface signals. The BSL may be invoked at runtime from application software by issuing a SYSRST with BSL entry command. BSL Pin Requirements and Functions DEVICE SIGNAL CONNECTION BSL FUNCTION BSLRX Required for UART UART receive signal (RXD), an input BSLTX Required for UART UART transmit signal (TXD) an output BSLSCL Required for I2C I2C BSL clock signal (SCL) BSLSDA Required for I2C I2C BSL data signal (SDA) BSL_invoke Optional Active-high digital input used to start the BSL during boot NRST Optional Active-low reset pin used to trigger a reset and subsequent check of the invoke signal (BSL_invoke) Device Factory Constants All devices include a memory-mapped FACTORY region which provides read-only data describing the capabilities of a device as well as any factory-provided trim information for use by application software. Refer to the Factory Constants chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . DEVICEID DEVICEID address is 0x41C4.0004, PARTNUM is bit 12 to 27, MANUFACTURER is bit 1 to 11. DEVICE DEVICEID.PARTNUM DEVICEID.MANUFACTURER MSPM0L1304 0xBB82 0x17 MSPM0L1305 0xBB82 0x17 MSPM0L1306 0xBB82 0x17 USERID USERID address is 0x41C4.0008, PART is bit 0 to 15, VARIANT is bit 16 to 23 DEVICE PART VARIANT DEVICE PART VARIANT M0L1306QRHBRQ1 0xDDD3 0xC2 M0L1305QRGERQ1 0x4845 0x74 M0L1306QDGS32RQ1 0xDDD3 0xC2 M0L1305QDGS20RQ1 0x4845 0xB7 M0L1306QDGS28RQ1 0xBB70 0xC2 M0L1305QDYYRQ1 0x4845 0xEC M0L1306QRGERQ1 0xDDD3 0xC2 M0L1304QRHBRQ1 0xAA4D 0xA9 M0L1306QDGS20RQ1 0xDDD3 0x59 M0L1304QDGS32RQ1 0xAA4D 0x91 M0L1306QDYYRQ1 0xBB70 0x9F M0L1304QDGS28RQ1 0xAA4D 0xB6 M0L1305QRHBRQ1 0x4845 0x78 M0L1304QRGERQ1 0xAA4D 0x91 M0L1305QDGS32RQ1 0x4845 0x74 M0L1304QDGS20RQ1 0xAA4D 0x91 M0L1305QDGS28RQ1 0x4845 0x74 M0L1304QDYYRQ1 0xAA4D 0xA0 Identification Revision and Device Identification The hardware revision and device identification values are stored in the memory-mapped FACTORY region (see the Device Factory Constants section) which provides read-only data describing the capabilities of a device as well as any factory-provided trim information for use by application software. For more information, see the Factory Constants chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The device revision and identification information are also included as part of the top-side marking on the device package. The device-specific errata describes these markings (see ). Detailed Description The following sections describe all of the components that make up the devices in this data sheet. The peripherals integrated into these devices are configured by software through Memory Mapped Registers (MMRs). For more details, see the corresponding chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The following sections describe all of the components that make up the devices in this data sheet. The peripherals integrated into these devices are configured by software through Memory Mapped Registers (MMRs). For more details, see the corresponding chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The following sections describe all of the components that make up the devices in this data sheet. The peripherals integrated into these devices are configured by software through Memory Mapped Registers (MMRs). For more details, see the corresponding chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual CPU The CPU subsystem (MCPUSS) implements an Arm Cortex-M0+ CPU, an instruction prefetch and cache, a system timer, and interrupt management features. The Arm Cortex-M0+ is a cost-optimized 32-bit CPU that delivers high performance and low power to embedded applications. Key features of the CPU Sub System include: Arm Cortex-M0+ CPU supports clock frequencies from 32 kHz to 32 MHz ARMv6-M Thumb instruction set (little endian) with single-cycle 32×32 multiply instruction Single-cycle access to GPIO registers through Arm single-cycle IO port Prefetch logic to improve sequential code execution, and I-cache with 2 64-bit cache lines System timer (SysTick) with 24-bit down counter and automatic reload Nested vectored interrupt controller (NVIC) with 4 programmable priority levels and tail chaining Interrupt groups for expanding the total interrupt sources, with jump index for low interrupt latency CPU The CPU subsystem (MCPUSS) implements an Arm Cortex-M0+ CPU, an instruction prefetch and cache, a system timer, and interrupt management features. The Arm Cortex-M0+ is a cost-optimized 32-bit CPU that delivers high performance and low power to embedded applications. Key features of the CPU Sub System include: Arm Cortex-M0+ CPU supports clock frequencies from 32 kHz to 32 MHz ARMv6-M Thumb instruction set (little endian) with single-cycle 32×32 multiply instruction Single-cycle access to GPIO registers through Arm single-cycle IO port Prefetch logic to improve sequential code execution, and I-cache with 2 64-bit cache lines System timer (SysTick) with 24-bit down counter and automatic reload Nested vectored interrupt controller (NVIC) with 4 programmable priority levels and tail chaining Interrupt groups for expanding the total interrupt sources, with jump index for low interrupt latency The CPU subsystem (MCPUSS) implements an Arm Cortex-M0+ CPU, an instruction prefetch and cache, a system timer, and interrupt management features. The Arm Cortex-M0+ is a cost-optimized 32-bit CPU that delivers high performance and low power to embedded applications. Key features of the CPU Sub System include: Arm Cortex-M0+ CPU supports clock frequencies from 32 kHz to 32 MHz ARMv6-M Thumb instruction set (little endian) with single-cycle 32×32 multiply instruction Single-cycle access to GPIO registers through Arm single-cycle IO port Prefetch logic to improve sequential code execution, and I-cache with 2 64-bit cache lines System timer (SysTick) with 24-bit down counter and automatic reload Nested vectored interrupt controller (NVIC) with 4 programmable priority levels and tail chaining Interrupt groups for expanding the total interrupt sources, with jump index for low interrupt latency The CPU subsystem (MCPUSS) implements an Arm Cortex-M0+ CPU, an instruction prefetch and cache, a system timer, and interrupt management features. The Arm Cortex-M0+ is a cost-optimized 32-bit CPU that delivers high performance and low power to embedded applications. Key features of the CPU Sub System include: Arm Cortex-M0+ CPU supports clock frequencies from 32 kHz to 32 MHz ARMv6-M Thumb instruction set (little endian) with single-cycle 32×32 multiply instruction Single-cycle access to GPIO registers through Arm single-cycle IO port Prefetch logic to improve sequential code execution, and I-cache with 2 64-bit cache lines System timer (SysTick) with 24-bit down counter and automatic reload Nested vectored interrupt controller (NVIC) with 4 programmable priority levels and tail chaining Interrupt groups for expanding the total interrupt sources, with jump index for low interrupt latency Arm Cortex-M0+ CPU supports clock frequencies from 32 kHz to 32 MHz ARMv6-M Thumb instruction set (little endian) with single-cycle 32×32 multiply instruction Single-cycle access to GPIO registers through Arm single-cycle IO port ARMv6-M Thumb instruction set (little endian) with single-cycle 32×32 multiply instruction Single-cycle access to GPIO registers through Arm single-cycle IO port ARMv6-M Thumb instruction set (little endian) with single-cycle 32×32 multiply instructionSingle-cycle access to GPIO registers through Arm single-cycle IO portPrefetch logic to improve sequential code execution, and I-cache with 2 64-bit cache lines System timer (SysTick) with 24-bit down counter and automatic reloadNested vectored interrupt controller (NVIC) with 4 programmable priority levels and tail chainingInterrupt groups for expanding the total interrupt sources, with jump index for low interrupt latency Operating Modes MSPM0L MCUs provide five main operating modes (power modes) to allow for optimization of the device power consumption based on application requirements. In order of decreasing power, the modes are: RUN, SLEEP, STOP, STANDBY, and SHUTDOWN. The CPU is active executing code in RUN mode. Peripheral interrupt events can wake the device from SLEEP, STOP, or STANDBY mode to the RUN mode. SHUTDOWN mode completely disables the internal core regulator to minimize power consumption, and wake is only possible via NRST, SWD, or a logic level match on certain IOs. RUN, SLEEP, STOP, and STANDBY modes also include several configurable policy options (for example, RUN.x) for balancing performance with power consumption. To further balance performance and power consumption, MSPM0L devices implement two power domains: PD1 (for the CPU, memories, and high performance peripherals), and PD0 (for low speed, low power peripherals). PD1 is always powered in RUN and SLEEP modes, but is disabled in all other modes. PD0 is always powered in RUN, SLEEP, STOP, and STANDBY modes. PD1 and PD0 are both disabled in SHUTDOWN mode. Functionality by Operating Mode Supported functionality in each operating mode is given in #GUID-977123ED-F95F-428C-8E94-CA9378F25E84/GUID-1905293B-066A-4864-B43E-7BB9C5D7A0C9. Functional key: EN: The function is enabled in the specified mode. DIS: The function is disabled (either clock or power gated) in the specified mode, but the function's configuration is retained. OPT: The function is optional in the specified mode, and remains enabled if configured to be enabled. NS: The function is not automatically disabled in the specified mode, but its use is not supported. OFF: The function is fully powered off in the specified mode, and no configuration information is retained. Supported Functionality by Operating Mode Operating Mode RUN SLEEP STOP STANDBY SHUTDOWN RUN0 RUN1 RUN2 SLEEP0 SLEEP1 SLEEP2 STOP0 STOP1 STOP2 STANDBY0 STANDBY1 Oscillators SYSOSC EN EN DIS EN EN DIS OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB EN DIS DIS DIS OFF LFOSC EN OFF Clocks CPUCLK 32M 32k 32k DIS OFF MCLK to PD1 32M 32k 32k 32M 32k 32k DIS OFF ULPCLK to PD0 32M 32k 32k 32M 32k 32k 4M#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB 4M 32k DIS OFF ULPCLK to TIMG0/1 32M 32k 32k 32M 32k 32k 4M#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB 4M 32k OFF MFCLK OPT DIS OPT DIS OPT DIS OFF LFCLK 32k DIS OFF LFCLK to TIMG0/1 32k OFF MCLK Monitor OPT DIS OFF PMU POR Monitor EN BOR Monitor EN OFF Core Regulator FULL DRIVE REDUCED DRIVE LOW DRIVE OFF Core Functions CPU EN DIS OFF DMA OPT NS (triggers supported) OFF Flash EN DIS OFF SRAM EN DIS OFF PD1 Peripherals SPI0 OPT DIS OFF CRC OPT DIS OFF PD0 Peripherals TIMG0/1 OPT OFF TIMG2/4 OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF UART0/1 OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF I2C0/1 OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF GPIOA OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF WWDT0 OPT DIS OFF Analog ADC0 OPT NS (triggers supported) OFF OPA0/1 OPT NS OPT NS OPT NS OFF GPAMP OPT NS OFF COMP0 OPT OPT (ULP) OPT OPT (ULP) OPT OPT (ULP) OFF IOMUX and IO Wakeup EN DIS w/ WAKE Wake Sources N/A ANY IRQ PD0 IRQ IOMUX, NRST, SWD If STOP0 is entered from RUN1 (SYSOSC enabled but MCLK sourced from LFCLK), SYSOSC remains enabled as in RUN1 and ULPCLK remains at 32 kHz as in RUN1. If STOP0 is entered from RUN2 (SYSOSC was disabled and MCLK was sourced from LFCLK), SYSOSC remains disabled as in RUN2 and ULPCLK remains at 32 kHz as in RUN2. When using the STANDBY1 policy for STANDBY, only TIMG0 and TIMG1 are clocked. Other PD0 peripherals can generate an asynchronous fast clock request upon external activity but are not actively clocked. Operating Modes MSPM0L MCUs provide five main operating modes (power modes) to allow for optimization of the device power consumption based on application requirements. In order of decreasing power, the modes are: RUN, SLEEP, STOP, STANDBY, and SHUTDOWN. The CPU is active executing code in RUN mode. Peripheral interrupt events can wake the device from SLEEP, STOP, or STANDBY mode to the RUN mode. SHUTDOWN mode completely disables the internal core regulator to minimize power consumption, and wake is only possible via NRST, SWD, or a logic level match on certain IOs. RUN, SLEEP, STOP, and STANDBY modes also include several configurable policy options (for example, RUN.x) for balancing performance with power consumption. To further balance performance and power consumption, MSPM0L devices implement two power domains: PD1 (for the CPU, memories, and high performance peripherals), and PD0 (for low speed, low power peripherals). PD1 is always powered in RUN and SLEEP modes, but is disabled in all other modes. PD0 is always powered in RUN, SLEEP, STOP, and STANDBY modes. PD1 and PD0 are both disabled in SHUTDOWN mode. MSPM0L MCUs provide five main operating modes (power modes) to allow for optimization of the device power consumption based on application requirements. In order of decreasing power, the modes are: RUN, SLEEP, STOP, STANDBY, and SHUTDOWN. The CPU is active executing code in RUN mode. Peripheral interrupt events can wake the device from SLEEP, STOP, or STANDBY mode to the RUN mode. SHUTDOWN mode completely disables the internal core regulator to minimize power consumption, and wake is only possible via NRST, SWD, or a logic level match on certain IOs. RUN, SLEEP, STOP, and STANDBY modes also include several configurable policy options (for example, RUN.x) for balancing performance with power consumption. To further balance performance and power consumption, MSPM0L devices implement two power domains: PD1 (for the CPU, memories, and high performance peripherals), and PD0 (for low speed, low power peripherals). PD1 is always powered in RUN and SLEEP modes, but is disabled in all other modes. PD0 is always powered in RUN, SLEEP, STOP, and STANDBY modes. PD1 and PD0 are both disabled in SHUTDOWN mode. MSPM0L MCUs provide five main operating modes (power modes) to allow for optimization of the device power consumption based on application requirements. In order of decreasing power, the modes are: RUN, SLEEP, STOP, STANDBY, and SHUTDOWN. The CPU is active executing code in RUN mode. Peripheral interrupt events can wake the device from SLEEP, STOP, or STANDBY mode to the RUN mode. SHUTDOWN mode completely disables the internal core regulator to minimize power consumption, and wake is only possible via NRST, SWD, or a logic level match on certain IOs. RUN, SLEEP, STOP, and STANDBY modes also include several configurable policy options (for example, RUN.x) for balancing performance with power consumption.To further balance performance and power consumption, MSPM0L devices implement two power domains: PD1 (for the CPU, memories, and high performance peripherals), and PD0 (for low speed, low power peripherals). PD1 is always powered in RUN and SLEEP modes, but is disabled in all other modes. PD0 is always powered in RUN, SLEEP, STOP, and STANDBY modes. PD1 and PD0 are both disabled in SHUTDOWN mode. Functionality by Operating Mode Supported functionality in each operating mode is given in #GUID-977123ED-F95F-428C-8E94-CA9378F25E84/GUID-1905293B-066A-4864-B43E-7BB9C5D7A0C9. Functional key: EN: The function is enabled in the specified mode. DIS: The function is disabled (either clock or power gated) in the specified mode, but the function's configuration is retained. OPT: The function is optional in the specified mode, and remains enabled if configured to be enabled. NS: The function is not automatically disabled in the specified mode, but its use is not supported. OFF: The function is fully powered off in the specified mode, and no configuration information is retained. Supported Functionality by Operating Mode Operating Mode RUN SLEEP STOP STANDBY SHUTDOWN RUN0 RUN1 RUN2 SLEEP0 SLEEP1 SLEEP2 STOP0 STOP1 STOP2 STANDBY0 STANDBY1 Oscillators SYSOSC EN EN DIS EN EN DIS OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB EN DIS DIS DIS OFF LFOSC EN OFF Clocks CPUCLK 32M 32k 32k DIS OFF MCLK to PD1 32M 32k 32k 32M 32k 32k DIS OFF ULPCLK to PD0 32M 32k 32k 32M 32k 32k 4M#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB 4M 32k DIS OFF ULPCLK to TIMG0/1 32M 32k 32k 32M 32k 32k 4M#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB 4M 32k OFF MFCLK OPT DIS OPT DIS OPT DIS OFF LFCLK 32k DIS OFF LFCLK to TIMG0/1 32k OFF MCLK Monitor OPT DIS OFF PMU POR Monitor EN BOR Monitor EN OFF Core Regulator FULL DRIVE REDUCED DRIVE LOW DRIVE OFF Core Functions CPU EN DIS OFF DMA OPT NS (triggers supported) OFF Flash EN DIS OFF SRAM EN DIS OFF PD1 Peripherals SPI0 OPT DIS OFF CRC OPT DIS OFF PD0 Peripherals TIMG0/1 OPT OFF TIMG2/4 OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF UART0/1 OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF I2C0/1 OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF GPIOA OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF WWDT0 OPT DIS OFF Analog ADC0 OPT NS (triggers supported) OFF OPA0/1 OPT NS OPT NS OPT NS OFF GPAMP OPT NS OFF COMP0 OPT OPT (ULP) OPT OPT (ULP) OPT OPT (ULP) OFF IOMUX and IO Wakeup EN DIS w/ WAKE Wake Sources N/A ANY IRQ PD0 IRQ IOMUX, NRST, SWD If STOP0 is entered from RUN1 (SYSOSC enabled but MCLK sourced from LFCLK), SYSOSC remains enabled as in RUN1 and ULPCLK remains at 32 kHz as in RUN1. If STOP0 is entered from RUN2 (SYSOSC was disabled and MCLK was sourced from LFCLK), SYSOSC remains disabled as in RUN2 and ULPCLK remains at 32 kHz as in RUN2. When using the STANDBY1 policy for STANDBY, only TIMG0 and TIMG1 are clocked. Other PD0 peripherals can generate an asynchronous fast clock request upon external activity but are not actively clocked. Functionality by Operating Mode Supported functionality in each operating mode is given in #GUID-977123ED-F95F-428C-8E94-CA9378F25E84/GUID-1905293B-066A-4864-B43E-7BB9C5D7A0C9. Functional key: EN: The function is enabled in the specified mode. DIS: The function is disabled (either clock or power gated) in the specified mode, but the function's configuration is retained. OPT: The function is optional in the specified mode, and remains enabled if configured to be enabled. NS: The function is not automatically disabled in the specified mode, but its use is not supported. OFF: The function is fully powered off in the specified mode, and no configuration information is retained. Supported Functionality by Operating Mode Operating Mode RUN SLEEP STOP STANDBY SHUTDOWN RUN0 RUN1 RUN2 SLEEP0 SLEEP1 SLEEP2 STOP0 STOP1 STOP2 STANDBY0 STANDBY1 Oscillators SYSOSC EN EN DIS EN EN DIS OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB EN DIS DIS DIS OFF LFOSC EN OFF Clocks CPUCLK 32M 32k 32k DIS OFF MCLK to PD1 32M 32k 32k 32M 32k 32k DIS OFF ULPCLK to PD0 32M 32k 32k 32M 32k 32k 4M#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB 4M 32k DIS OFF ULPCLK to TIMG0/1 32M 32k 32k 32M 32k 32k 4M#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB 4M 32k OFF MFCLK OPT DIS OPT DIS OPT DIS OFF LFCLK 32k DIS OFF LFCLK to TIMG0/1 32k OFF MCLK Monitor OPT DIS OFF PMU POR Monitor EN BOR Monitor EN OFF Core Regulator FULL DRIVE REDUCED DRIVE LOW DRIVE OFF Core Functions CPU EN DIS OFF DMA OPT NS (triggers supported) OFF Flash EN DIS OFF SRAM EN DIS OFF PD1 Peripherals SPI0 OPT DIS OFF CRC OPT DIS OFF PD0 Peripherals TIMG0/1 OPT OFF TIMG2/4 OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF UART0/1 OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF I2C0/1 OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF GPIOA OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF WWDT0 OPT DIS OFF Analog ADC0 OPT NS (triggers supported) OFF OPA0/1 OPT NS OPT NS OPT NS OFF GPAMP OPT NS OFF COMP0 OPT OPT (ULP) OPT OPT (ULP) OPT OPT (ULP) OFF IOMUX and IO Wakeup EN DIS w/ WAKE Wake Sources N/A ANY IRQ PD0 IRQ IOMUX, NRST, SWD If STOP0 is entered from RUN1 (SYSOSC enabled but MCLK sourced from LFCLK), SYSOSC remains enabled as in RUN1 and ULPCLK remains at 32 kHz as in RUN1. If STOP0 is entered from RUN2 (SYSOSC was disabled and MCLK was sourced from LFCLK), SYSOSC remains disabled as in RUN2 and ULPCLK remains at 32 kHz as in RUN2. When using the STANDBY1 policy for STANDBY, only TIMG0 and TIMG1 are clocked. Other PD0 peripherals can generate an asynchronous fast clock request upon external activity but are not actively clocked. Supported functionality in each operating mode is given in #GUID-977123ED-F95F-428C-8E94-CA9378F25E84/GUID-1905293B-066A-4864-B43E-7BB9C5D7A0C9. Functional key: EN: The function is enabled in the specified mode. DIS: The function is disabled (either clock or power gated) in the specified mode, but the function's configuration is retained. OPT: The function is optional in the specified mode, and remains enabled if configured to be enabled. NS: The function is not automatically disabled in the specified mode, but its use is not supported. OFF: The function is fully powered off in the specified mode, and no configuration information is retained. Supported Functionality by Operating Mode Operating Mode RUN SLEEP STOP STANDBY SHUTDOWN RUN0 RUN1 RUN2 SLEEP0 SLEEP1 SLEEP2 STOP0 STOP1 STOP2 STANDBY0 STANDBY1 Oscillators SYSOSC EN EN DIS EN EN DIS OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB EN DIS DIS DIS OFF LFOSC EN OFF Clocks CPUCLK 32M 32k 32k DIS OFF MCLK to PD1 32M 32k 32k 32M 32k 32k DIS OFF ULPCLK to PD0 32M 32k 32k 32M 32k 32k 4M#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB 4M 32k DIS OFF ULPCLK to TIMG0/1 32M 32k 32k 32M 32k 32k 4M#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB 4M 32k OFF MFCLK OPT DIS OPT DIS OPT DIS OFF LFCLK 32k DIS OFF LFCLK to TIMG0/1 32k OFF MCLK Monitor OPT DIS OFF PMU POR Monitor EN BOR Monitor EN OFF Core Regulator FULL DRIVE REDUCED DRIVE LOW DRIVE OFF Core Functions CPU EN DIS OFF DMA OPT NS (triggers supported) OFF Flash EN DIS OFF SRAM EN DIS OFF PD1 Peripherals SPI0 OPT DIS OFF CRC OPT DIS OFF PD0 Peripherals TIMG0/1 OPT OFF TIMG2/4 OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF UART0/1 OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF I2C0/1 OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF GPIOA OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF WWDT0 OPT DIS OFF Analog ADC0 OPT NS (triggers supported) OFF OPA0/1 OPT NS OPT NS OPT NS OFF GPAMP OPT NS OFF COMP0 OPT OPT (ULP) OPT OPT (ULP) OPT OPT (ULP) OFF IOMUX and IO Wakeup EN DIS w/ WAKE Wake Sources N/A ANY IRQ PD0 IRQ IOMUX, NRST, SWD If STOP0 is entered from RUN1 (SYSOSC enabled but MCLK sourced from LFCLK), SYSOSC remains enabled as in RUN1 and ULPCLK remains at 32 kHz as in RUN1. If STOP0 is entered from RUN2 (SYSOSC was disabled and MCLK was sourced from LFCLK), SYSOSC remains disabled as in RUN2 and ULPCLK remains at 32 kHz as in RUN2. When using the STANDBY1 policy for STANDBY, only TIMG0 and TIMG1 are clocked. Other PD0 peripherals can generate an asynchronous fast clock request upon external activity but are not actively clocked. Supported functionality in each operating mode is given in #GUID-977123ED-F95F-428C-8E94-CA9378F25E84/GUID-1905293B-066A-4864-B43E-7BB9C5D7A0C9.#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/GUID-1905293B-066A-4864-B43E-7BB9C5D7A0C9Functional key: EN: The function is enabled in the specified mode. DIS: The function is disabled (either clock or power gated) in the specified mode, but the function's configuration is retained. OPT: The function is optional in the specified mode, and remains enabled if configured to be enabled. NS: The function is not automatically disabled in the specified mode, but its use is not supported. OFF: The function is fully powered off in the specified mode, and no configuration information is retained. EN: The function is enabled in the specified mode.EN DIS: The function is disabled (either clock or power gated) in the specified mode, but the function's configuration is retained.DIS OPT: The function is optional in the specified mode, and remains enabled if configured to be enabled.OPT NS: The function is not automatically disabled in the specified mode, but its use is not supported.NS OFF: The function is fully powered off in the specified mode, and no configuration information is retained.OFF Supported Functionality by Operating Mode Operating Mode RUN SLEEP STOP STANDBY SHUTDOWN RUN0 RUN1 RUN2 SLEEP0 SLEEP1 SLEEP2 STOP0 STOP1 STOP2 STANDBY0 STANDBY1 Oscillators SYSOSC EN EN DIS EN EN DIS OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB EN DIS DIS DIS OFF LFOSC EN OFF Clocks CPUCLK 32M 32k 32k DIS OFF MCLK to PD1 32M 32k 32k 32M 32k 32k DIS OFF ULPCLK to PD0 32M 32k 32k 32M 32k 32k 4M#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB 4M 32k DIS OFF ULPCLK to TIMG0/1 32M 32k 32k 32M 32k 32k 4M#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB 4M 32k OFF MFCLK OPT DIS OPT DIS OPT DIS OFF LFCLK 32k DIS OFF LFCLK to TIMG0/1 32k OFF MCLK Monitor OPT DIS OFF PMU POR Monitor EN BOR Monitor EN OFF Core Regulator FULL DRIVE REDUCED DRIVE LOW DRIVE OFF Core Functions CPU EN DIS OFF DMA OPT NS (triggers supported) OFF Flash EN DIS OFF SRAM EN DIS OFF PD1 Peripherals SPI0 OPT DIS OFF CRC OPT DIS OFF PD0 Peripherals TIMG0/1 OPT OFF TIMG2/4 OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF UART0/1 OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF I2C0/1 OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF GPIOA OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF WWDT0 OPT DIS OFF Analog ADC0 OPT NS (triggers supported) OFF OPA0/1 OPT NS OPT NS OPT NS OFF GPAMP OPT NS OFF COMP0 OPT OPT (ULP) OPT OPT (ULP) OPT OPT (ULP) OFF IOMUX and IO Wakeup EN DIS w/ WAKE Wake Sources N/A ANY IRQ PD0 IRQ IOMUX, NRST, SWD Supported Functionality by Operating Mode Operating Mode RUN SLEEP STOP STANDBY SHUTDOWN RUN0 RUN1 RUN2 SLEEP0 SLEEP1 SLEEP2 STOP0 STOP1 STOP2 STANDBY0 STANDBY1 Oscillators SYSOSC EN EN DIS EN EN DIS OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB EN DIS DIS DIS OFF LFOSC EN OFF Clocks CPUCLK 32M 32k 32k DIS OFF MCLK to PD1 32M 32k 32k 32M 32k 32k DIS OFF ULPCLK to PD0 32M 32k 32k 32M 32k 32k 4M#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB 4M 32k DIS OFF ULPCLK to TIMG0/1 32M 32k 32k 32M 32k 32k 4M#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB 4M 32k OFF MFCLK OPT DIS OPT DIS OPT DIS OFF LFCLK 32k DIS OFF LFCLK to TIMG0/1 32k OFF MCLK Monitor OPT DIS OFF PMU POR Monitor EN BOR Monitor EN OFF Core Regulator FULL DRIVE REDUCED DRIVE LOW DRIVE OFF Core Functions CPU EN DIS OFF DMA OPT NS (triggers supported) OFF Flash EN DIS OFF SRAM EN DIS OFF PD1 Peripherals SPI0 OPT DIS OFF CRC OPT DIS OFF PD0 Peripherals TIMG0/1 OPT OFF TIMG2/4 OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF UART0/1 OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF I2C0/1 OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF GPIOA OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF WWDT0 OPT DIS OFF Analog ADC0 OPT NS (triggers supported) OFF OPA0/1 OPT NS OPT NS OPT NS OFF GPAMP OPT NS OFF COMP0 OPT OPT (ULP) OPT OPT (ULP) OPT OPT (ULP) OFF IOMUX and IO Wakeup EN DIS w/ WAKE Wake Sources N/A ANY IRQ PD0 IRQ IOMUX, NRST, SWD Operating Mode RUN SLEEP STOP STANDBY SHUTDOWN RUN0 RUN1 RUN2 SLEEP0 SLEEP1 SLEEP2 STOP0 STOP1 STOP2 STANDBY0 STANDBY1 Operating Mode RUN SLEEP STOP STANDBY SHUTDOWN Operating ModeRUNSLEEPSTOPSTANDBYSHUTDOWN RUN0 RUN1 RUN2 SLEEP0 SLEEP1 SLEEP2 STOP0 STOP1 STOP2 STANDBY0 STANDBY1 RUN0RUN1RUN2SLEEP0SLEEP1SLEEP2STOP0STOP1STOP2STANDBY0STANDBY1 Oscillators SYSOSC EN EN DIS EN EN DIS OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB EN DIS DIS DIS OFF LFOSC EN OFF Clocks CPUCLK 32M 32k 32k DIS OFF MCLK to PD1 32M 32k 32k 32M 32k 32k DIS OFF ULPCLK to PD0 32M 32k 32k 32M 32k 32k 4M#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB 4M 32k DIS OFF ULPCLK to TIMG0/1 32M 32k 32k 32M 32k 32k 4M#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB 4M 32k OFF MFCLK OPT DIS OPT DIS OPT DIS OFF LFCLK 32k DIS OFF LFCLK to TIMG0/1 32k OFF MCLK Monitor OPT DIS OFF PMU POR Monitor EN BOR Monitor EN OFF Core Regulator FULL DRIVE REDUCED DRIVE LOW DRIVE OFF Core Functions CPU EN DIS OFF DMA OPT NS (triggers supported) OFF Flash EN DIS OFF SRAM EN DIS OFF PD1 Peripherals SPI0 OPT DIS OFF CRC OPT DIS OFF PD0 Peripherals TIMG0/1 OPT OFF TIMG2/4 OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF UART0/1 OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF I2C0/1 OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF GPIOA OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF WWDT0 OPT DIS OFF Analog ADC0 OPT NS (triggers supported) OFF OPA0/1 OPT NS OPT NS OPT NS OFF GPAMP OPT NS OFF COMP0 OPT OPT (ULP) OPT OPT (ULP) OPT OPT (ULP) OFF IOMUX and IO Wakeup EN DIS w/ WAKE Wake Sources N/A ANY IRQ PD0 IRQ IOMUX, NRST, SWD Oscillators SYSOSC EN EN DIS EN EN DIS OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB EN DIS DIS DIS OFF OscillatorsSYSOSCENENDISENENDISOPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB #GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VBENDISDISDISOFF LFOSC EN OFF LFOSCENOFF Clocks CPUCLK 32M 32k 32k DIS OFF ClocksCPUCLK32M32k32kDISOFF MCLK to PD1 32M 32k 32k 32M 32k 32k DIS OFF MCLK to PD132M32k32k32M32k32kDISOFF ULPCLK to PD0 32M 32k 32k 32M 32k 32k 4M#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB 4M 32k DIS OFF ULPCLK to PD032M32k32k32M32k32k4M#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB #GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB4M32kDISOFF ULPCLK to TIMG0/1 32M 32k 32k 32M 32k 32k 4M#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB 4M 32k OFF ULPCLK to TIMG0/132M32k32k32M32k32k4M#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB #GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_RGD_NPH_1VB4M32kOFF MFCLK OPT DIS OPT DIS OPT DIS OFF MFCLKOPTDISOPTDISOPTDISOFF LFCLK 32k DIS OFF LFCLK32kDISOFF LFCLK to TIMG0/1 32k OFF LFCLK to TIMG0/132kOFF MCLK Monitor OPT DIS OFF MCLK MonitorOPTDISOFF PMU POR Monitor EN PMUPOR MonitorEN BOR Monitor EN OFF BOR MonitorENOFF Core Regulator FULL DRIVE REDUCED DRIVE LOW DRIVE OFF Core RegulatorFULL DRIVEREDUCED DRIVELOW DRIVEOFF Core Functions CPU EN DIS OFF Core FunctionsCPUENDISOFF DMA OPT NS (triggers supported) OFF DMAOPTNS (triggers supported)OFF Flash EN DIS OFF FlashENDISOFF SRAM EN DIS OFF SRAMENDISOFF PD1 Peripherals SPI0 OPT DIS OFF PD1 PeripheralsSPI0OPTDISOFF CRC OPT DIS OFF CRCOPTDISOFF PD0 Peripherals TIMG0/1 OPT OFF PD0 PeripheralsTIMG0/1OPTOFF TIMG2/4 OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF TIMG2/4OPTOPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB #GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VBOFF UART0/1 OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF UART0/1OPTOPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB #GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VBOFF I2C0/1 OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF I2C0/1OPTOPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB #GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VBOFF GPIOA OPT OPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB OFF GPIOAOPTOPT#GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VB #GUID-977123ED-F95F-428C-8E94-CA9378F25E84/LI_WX1_NPH_1VBOFF WWDT0 OPT DIS OFF WWDT0OPTDISOFF Analog ADC0 OPT NS (triggers supported) OFF AnalogADC0OPTNS (triggers supported)OFF OPA0/1 OPT NS OPT NS OPT NS OFF OPA0/1OPTNSOPTNSOPTNSOFF GPAMP OPT NS OFF GPAMPOPTNSOFF COMP0 OPT OPT (ULP) OPT OPT (ULP) OPT OPT (ULP) OFF COMP0OPT OPT (ULP) (ULP)OPTOPT (ULP) (ULP)OPTOPT (ULP) (ULP)OFF IOMUX and IO Wakeup EN DIS w/ WAKE IOMUX and IO WakeupENDIS w/ WAKE Wake Sources N/A ANY IRQ PD0 IRQ IOMUX, NRST, SWD Wake SourcesN/AANY IRQPD0 IRQIOMUX, NRST, SWD If STOP0 is entered from RUN1 (SYSOSC enabled but MCLK sourced from LFCLK), SYSOSC remains enabled as in RUN1 and ULPCLK remains at 32 kHz as in RUN1. If STOP0 is entered from RUN2 (SYSOSC was disabled and MCLK was sourced from LFCLK), SYSOSC remains disabled as in RUN2 and ULPCLK remains at 32 kHz as in RUN2. When using the STANDBY1 policy for STANDBY, only TIMG0 and TIMG1 are clocked. Other PD0 peripherals can generate an asynchronous fast clock request upon external activity but are not actively clocked. If STOP0 is entered from RUN1 (SYSOSC enabled but MCLK sourced from LFCLK), SYSOSC remains enabled as in RUN1 and ULPCLK remains at 32 kHz as in RUN1. If STOP0 is entered from RUN2 (SYSOSC was disabled and MCLK was sourced from LFCLK), SYSOSC remains disabled as in RUN2 and ULPCLK remains at 32 kHz as in RUN2.When using the STANDBY1 policy for STANDBY, only TIMG0 and TIMG1 are clocked. Other PD0 peripherals can generate an asynchronous fast clock request upon external activity but are not actively clocked. Power Management Unit (PMU) The power management unit (PMU) generates the internally regulated core supplies for the device and provides supervision of the external supply (VDD). The PMU also contains the bandgap voltage reference used by the PMU itself as well as analog peripherals. Key features of the PMU include: Power-on reset (POR) supply monitor Brownout reset (BOR) supply monitor with early warning capability using three programmable thresholds Core regulator with support for RUN, SLEEP, STOP, and STANDBY operating modes to dynamically balance performance with power consumption Parity-protected trim to immediately generate a power-on reset (POR) in the event that a power management trim is corrupted For more details, see the PMU chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . Power Management Unit (PMU) The power management unit (PMU) generates the internally regulated core supplies for the device and provides supervision of the external supply (VDD). The PMU also contains the bandgap voltage reference used by the PMU itself as well as analog peripherals. Key features of the PMU include: Power-on reset (POR) supply monitor Brownout reset (BOR) supply monitor with early warning capability using three programmable thresholds Core regulator with support for RUN, SLEEP, STOP, and STANDBY operating modes to dynamically balance performance with power consumption Parity-protected trim to immediately generate a power-on reset (POR) in the event that a power management trim is corrupted For more details, see the PMU chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The power management unit (PMU) generates the internally regulated core supplies for the device and provides supervision of the external supply (VDD). The PMU also contains the bandgap voltage reference used by the PMU itself as well as analog peripherals. Key features of the PMU include: Power-on reset (POR) supply monitor Brownout reset (BOR) supply monitor with early warning capability using three programmable thresholds Core regulator with support for RUN, SLEEP, STOP, and STANDBY operating modes to dynamically balance performance with power consumption Parity-protected trim to immediately generate a power-on reset (POR) in the event that a power management trim is corrupted For more details, see the PMU chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The power management unit (PMU) generates the internally regulated core supplies for the device and provides supervision of the external supply (VDD). The PMU also contains the bandgap voltage reference used by the PMU itself as well as analog peripherals. Key features of the PMU include: Power-on reset (POR) supply monitor Brownout reset (BOR) supply monitor with early warning capability using three programmable thresholds Core regulator with support for RUN, SLEEP, STOP, and STANDBY operating modes to dynamically balance performance with power consumption Parity-protected trim to immediately generate a power-on reset (POR) in the event that a power management trim is corrupted Power-on reset (POR) supply monitorBrownout reset (BOR) supply monitor with early warning capability using three programmable thresholdsCore regulator with support for RUN, SLEEP, STOP, and STANDBY operating modes to dynamically balance performance with power consumptionParity-protected trim to immediately generate a power-on reset (POR) in the event that a power management trim is corruptedFor more details, see the PMU chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual Clock Module (CKM) The clock module provides the following oscillators: LFOSC: Internal low-frequency oscillator (32 kHz) SYSOSC: Internal high-frequency oscillator (4 MHz or 32 MHz with factory trim, 16 MHz or 24 MHz with user trim) The following clocks are distributed by the clock module for use by the processor, bus, and peripherals: MCLK: Main system clock for PD1 peripherals, derived from SYSOSC or LFCLK, active in RUN and SLEEP modes CPUCLK: Clock for the processor (derived from MCLK), active in RUN mode ULPCLK: Ultra-low power clock for PD0 peripherals, active in RUN, SLEEP, STOP, and STANDBY modes MFCLK: 4-MHz fixed mid-frequency clock for peripherals, available in RUN, SLEEP, and STOP modes LFCLK: 32-kHz fixed low-frequency clock for peripherals or MCLK, active in RUN, SLEEP, STOP, and STANDBY modes ADCCLK: ADC clock, available in RUN, SLEEP and STOP modes CLK_OUT: Used to output a clock externally, available in RUN, SLEEP, STOP, and STANDBY modes For more details, see the CKM chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . Clock Module (CKM) The clock module provides the following oscillators: LFOSC: Internal low-frequency oscillator (32 kHz) SYSOSC: Internal high-frequency oscillator (4 MHz or 32 MHz with factory trim, 16 MHz or 24 MHz with user trim) The following clocks are distributed by the clock module for use by the processor, bus, and peripherals: MCLK: Main system clock for PD1 peripherals, derived from SYSOSC or LFCLK, active in RUN and SLEEP modes CPUCLK: Clock for the processor (derived from MCLK), active in RUN mode ULPCLK: Ultra-low power clock for PD0 peripherals, active in RUN, SLEEP, STOP, and STANDBY modes MFCLK: 4-MHz fixed mid-frequency clock for peripherals, available in RUN, SLEEP, and STOP modes LFCLK: 32-kHz fixed low-frequency clock for peripherals or MCLK, active in RUN, SLEEP, STOP, and STANDBY modes ADCCLK: ADC clock, available in RUN, SLEEP and STOP modes CLK_OUT: Used to output a clock externally, available in RUN, SLEEP, STOP, and STANDBY modes For more details, see the CKM chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The clock module provides the following oscillators: LFOSC: Internal low-frequency oscillator (32 kHz) SYSOSC: Internal high-frequency oscillator (4 MHz or 32 MHz with factory trim, 16 MHz or 24 MHz with user trim) The following clocks are distributed by the clock module for use by the processor, bus, and peripherals: MCLK: Main system clock for PD1 peripherals, derived from SYSOSC or LFCLK, active in RUN and SLEEP modes CPUCLK: Clock for the processor (derived from MCLK), active in RUN mode ULPCLK: Ultra-low power clock for PD0 peripherals, active in RUN, SLEEP, STOP, and STANDBY modes MFCLK: 4-MHz fixed mid-frequency clock for peripherals, available in RUN, SLEEP, and STOP modes LFCLK: 32-kHz fixed low-frequency clock for peripherals or MCLK, active in RUN, SLEEP, STOP, and STANDBY modes ADCCLK: ADC clock, available in RUN, SLEEP and STOP modes CLK_OUT: Used to output a clock externally, available in RUN, SLEEP, STOP, and STANDBY modes For more details, see the CKM chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The clock module provides the following oscillators: LFOSC: Internal low-frequency oscillator (32 kHz) SYSOSC: Internal high-frequency oscillator (4 MHz or 32 MHz with factory trim, 16 MHz or 24 MHz with user trim) LFOSC: Internal low-frequency oscillator (32 kHz)LFOSC SYSOSC: Internal high-frequency oscillator (4 MHz or 32 MHz with factory trim, 16 MHz or 24 MHz with user trim)SYSOSCThe following clocks are distributed by the clock module for use by the processor, bus, and peripherals: MCLK: Main system clock for PD1 peripherals, derived from SYSOSC or LFCLK, active in RUN and SLEEP modes CPUCLK: Clock for the processor (derived from MCLK), active in RUN mode ULPCLK: Ultra-low power clock for PD0 peripherals, active in RUN, SLEEP, STOP, and STANDBY modes MFCLK: 4-MHz fixed mid-frequency clock for peripherals, available in RUN, SLEEP, and STOP modes LFCLK: 32-kHz fixed low-frequency clock for peripherals or MCLK, active in RUN, SLEEP, STOP, and STANDBY modes ADCCLK: ADC clock, available in RUN, SLEEP and STOP modes CLK_OUT: Used to output a clock externally, available in RUN, SLEEP, STOP, and STANDBY modes MCLK: Main system clock for PD1 peripherals, derived from SYSOSC or LFCLK, active in RUN and SLEEP modesMCLK CPUCLK: Clock for the processor (derived from MCLK), active in RUN modeCPUCLK ULPCLK: Ultra-low power clock for PD0 peripherals, active in RUN, SLEEP, STOP, and STANDBY modesULPCLK MFCLK: 4-MHz fixed mid-frequency clock for peripherals, available in RUN, SLEEP, and STOP modesMFCLK LFCLK: 32-kHz fixed low-frequency clock for peripherals or MCLK, active in RUN, SLEEP, STOP, and STANDBY modesLFCLK ADCCLK: ADC clock, available in RUN, SLEEP and STOP modesADCCLK CLK_OUT: Used to output a clock externally, available in RUN, SLEEP, STOP, and STANDBY modesCLK_OUTFor more details, see the CKM chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual DMA The direct memory access (DMA) controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA can be used to move data from ADC conversion memory to SRAM. The DMA reduces system power consumption by allowing the CPU to remain in low power mode, without having to awaken to move data to or from a peripheral. The DMA in these devices support the following key features: 3 independent DMA transfer channels 1 full-feature channel (DMA0), supporting repeated transfer modes 2 basic channels (DMA1, DMA2), supporting single transfer modes Configurable DMA channel priorities Byte (8-bit), short word (16-bit), word (32-bit) and long word (64-bit) or mixed byte and word transfer capability Transfer counter block size supports up to 64k transfers of any data type Configurable DMA transfer trigger selection Active channel interruption to service other channels Early interrupt generation for ping-pong buffer architecture Cascading channels upon completion of activity on another channel Stride mode to support data re-organization #GUID-2419372E-9A40-4FA9-808F-2DF8632C5F3E/TABLE_KL4_T4S_CQB lists the available triggers for the DMA which are configured using the DMATCTL.DMATSEL control bits in the DMA memory mapped registers. DMA Trigger Mapping TRIGGER 0:6 SOURCE TRIGGER 7:13 SOURCE 0 Software 7 I2C1 Publisher 2 1 Generic Subscriber 0 (FSUB_0) 8 SPI0 Publisher 1 2 Generic Subscriber 1 (FSUB_1) 9 SPI0 Publisher 2 3 ADC0 Publisher 2 10 UART0 Publisher 1 4 I2C0 Publisher 1 11 UART0 Publisher 2 5 I2C0 Publisher 2 12 UART1 Publisher 1 6 I2C1 Publisher 1 13 UART1 Publisher 2 DMA The direct memory access (DMA) controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA can be used to move data from ADC conversion memory to SRAM. The DMA reduces system power consumption by allowing the CPU to remain in low power mode, without having to awaken to move data to or from a peripheral. The DMA in these devices support the following key features: 3 independent DMA transfer channels 1 full-feature channel (DMA0), supporting repeated transfer modes 2 basic channels (DMA1, DMA2), supporting single transfer modes Configurable DMA channel priorities Byte (8-bit), short word (16-bit), word (32-bit) and long word (64-bit) or mixed byte and word transfer capability Transfer counter block size supports up to 64k transfers of any data type Configurable DMA transfer trigger selection Active channel interruption to service other channels Early interrupt generation for ping-pong buffer architecture Cascading channels upon completion of activity on another channel Stride mode to support data re-organization #GUID-2419372E-9A40-4FA9-808F-2DF8632C5F3E/TABLE_KL4_T4S_CQB lists the available triggers for the DMA which are configured using the DMATCTL.DMATSEL control bits in the DMA memory mapped registers. DMA Trigger Mapping TRIGGER 0:6 SOURCE TRIGGER 7:13 SOURCE 0 Software 7 I2C1 Publisher 2 1 Generic Subscriber 0 (FSUB_0) 8 SPI0 Publisher 1 2 Generic Subscriber 1 (FSUB_1) 9 SPI0 Publisher 2 3 ADC0 Publisher 2 10 UART0 Publisher 1 4 I2C0 Publisher 1 11 UART0 Publisher 2 5 I2C0 Publisher 2 12 UART1 Publisher 1 6 I2C1 Publisher 1 13 UART1 Publisher 2 The direct memory access (DMA) controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA can be used to move data from ADC conversion memory to SRAM. The DMA reduces system power consumption by allowing the CPU to remain in low power mode, without having to awaken to move data to or from a peripheral. The DMA in these devices support the following key features: 3 independent DMA transfer channels 1 full-feature channel (DMA0), supporting repeated transfer modes 2 basic channels (DMA1, DMA2), supporting single transfer modes Configurable DMA channel priorities Byte (8-bit), short word (16-bit), word (32-bit) and long word (64-bit) or mixed byte and word transfer capability Transfer counter block size supports up to 64k transfers of any data type Configurable DMA transfer trigger selection Active channel interruption to service other channels Early interrupt generation for ping-pong buffer architecture Cascading channels upon completion of activity on another channel Stride mode to support data re-organization #GUID-2419372E-9A40-4FA9-808F-2DF8632C5F3E/TABLE_KL4_T4S_CQB lists the available triggers for the DMA which are configured using the DMATCTL.DMATSEL control bits in the DMA memory mapped registers. DMA Trigger Mapping TRIGGER 0:6 SOURCE TRIGGER 7:13 SOURCE 0 Software 7 I2C1 Publisher 2 1 Generic Subscriber 0 (FSUB_0) 8 SPI0 Publisher 1 2 Generic Subscriber 1 (FSUB_1) 9 SPI0 Publisher 2 3 ADC0 Publisher 2 10 UART0 Publisher 1 4 I2C0 Publisher 1 11 UART0 Publisher 2 5 I2C0 Publisher 2 12 UART1 Publisher 1 6 I2C1 Publisher 1 13 UART1 Publisher 2 The direct memory access (DMA) controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA can be used to move data from ADC conversion memory to SRAM. The DMA reduces system power consumption by allowing the CPU to remain in low power mode, without having to awaken to move data to or from a peripheral.The DMA in these devices support the following key features: 3 independent DMA transfer channels 1 full-feature channel (DMA0), supporting repeated transfer modes 2 basic channels (DMA1, DMA2), supporting single transfer modes Configurable DMA channel priorities Byte (8-bit), short word (16-bit), word (32-bit) and long word (64-bit) or mixed byte and word transfer capability Transfer counter block size supports up to 64k transfers of any data type Configurable DMA transfer trigger selection Active channel interruption to service other channels Early interrupt generation for ping-pong buffer architecture Cascading channels upon completion of activity on another channel Stride mode to support data re-organization 3 independent DMA transfer channels 1 full-feature channel (DMA0), supporting repeated transfer modes 2 basic channels (DMA1, DMA2), supporting single transfer modes Configurable DMA channel priorities Byte (8-bit), short word (16-bit), word (32-bit) and long word (64-bit) or mixed byte and word transfer capability Transfer counter block size supports up to 64k transfers of any data type Configurable DMA transfer trigger selection Active channel interruption to service other channels Early interrupt generation for ping-pong buffer architecture Cascading channels upon completion of activity on another channel Stride mode to support data re-organization 3 independent DMA transfer channels 1 full-feature channel (DMA0), supporting repeated transfer modes 2 basic channels (DMA1, DMA2), supporting single transfer modes 1 full-feature channel (DMA0), supporting repeated transfer modes 2 basic channels (DMA1, DMA2), supporting single transfer modes 1 full-feature channel (DMA0), supporting repeated transfer modes2 basic channels (DMA1, DMA2), supporting single transfer modesConfigurable DMA channel prioritiesByte (8-bit), short word (16-bit), word (32-bit) and long word (64-bit) or mixed byte and word transfer capabilityTransfer counter block size supports up to 64k transfers of any data typeConfigurable DMA transfer trigger selectionActive channel interruption to service other channelsEarly interrupt generation for ping-pong buffer architectureCascading channels upon completion of activity on another channelStride mode to support data re-organization #GUID-2419372E-9A40-4FA9-808F-2DF8632C5F3E/TABLE_KL4_T4S_CQB lists the available triggers for the DMA which are configured using the DMATCTL.DMATSEL control bits in the DMA memory mapped registers.#GUID-2419372E-9A40-4FA9-808F-2DF8632C5F3E/TABLE_KL4_T4S_CQB DMA Trigger Mapping TRIGGER 0:6 SOURCE TRIGGER 7:13 SOURCE 0 Software 7 I2C1 Publisher 2 1 Generic Subscriber 0 (FSUB_0) 8 SPI0 Publisher 1 2 Generic Subscriber 1 (FSUB_1) 9 SPI0 Publisher 2 3 ADC0 Publisher 2 10 UART0 Publisher 1 4 I2C0 Publisher 1 11 UART0 Publisher 2 5 I2C0 Publisher 2 12 UART1 Publisher 1 6 I2C1 Publisher 1 13 UART1 Publisher 2 DMA Trigger Mapping TRIGGER 0:6 SOURCE TRIGGER 7:13 SOURCE 0 Software 7 I2C1 Publisher 2 1 Generic Subscriber 0 (FSUB_0) 8 SPI0 Publisher 1 2 Generic Subscriber 1 (FSUB_1) 9 SPI0 Publisher 2 3 ADC0 Publisher 2 10 UART0 Publisher 1 4 I2C0 Publisher 1 11 UART0 Publisher 2 5 I2C0 Publisher 2 12 UART1 Publisher 1 6 I2C1 Publisher 1 13 UART1 Publisher 2 TRIGGER 0:6 SOURCE TRIGGER 7:13 SOURCE TRIGGER 0:6 SOURCE TRIGGER 7:13 SOURCE TRIGGER 0:6SOURCETRIGGER 7:13SOURCE 0 Software 7 I2C1 Publisher 2 1 Generic Subscriber 0 (FSUB_0) 8 SPI0 Publisher 1 2 Generic Subscriber 1 (FSUB_1) 9 SPI0 Publisher 2 3 ADC0 Publisher 2 10 UART0 Publisher 1 4 I2C0 Publisher 1 11 UART0 Publisher 2 5 I2C0 Publisher 2 12 UART1 Publisher 1 6 I2C1 Publisher 1 13 UART1 Publisher 2 0 Software 7 I2C1 Publisher 2 0Software7I2C1 Publisher 2 1 Generic Subscriber 0 (FSUB_0) 8 SPI0 Publisher 1 1Generic Subscriber 0 (FSUB_0)8SPI0 Publisher 1 2 Generic Subscriber 1 (FSUB_1) 9 SPI0 Publisher 2 2Generic Subscriber 1 (FSUB_1)9SPI0 Publisher 2 3 ADC0 Publisher 2 10 UART0 Publisher 1 3ADC0 Publisher 210UART0 Publisher 1 4 I2C0 Publisher 1 11 UART0 Publisher 2 4I2C0 Publisher 111UART0 Publisher 2 5 I2C0 Publisher 2 12 UART1 Publisher 1 5I2C0 Publisher 212UART1 Publisher 1 6 I2C1 Publisher 1 13 UART1 Publisher 2 6I2C1 Publisher 113UART1 Publisher 2 Events The event manager transfers digital events from one entity (for example, a peripheral) to another (for example, a second peripheral, the DMA or the CPU). The event manager implements event transfer through a defined set of event publishers (generators) and subscribers (receivers) that are interconnected through an event fabric containing a combination of static and programmable routes. Events that are transferred by the event manager include: Peripheral event transferred to the CPU as an interrupt request (IRQ) (Static Event) Example: GPIO interrupt is sent to the CPU Peripheral event transferred to the DMA as a DMA trigger (DMA Event) Example: UART data receive trigger to DMA to request a DMA transfer Peripheral event transferred to another peripheral to directly trigger an action in hardware (Generic Event) Example: TIMx timer peripheral publishes a periodic event to the ADC subscriber port, and the ADC uses the event to trigger start-of-sampling For more details, see the Event chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . Generic Event Channels A generic route is either a point-to-point (1:1) route or a point-to-two (1:2) splitter route in which the peripheral publishing the event is configured to use one of several available generic route channels to publish the event to another entity (or entities, in the case of a splitter route). An entity can be another peripheral, a generic DMA trigger event, or a generic CPU event. CHANID Generic Route Channel Selection Channel Type 0 No generic event channel selected N/A 1 Generic event channel 1 selected 1 : 1 2 Generic event channel 2 selected 1 : 1 3 Generic event channel 3 selected 1 : 2 (splitter) Events The event manager transfers digital events from one entity (for example, a peripheral) to another (for example, a second peripheral, the DMA or the CPU). The event manager implements event transfer through a defined set of event publishers (generators) and subscribers (receivers) that are interconnected through an event fabric containing a combination of static and programmable routes. Events that are transferred by the event manager include: Peripheral event transferred to the CPU as an interrupt request (IRQ) (Static Event) Example: GPIO interrupt is sent to the CPU Peripheral event transferred to the DMA as a DMA trigger (DMA Event) Example: UART data receive trigger to DMA to request a DMA transfer Peripheral event transferred to another peripheral to directly trigger an action in hardware (Generic Event) Example: TIMx timer peripheral publishes a periodic event to the ADC subscriber port, and the ADC uses the event to trigger start-of-sampling For more details, see the Event chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . Generic Event Channels A generic route is either a point-to-point (1:1) route or a point-to-two (1:2) splitter route in which the peripheral publishing the event is configured to use one of several available generic route channels to publish the event to another entity (or entities, in the case of a splitter route). An entity can be another peripheral, a generic DMA trigger event, or a generic CPU event. CHANID Generic Route Channel Selection Channel Type 0 No generic event channel selected N/A 1 Generic event channel 1 selected 1 : 1 2 Generic event channel 2 selected 1 : 1 3 Generic event channel 3 selected 1 : 2 (splitter) The event manager transfers digital events from one entity (for example, a peripheral) to another (for example, a second peripheral, the DMA or the CPU). The event manager implements event transfer through a defined set of event publishers (generators) and subscribers (receivers) that are interconnected through an event fabric containing a combination of static and programmable routes. Events that are transferred by the event manager include: Peripheral event transferred to the CPU as an interrupt request (IRQ) (Static Event) Example: GPIO interrupt is sent to the CPU Peripheral event transferred to the DMA as a DMA trigger (DMA Event) Example: UART data receive trigger to DMA to request a DMA transfer Peripheral event transferred to another peripheral to directly trigger an action in hardware (Generic Event) Example: TIMx timer peripheral publishes a periodic event to the ADC subscriber port, and the ADC uses the event to trigger start-of-sampling For more details, see the Event chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . Generic Event Channels A generic route is either a point-to-point (1:1) route or a point-to-two (1:2) splitter route in which the peripheral publishing the event is configured to use one of several available generic route channels to publish the event to another entity (or entities, in the case of a splitter route). An entity can be another peripheral, a generic DMA trigger event, or a generic CPU event. CHANID Generic Route Channel Selection Channel Type 0 No generic event channel selected N/A 1 Generic event channel 1 selected 1 : 1 2 Generic event channel 2 selected 1 : 1 3 Generic event channel 3 selected 1 : 2 (splitter) The event manager transfers digital events from one entity (for example, a peripheral) to another (for example, a second peripheral, the DMA or the CPU). The event manager implements event transfer through a defined set of event publishers (generators) and subscribers (receivers) that are interconnected through an event fabric containing a combination of static and programmable routes.Events that are transferred by the event manager include: Peripheral event transferred to the CPU as an interrupt request (IRQ) (Static Event) Example: GPIO interrupt is sent to the CPU Peripheral event transferred to the DMA as a DMA trigger (DMA Event) Example: UART data receive trigger to DMA to request a DMA transfer Peripheral event transferred to another peripheral to directly trigger an action in hardware (Generic Event) Example: TIMx timer peripheral publishes a periodic event to the ADC subscriber port, and the ADC uses the event to trigger start-of-sampling Peripheral event transferred to the CPU as an interrupt request (IRQ) (Static Event) Example: GPIO interrupt is sent to the CPU Peripheral event transferred to the DMA as a DMA trigger (DMA Event) Example: UART data receive trigger to DMA to request a DMA transfer Peripheral event transferred to another peripheral to directly trigger an action in hardware (Generic Event) Example: TIMx timer peripheral publishes a periodic event to the ADC subscriber port, and the ADC uses the event to trigger start-of-sampling Peripheral event transferred to the CPU as an interrupt request (IRQ) (Static Event) Example: GPIO interrupt is sent to the CPU Example: GPIO interrupt is sent to the CPU Example: GPIO interrupt is sent to the CPUPeripheral event transferred to the DMA as a DMA trigger (DMA Event) Example: UART data receive trigger to DMA to request a DMA transfer Example: UART data receive trigger to DMA to request a DMA transfer Example: UART data receive trigger to DMA to request a DMA transferPeripheral event transferred to another peripheral to directly trigger an action in hardware (Generic Event) Example: TIMx timer peripheral publishes a periodic event to the ADC subscriber port, and the ADC uses the event to trigger start-of-sampling Example: TIMx timer peripheral publishes a periodic event to the ADC subscriber port, and the ADC uses the event to trigger start-of-sampling Example: TIMx timer peripheral publishes a periodic event to the ADC subscriber port, and the ADC uses the event to trigger start-of-samplingFor more details, see the Event chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual Generic Event Channels A generic route is either a point-to-point (1:1) route or a point-to-two (1:2) splitter route in which the peripheral publishing the event is configured to use one of several available generic route channels to publish the event to another entity (or entities, in the case of a splitter route). An entity can be another peripheral, a generic DMA trigger event, or a generic CPU event. CHANID Generic Route Channel Selection Channel Type 0 No generic event channel selected N/A 1 Generic event channel 1 selected 1 : 1 2 Generic event channel 2 selected 1 : 1 3 Generic event channel 3 selected 1 : 2 (splitter) Generic Event ChannelsA generic route is either a point-to-point (1:1) route or a point-to-two (1:2) splitter route in which the peripheral publishing the event is configured to use one of several available generic route channels to publish the event to another entity (or entities, in the case of a splitter route). An entity can be another peripheral, a generic DMA trigger event, or a generic CPU event. CHANID Generic Route Channel Selection Channel Type 0 No generic event channel selected N/A 1 Generic event channel 1 selected 1 : 1 2 Generic event channel 2 selected 1 : 1 3 Generic event channel 3 selected 1 : 2 (splitter) CHANID Generic Route Channel Selection Channel Type CHANID Generic Route Channel Selection Channel Type CHANIDGeneric Route Channel SelectionChannel Type 0 No generic event channel selected N/A 1 Generic event channel 1 selected 1 : 1 2 Generic event channel 2 selected 1 : 1 3 Generic event channel 3 selected 1 : 2 (splitter) 0 No generic event channel selected N/A 0No generic event channel selectedN/A 1 Generic event channel 1 selected 1 : 1 1Generic event channel 1 selected1 : 1 2 Generic event channel 2 selected 1 : 1 2Generic event channel 2 selected1 : 1 3 Generic event channel 3 selected 1 : 2 (splitter) 3Generic event channel 3 selected1 : 2 (splitter) Memory Memory Organization The following table summarizes the memory map of the devices. For more information about the memory region detail, see the Platform Memory Map chapter in the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . Memory Organization Memory Region Subregion MSPM0L1304 MSPM0L1305 MSPM0L1306 Code (Flash) MAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 16KB - 8B0x0000.0000 to 0x0000.3FF8 32KB - 8B#GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC 0x0000.0000 to 0x0000.7FF8 64KB - 8B#GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC 0x0000.0000 to 0x0000.FFF8 Aliased MAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 0x0040.0000 to 0x0040.3FF8 0x0040.0000 to 0x0040.7FF8 0x0040.0000 to 0x0040.FFF8 SRAM (SRAM) SRAM 2KB0x2000.0000 to 0x2000.0800 4KB0x2000.0000 to 0x2000.1000 4KB0x2000.0000 to 0x2000.1000 Aliased SRAM#GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE 0x2000.0000 to 0x2000.0800 0x2000.0000 to 0x2000.1000 0x2000.0000 to 0x2000.1000 Peripheral Peripherals 0x4000.0000 to 0x40FF.FFFF 0x4000.0000 to 0x40FF.FFFF 0x4000.0000 to 0x40FF.FFFF MAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 0x0000.0000 to 0x0000.3FF8 0x0000.0000 to 0x0000.7FF8 0x0000.0000 to 0x0000.FFF8 Aliased MAIN#GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 0x0040.0000 to 0x0040.3FF8 0x0040.0000 to 0x0040.7FF8 0x0040.0000 to 0x0040.FFF8 NONMAIN 512 bytes0x41C0.0000 to 0x41C0.0200 512 bytes0x41C0.0000 to 0x41C0.0200 512 bytes0x41C0.0000 to 0x41C0.0200 Aliased NONMAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE 0x41C1.0000 to 0x41C1.0200 0x41C1.0000 to 0x41C1.0200 0x41C1.0000 to 0x41C1.0200 FACTORY 0x41C4.0000 to 0x41C4.0080 0x41C4.0000 to 0x41C4.0080 0x41C4.0000 to 0x41C4.0080 Aliased FACTORY #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE 0x41C5.0000 to 0x41C5.0080 0x41C5.0000 to 0x41C5.0080 0x41C5.0000 to 0x41C5.0080 Subsystem 0x6000.0000 to 0x7FFF.FFFF 0x6000.0000 to 0x7FFF.FFFF 0x6000.0000 to 0x7FFF.FFFF System PPB 0xE000.0000 to 0xE00F.FFFF 0xE000.0000 to 0xE00F.FFFF 0xE000.0000 to 0xE00F.FFFF First 32KB flash memory (address 0x0000.0000 to 0x0000.8000) has up to 100000 program and erase cycles. Aliased memory reads the same as the corresponding memory region. Aliased memory is included to keep the compatibility with devices that have ECC. CPU access to one of the last 8 bytes of a flash region will cause a hard fault. This occurs because the prefetch logic tries to read one flash word (64 bits) ahead, resulting in a read attempt to an invalid memory location. Peripheral File Map #GUID-75EA9B50-3030-49EE-B191-0EF3DCD84C4A/TABLE_AXS_5GM_CRB lists the available peripherals and the register base address for each. Peripherals Summary Peripheral Name Base Address Size ADC0 0x40004000 0x2000 COMP0 0x40008000 0x2000 OPA0 0x40020000 0x2000 OPA1 0x40022000 0x2000 VREF 0x40030000 0x2000 WWDT0 0x40080000 0x2000 TIMG0 0x40084000 0x2000 TIMG1 0x40086000 0x2000 TIMG2 0x40088000 0x2000 TIMG4 0x4008C000 0x2000 GPIO0 0x400A0000 0x2000 SYSCTL 0x400AF000 0x3000 DEBUGSS 0x400C7000 0x2000 EVENT 0x400C9000 0x3000 NVMNW 0x400CD000 0x2000 I2C0 0x400F0000 0x2000 I2C1 0x400F2000 0x2000 UART1 0x40100000 0x2000 UART0 0x40108000 0x2000 MCPUSS 0x40400000 0x2000 WUC 0x40424000 0x1000 IOMUX 0x40428000 0x2000 DMA 0x4042A000 0x2000 CRC 0x40440000 0x2000 SPI0 0x40468000 0x2000 ADC0 (1) 0x4055A000 0x1000 (1) Aliased region of ADC0 memory-mapped registers. Peripheral Interrupt Vector #GUID-E85B0824-C3C2-42E1-ABB9-E274B22E95FC/TABLE_AXS_5GM_CRB shows the IRQ number and the interrupt group number for each peripherals in this device. Interrupt Vector Number Peripheral Name NVIC IRQ Group IIDX WWDT0 0 0 DEBUGSS 0 2 NVMNW 0 3 EVENT SUB PORT0 0 4 EVENT SUB PORT1 0 5 SYSCTL 0 6 GPIO0 1 0 COMP0 1 2 TIMG1 2 – ADC 4 – SPI0 9 – UART1 13 – UART0 15 – TIMG0 16 – TIMG2 18 – TIMG4 20 – I2C0 24 – I2C1 25 – DMA 31 – Memory Memory Organization The following table summarizes the memory map of the devices. For more information about the memory region detail, see the Platform Memory Map chapter in the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . Memory Organization Memory Region Subregion MSPM0L1304 MSPM0L1305 MSPM0L1306 Code (Flash) MAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 16KB - 8B0x0000.0000 to 0x0000.3FF8 32KB - 8B#GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC 0x0000.0000 to 0x0000.7FF8 64KB - 8B#GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC 0x0000.0000 to 0x0000.FFF8 Aliased MAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 0x0040.0000 to 0x0040.3FF8 0x0040.0000 to 0x0040.7FF8 0x0040.0000 to 0x0040.FFF8 SRAM (SRAM) SRAM 2KB0x2000.0000 to 0x2000.0800 4KB0x2000.0000 to 0x2000.1000 4KB0x2000.0000 to 0x2000.1000 Aliased SRAM#GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE 0x2000.0000 to 0x2000.0800 0x2000.0000 to 0x2000.1000 0x2000.0000 to 0x2000.1000 Peripheral Peripherals 0x4000.0000 to 0x40FF.FFFF 0x4000.0000 to 0x40FF.FFFF 0x4000.0000 to 0x40FF.FFFF MAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 0x0000.0000 to 0x0000.3FF8 0x0000.0000 to 0x0000.7FF8 0x0000.0000 to 0x0000.FFF8 Aliased MAIN#GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 0x0040.0000 to 0x0040.3FF8 0x0040.0000 to 0x0040.7FF8 0x0040.0000 to 0x0040.FFF8 NONMAIN 512 bytes0x41C0.0000 to 0x41C0.0200 512 bytes0x41C0.0000 to 0x41C0.0200 512 bytes0x41C0.0000 to 0x41C0.0200 Aliased NONMAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE 0x41C1.0000 to 0x41C1.0200 0x41C1.0000 to 0x41C1.0200 0x41C1.0000 to 0x41C1.0200 FACTORY 0x41C4.0000 to 0x41C4.0080 0x41C4.0000 to 0x41C4.0080 0x41C4.0000 to 0x41C4.0080 Aliased FACTORY #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE 0x41C5.0000 to 0x41C5.0080 0x41C5.0000 to 0x41C5.0080 0x41C5.0000 to 0x41C5.0080 Subsystem 0x6000.0000 to 0x7FFF.FFFF 0x6000.0000 to 0x7FFF.FFFF 0x6000.0000 to 0x7FFF.FFFF System PPB 0xE000.0000 to 0xE00F.FFFF 0xE000.0000 to 0xE00F.FFFF 0xE000.0000 to 0xE00F.FFFF First 32KB flash memory (address 0x0000.0000 to 0x0000.8000) has up to 100000 program and erase cycles. Aliased memory reads the same as the corresponding memory region. Aliased memory is included to keep the compatibility with devices that have ECC. CPU access to one of the last 8 bytes of a flash region will cause a hard fault. This occurs because the prefetch logic tries to read one flash word (64 bits) ahead, resulting in a read attempt to an invalid memory location. Memory Organization The following table summarizes the memory map of the devices. For more information about the memory region detail, see the Platform Memory Map chapter in the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . Memory Organization Memory Region Subregion MSPM0L1304 MSPM0L1305 MSPM0L1306 Code (Flash) MAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 16KB - 8B0x0000.0000 to 0x0000.3FF8 32KB - 8B#GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC 0x0000.0000 to 0x0000.7FF8 64KB - 8B#GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC 0x0000.0000 to 0x0000.FFF8 Aliased MAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 0x0040.0000 to 0x0040.3FF8 0x0040.0000 to 0x0040.7FF8 0x0040.0000 to 0x0040.FFF8 SRAM (SRAM) SRAM 2KB0x2000.0000 to 0x2000.0800 4KB0x2000.0000 to 0x2000.1000 4KB0x2000.0000 to 0x2000.1000 Aliased SRAM#GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE 0x2000.0000 to 0x2000.0800 0x2000.0000 to 0x2000.1000 0x2000.0000 to 0x2000.1000 Peripheral Peripherals 0x4000.0000 to 0x40FF.FFFF 0x4000.0000 to 0x40FF.FFFF 0x4000.0000 to 0x40FF.FFFF MAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 0x0000.0000 to 0x0000.3FF8 0x0000.0000 to 0x0000.7FF8 0x0000.0000 to 0x0000.FFF8 Aliased MAIN#GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 0x0040.0000 to 0x0040.3FF8 0x0040.0000 to 0x0040.7FF8 0x0040.0000 to 0x0040.FFF8 NONMAIN 512 bytes0x41C0.0000 to 0x41C0.0200 512 bytes0x41C0.0000 to 0x41C0.0200 512 bytes0x41C0.0000 to 0x41C0.0200 Aliased NONMAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE 0x41C1.0000 to 0x41C1.0200 0x41C1.0000 to 0x41C1.0200 0x41C1.0000 to 0x41C1.0200 FACTORY 0x41C4.0000 to 0x41C4.0080 0x41C4.0000 to 0x41C4.0080 0x41C4.0000 to 0x41C4.0080 Aliased FACTORY #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE 0x41C5.0000 to 0x41C5.0080 0x41C5.0000 to 0x41C5.0080 0x41C5.0000 to 0x41C5.0080 Subsystem 0x6000.0000 to 0x7FFF.FFFF 0x6000.0000 to 0x7FFF.FFFF 0x6000.0000 to 0x7FFF.FFFF System PPB 0xE000.0000 to 0xE00F.FFFF 0xE000.0000 to 0xE00F.FFFF 0xE000.0000 to 0xE00F.FFFF First 32KB flash memory (address 0x0000.0000 to 0x0000.8000) has up to 100000 program and erase cycles. Aliased memory reads the same as the corresponding memory region. Aliased memory is included to keep the compatibility with devices that have ECC. CPU access to one of the last 8 bytes of a flash region will cause a hard fault. This occurs because the prefetch logic tries to read one flash word (64 bits) ahead, resulting in a read attempt to an invalid memory location. The following table summarizes the memory map of the devices. For more information about the memory region detail, see the Platform Memory Map chapter in the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . Memory Organization Memory Region Subregion MSPM0L1304 MSPM0L1305 MSPM0L1306 Code (Flash) MAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 16KB - 8B0x0000.0000 to 0x0000.3FF8 32KB - 8B#GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC 0x0000.0000 to 0x0000.7FF8 64KB - 8B#GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC 0x0000.0000 to 0x0000.FFF8 Aliased MAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 0x0040.0000 to 0x0040.3FF8 0x0040.0000 to 0x0040.7FF8 0x0040.0000 to 0x0040.FFF8 SRAM (SRAM) SRAM 2KB0x2000.0000 to 0x2000.0800 4KB0x2000.0000 to 0x2000.1000 4KB0x2000.0000 to 0x2000.1000 Aliased SRAM#GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE 0x2000.0000 to 0x2000.0800 0x2000.0000 to 0x2000.1000 0x2000.0000 to 0x2000.1000 Peripheral Peripherals 0x4000.0000 to 0x40FF.FFFF 0x4000.0000 to 0x40FF.FFFF 0x4000.0000 to 0x40FF.FFFF MAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 0x0000.0000 to 0x0000.3FF8 0x0000.0000 to 0x0000.7FF8 0x0000.0000 to 0x0000.FFF8 Aliased MAIN#GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 0x0040.0000 to 0x0040.3FF8 0x0040.0000 to 0x0040.7FF8 0x0040.0000 to 0x0040.FFF8 NONMAIN 512 bytes0x41C0.0000 to 0x41C0.0200 512 bytes0x41C0.0000 to 0x41C0.0200 512 bytes0x41C0.0000 to 0x41C0.0200 Aliased NONMAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE 0x41C1.0000 to 0x41C1.0200 0x41C1.0000 to 0x41C1.0200 0x41C1.0000 to 0x41C1.0200 FACTORY 0x41C4.0000 to 0x41C4.0080 0x41C4.0000 to 0x41C4.0080 0x41C4.0000 to 0x41C4.0080 Aliased FACTORY #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE 0x41C5.0000 to 0x41C5.0080 0x41C5.0000 to 0x41C5.0080 0x41C5.0000 to 0x41C5.0080 Subsystem 0x6000.0000 to 0x7FFF.FFFF 0x6000.0000 to 0x7FFF.FFFF 0x6000.0000 to 0x7FFF.FFFF System PPB 0xE000.0000 to 0xE00F.FFFF 0xE000.0000 to 0xE00F.FFFF 0xE000.0000 to 0xE00F.FFFF First 32KB flash memory (address 0x0000.0000 to 0x0000.8000) has up to 100000 program and erase cycles. Aliased memory reads the same as the corresponding memory region. Aliased memory is included to keep the compatibility with devices that have ECC. CPU access to one of the last 8 bytes of a flash region will cause a hard fault. This occurs because the prefetch logic tries to read one flash word (64 bits) ahead, resulting in a read attempt to an invalid memory location. The following table summarizes the memory map of the devices. For more information about the memory region detail, see the Platform Memory Map chapter in the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual .Platform Memory Map MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual Memory Organization Memory Region Subregion MSPM0L1304 MSPM0L1305 MSPM0L1306 Code (Flash) MAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 16KB - 8B0x0000.0000 to 0x0000.3FF8 32KB - 8B#GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC 0x0000.0000 to 0x0000.7FF8 64KB - 8B#GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC 0x0000.0000 to 0x0000.FFF8 Aliased MAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 0x0040.0000 to 0x0040.3FF8 0x0040.0000 to 0x0040.7FF8 0x0040.0000 to 0x0040.FFF8 SRAM (SRAM) SRAM 2KB0x2000.0000 to 0x2000.0800 4KB0x2000.0000 to 0x2000.1000 4KB0x2000.0000 to 0x2000.1000 Aliased SRAM#GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE 0x2000.0000 to 0x2000.0800 0x2000.0000 to 0x2000.1000 0x2000.0000 to 0x2000.1000 Peripheral Peripherals 0x4000.0000 to 0x40FF.FFFF 0x4000.0000 to 0x40FF.FFFF 0x4000.0000 to 0x40FF.FFFF MAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 0x0000.0000 to 0x0000.3FF8 0x0000.0000 to 0x0000.7FF8 0x0000.0000 to 0x0000.FFF8 Aliased MAIN#GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 0x0040.0000 to 0x0040.3FF8 0x0040.0000 to 0x0040.7FF8 0x0040.0000 to 0x0040.FFF8 NONMAIN 512 bytes0x41C0.0000 to 0x41C0.0200 512 bytes0x41C0.0000 to 0x41C0.0200 512 bytes0x41C0.0000 to 0x41C0.0200 Aliased NONMAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE 0x41C1.0000 to 0x41C1.0200 0x41C1.0000 to 0x41C1.0200 0x41C1.0000 to 0x41C1.0200 FACTORY 0x41C4.0000 to 0x41C4.0080 0x41C4.0000 to 0x41C4.0080 0x41C4.0000 to 0x41C4.0080 Aliased FACTORY #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE 0x41C5.0000 to 0x41C5.0080 0x41C5.0000 to 0x41C5.0080 0x41C5.0000 to 0x41C5.0080 Subsystem 0x6000.0000 to 0x7FFF.FFFF 0x6000.0000 to 0x7FFF.FFFF 0x6000.0000 to 0x7FFF.FFFF System PPB 0xE000.0000 to 0xE00F.FFFF 0xE000.0000 to 0xE00F.FFFF 0xE000.0000 to 0xE00F.FFFF Memory Organization Memory Region Subregion MSPM0L1304 MSPM0L1305 MSPM0L1306 Code (Flash) MAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 16KB - 8B0x0000.0000 to 0x0000.3FF8 32KB - 8B#GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC 0x0000.0000 to 0x0000.7FF8 64KB - 8B#GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC 0x0000.0000 to 0x0000.FFF8 Aliased MAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 0x0040.0000 to 0x0040.3FF8 0x0040.0000 to 0x0040.7FF8 0x0040.0000 to 0x0040.FFF8 SRAM (SRAM) SRAM 2KB0x2000.0000 to 0x2000.0800 4KB0x2000.0000 to 0x2000.1000 4KB0x2000.0000 to 0x2000.1000 Aliased SRAM#GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE 0x2000.0000 to 0x2000.0800 0x2000.0000 to 0x2000.1000 0x2000.0000 to 0x2000.1000 Peripheral Peripherals 0x4000.0000 to 0x40FF.FFFF 0x4000.0000 to 0x40FF.FFFF 0x4000.0000 to 0x40FF.FFFF MAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 0x0000.0000 to 0x0000.3FF8 0x0000.0000 to 0x0000.7FF8 0x0000.0000 to 0x0000.FFF8 Aliased MAIN#GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 0x0040.0000 to 0x0040.3FF8 0x0040.0000 to 0x0040.7FF8 0x0040.0000 to 0x0040.FFF8 NONMAIN 512 bytes0x41C0.0000 to 0x41C0.0200 512 bytes0x41C0.0000 to 0x41C0.0200 512 bytes0x41C0.0000 to 0x41C0.0200 Aliased NONMAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE 0x41C1.0000 to 0x41C1.0200 0x41C1.0000 to 0x41C1.0200 0x41C1.0000 to 0x41C1.0200 FACTORY 0x41C4.0000 to 0x41C4.0080 0x41C4.0000 to 0x41C4.0080 0x41C4.0000 to 0x41C4.0080 Aliased FACTORY #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE 0x41C5.0000 to 0x41C5.0080 0x41C5.0000 to 0x41C5.0080 0x41C5.0000 to 0x41C5.0080 Subsystem 0x6000.0000 to 0x7FFF.FFFF 0x6000.0000 to 0x7FFF.FFFF 0x6000.0000 to 0x7FFF.FFFF System PPB 0xE000.0000 to 0xE00F.FFFF 0xE000.0000 to 0xE00F.FFFF 0xE000.0000 to 0xE00F.FFFF Memory Region Subregion MSPM0L1304 MSPM0L1305 MSPM0L1306 Memory Region Subregion MSPM0L1304 MSPM0L1305 MSPM0L1306 Memory RegionSubregionMSPM0L1304MSPM0L1305MSPM0L1306 Code (Flash) MAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 16KB - 8B0x0000.0000 to 0x0000.3FF8 32KB - 8B#GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC 0x0000.0000 to 0x0000.7FF8 64KB - 8B#GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC 0x0000.0000 to 0x0000.FFF8 Aliased MAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 0x0040.0000 to 0x0040.3FF8 0x0040.0000 to 0x0040.7FF8 0x0040.0000 to 0x0040.FFF8 SRAM (SRAM) SRAM 2KB0x2000.0000 to 0x2000.0800 4KB0x2000.0000 to 0x2000.1000 4KB0x2000.0000 to 0x2000.1000 Aliased SRAM#GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE 0x2000.0000 to 0x2000.0800 0x2000.0000 to 0x2000.1000 0x2000.0000 to 0x2000.1000 Peripheral Peripherals 0x4000.0000 to 0x40FF.FFFF 0x4000.0000 to 0x40FF.FFFF 0x4000.0000 to 0x40FF.FFFF MAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 0x0000.0000 to 0x0000.3FF8 0x0000.0000 to 0x0000.7FF8 0x0000.0000 to 0x0000.FFF8 Aliased MAIN#GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 0x0040.0000 to 0x0040.3FF8 0x0040.0000 to 0x0040.7FF8 0x0040.0000 to 0x0040.FFF8 NONMAIN 512 bytes0x41C0.0000 to 0x41C0.0200 512 bytes0x41C0.0000 to 0x41C0.0200 512 bytes0x41C0.0000 to 0x41C0.0200 Aliased NONMAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE 0x41C1.0000 to 0x41C1.0200 0x41C1.0000 to 0x41C1.0200 0x41C1.0000 to 0x41C1.0200 FACTORY 0x41C4.0000 to 0x41C4.0080 0x41C4.0000 to 0x41C4.0080 0x41C4.0000 to 0x41C4.0080 Aliased FACTORY #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE 0x41C5.0000 to 0x41C5.0080 0x41C5.0000 to 0x41C5.0080 0x41C5.0000 to 0x41C5.0080 Subsystem 0x6000.0000 to 0x7FFF.FFFF 0x6000.0000 to 0x7FFF.FFFF 0x6000.0000 to 0x7FFF.FFFF System PPB 0xE000.0000 to 0xE00F.FFFF 0xE000.0000 to 0xE00F.FFFF 0xE000.0000 to 0xE00F.FFFF Code (Flash) MAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 16KB - 8B0x0000.0000 to 0x0000.3FF8 32KB - 8B#GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC 0x0000.0000 to 0x0000.7FF8 64KB - 8B#GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC 0x0000.0000 to 0x0000.FFF8 Code (Flash)MAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 16KB - 8B0x0000.0000 to 0x0000.3FF816KB - 8B 32KB - 8B#GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC 0x0000.0000 to 0x0000.7FF832KB - 8B#GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC 64KB - 8B#GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC 0x0000.0000 to 0x0000.FFF864KB - 8B#GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-5E755BE1-BC44-4826-82B9-4E79567D0ACC Aliased MAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 0x0040.0000 to 0x0040.3FF8 0x0040.0000 to 0x0040.7FF8 0x0040.0000 to 0x0040.FFF8 Aliased MAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE#GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D0x0040.0000 to 0x0040.3FF80x0040.0000 to 0x0040.7FF80x0040.0000 to 0x0040.FFF8 SRAM (SRAM) SRAM 2KB0x2000.0000 to 0x2000.0800 4KB0x2000.0000 to 0x2000.1000 4KB0x2000.0000 to 0x2000.1000 SRAM (SRAM)SRAM 2KB0x2000.0000 to 0x2000.08002KB 4KB0x2000.0000 to 0x2000.10004KB 4KB0x2000.0000 to 0x2000.10004KB Aliased SRAM#GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE 0x2000.0000 to 0x2000.0800 0x2000.0000 to 0x2000.1000 0x2000.0000 to 0x2000.1000 Aliased SRAM#GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE0x2000.0000 to 0x2000.08000x2000.0000 to 0x2000.10000x2000.0000 to 0x2000.1000 Peripheral Peripherals 0x4000.0000 to 0x40FF.FFFF 0x4000.0000 to 0x40FF.FFFF 0x4000.0000 to 0x40FF.FFFF PeripheralPeripherals0x4000.0000 to 0x40FF.FFFF0x4000.0000 to 0x40FF.FFFF0x4000.0000 to 0x40FF.FFFF MAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 0x0000.0000 to 0x0000.3FF8 0x0000.0000 to 0x0000.7FF8 0x0000.0000 to 0x0000.FFF8 MAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D0x0000.0000 to 0x0000.3FF80x0000.0000 to 0x0000.7FF80x0000.0000 to 0x0000.FFF8 Aliased MAIN#GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D 0x0040.0000 to 0x0040.3FF8 0x0040.0000 to 0x0040.7FF8 0x0040.0000 to 0x0040.FFF8 Aliased MAIN#GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE #GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE#GUID-50AA9617-B037-497F-B21E-3412F8A52045/GUID-64797140-BF45-4EBB-A2A6-AD1986DE378D0x0040.0000 to 0x0040.3FF80x0040.0000 to 0x0040.7FF80x0040.0000 to 0x0040.FFF8 NONMAIN 512 bytes0x41C0.0000 to 0x41C0.0200 512 bytes0x41C0.0000 to 0x41C0.0200 512 bytes0x41C0.0000 to 0x41C0.0200 NONMAIN 512 bytes0x41C0.0000 to 0x41C0.0200512 bytes 512 bytes0x41C0.0000 to 0x41C0.0200512 bytes 512 bytes0x41C0.0000 to 0x41C0.0200512 bytes Aliased NONMAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE 0x41C1.0000 to 0x41C1.0200 0x41C1.0000 to 0x41C1.0200 0x41C1.0000 to 0x41C1.0200 Aliased NONMAIN #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE0x41C1.0000 to 0x41C1.02000x41C1.0000 to 0x41C1.02000x41C1.0000 to 0x41C1.0200 FACTORY 0x41C4.0000 to 0x41C4.0080 0x41C4.0000 to 0x41C4.0080 0x41C4.0000 to 0x41C4.0080 FACTORY 0x41C4.0000 to 0x41C4.00800x41C4.0000 to 0x41C4.00800x41C4.0000 to 0x41C4.0080 Aliased FACTORY #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE 0x41C5.0000 to 0x41C5.0080 0x41C5.0000 to 0x41C5.0080 0x41C5.0000 to 0x41C5.0080 Aliased FACTORY #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE #GUID-50AA9617-B037-497F-B21E-3412F8A52045/WETTABLE_FLANK_NOTE0x41C5.0000 to 0x41C5.00800x41C5.0000 to 0x41C5.00800x41C5.0000 to 0x41C5.0080 Subsystem 0x6000.0000 to 0x7FFF.FFFF 0x6000.0000 to 0x7FFF.FFFF 0x6000.0000 to 0x7FFF.FFFF Subsystem0x6000.0000 to 0x7FFF.FFFF0x6000.0000 to 0x7FFF.FFFF0x6000.0000 to 0x7FFF.FFFF System PPB 0xE000.0000 to 0xE00F.FFFF 0xE000.0000 to 0xE00F.FFFF 0xE000.0000 to 0xE00F.FFFF System PPB0xE000.0000 to 0xE00F.FFFF0xE000.0000 to 0xE00F.FFFF0xE000.0000 to 0xE00F.FFFF First 32KB flash memory (address 0x0000.0000 to 0x0000.8000) has up to 100000 program and erase cycles. Aliased memory reads the same as the corresponding memory region. Aliased memory is included to keep the compatibility with devices that have ECC. CPU access to one of the last 8 bytes of a flash region will cause a hard fault. This occurs because the prefetch logic tries to read one flash word (64 bits) ahead, resulting in a read attempt to an invalid memory location. First 32KB flash memory (address 0x0000.0000 to 0x0000.8000) has up to 100000 program and erase cycles.Aliased memory reads the same as the corresponding memory region. Aliased memory is included to keep the compatibility with devices that have ECC. CPU access to one of the last 8 bytes of a flash region will cause a hard fault. This occurs because the prefetch logic tries to read one flash word (64 bits) ahead, resulting in a read attempt to an invalid memory location. Peripheral File Map #GUID-75EA9B50-3030-49EE-B191-0EF3DCD84C4A/TABLE_AXS_5GM_CRB lists the available peripherals and the register base address for each. Peripherals Summary Peripheral Name Base Address Size ADC0 0x40004000 0x2000 COMP0 0x40008000 0x2000 OPA0 0x40020000 0x2000 OPA1 0x40022000 0x2000 VREF 0x40030000 0x2000 WWDT0 0x40080000 0x2000 TIMG0 0x40084000 0x2000 TIMG1 0x40086000 0x2000 TIMG2 0x40088000 0x2000 TIMG4 0x4008C000 0x2000 GPIO0 0x400A0000 0x2000 SYSCTL 0x400AF000 0x3000 DEBUGSS 0x400C7000 0x2000 EVENT 0x400C9000 0x3000 NVMNW 0x400CD000 0x2000 I2C0 0x400F0000 0x2000 I2C1 0x400F2000 0x2000 UART1 0x40100000 0x2000 UART0 0x40108000 0x2000 MCPUSS 0x40400000 0x2000 WUC 0x40424000 0x1000 IOMUX 0x40428000 0x2000 DMA 0x4042A000 0x2000 CRC 0x40440000 0x2000 SPI0 0x40468000 0x2000 ADC0 (1) 0x4055A000 0x1000 (1) Aliased region of ADC0 memory-mapped registers. Peripheral File Map #GUID-75EA9B50-3030-49EE-B191-0EF3DCD84C4A/TABLE_AXS_5GM_CRB lists the available peripherals and the register base address for each. Peripherals Summary Peripheral Name Base Address Size ADC0 0x40004000 0x2000 COMP0 0x40008000 0x2000 OPA0 0x40020000 0x2000 OPA1 0x40022000 0x2000 VREF 0x40030000 0x2000 WWDT0 0x40080000 0x2000 TIMG0 0x40084000 0x2000 TIMG1 0x40086000 0x2000 TIMG2 0x40088000 0x2000 TIMG4 0x4008C000 0x2000 GPIO0 0x400A0000 0x2000 SYSCTL 0x400AF000 0x3000 DEBUGSS 0x400C7000 0x2000 EVENT 0x400C9000 0x3000 NVMNW 0x400CD000 0x2000 I2C0 0x400F0000 0x2000 I2C1 0x400F2000 0x2000 UART1 0x40100000 0x2000 UART0 0x40108000 0x2000 MCPUSS 0x40400000 0x2000 WUC 0x40424000 0x1000 IOMUX 0x40428000 0x2000 DMA 0x4042A000 0x2000 CRC 0x40440000 0x2000 SPI0 0x40468000 0x2000 ADC0 (1) 0x4055A000 0x1000 (1) Aliased region of ADC0 memory-mapped registers. #GUID-75EA9B50-3030-49EE-B191-0EF3DCD84C4A/TABLE_AXS_5GM_CRB lists the available peripherals and the register base address for each. #GUID-75EA9B50-3030-49EE-B191-0EF3DCD84C4A/TABLE_AXS_5GM_CRB lists the available peripherals and the register base address for each. #GUID-75EA9B50-3030-49EE-B191-0EF3DCD84C4A/TABLE_AXS_5GM_CRB Peripherals Summary Peripheral Name Base Address Size ADC0 0x40004000 0x2000 COMP0 0x40008000 0x2000 OPA0 0x40020000 0x2000 OPA1 0x40022000 0x2000 VREF 0x40030000 0x2000 WWDT0 0x40080000 0x2000 TIMG0 0x40084000 0x2000 TIMG1 0x40086000 0x2000 TIMG2 0x40088000 0x2000 TIMG4 0x4008C000 0x2000 GPIO0 0x400A0000 0x2000 SYSCTL 0x400AF000 0x3000 DEBUGSS 0x400C7000 0x2000 EVENT 0x400C9000 0x3000 NVMNW 0x400CD000 0x2000 I2C0 0x400F0000 0x2000 I2C1 0x400F2000 0x2000 UART1 0x40100000 0x2000 UART0 0x40108000 0x2000 MCPUSS 0x40400000 0x2000 WUC 0x40424000 0x1000 IOMUX 0x40428000 0x2000 DMA 0x4042A000 0x2000 CRC 0x40440000 0x2000 SPI0 0x40468000 0x2000 ADC0 (1) 0x4055A000 0x1000 Peripherals Summary Peripheral Name Base Address Size ADC0 0x40004000 0x2000 COMP0 0x40008000 0x2000 OPA0 0x40020000 0x2000 OPA1 0x40022000 0x2000 VREF 0x40030000 0x2000 WWDT0 0x40080000 0x2000 TIMG0 0x40084000 0x2000 TIMG1 0x40086000 0x2000 TIMG2 0x40088000 0x2000 TIMG4 0x4008C000 0x2000 GPIO0 0x400A0000 0x2000 SYSCTL 0x400AF000 0x3000 DEBUGSS 0x400C7000 0x2000 EVENT 0x400C9000 0x3000 NVMNW 0x400CD000 0x2000 I2C0 0x400F0000 0x2000 I2C1 0x400F2000 0x2000 UART1 0x40100000 0x2000 UART0 0x40108000 0x2000 MCPUSS 0x40400000 0x2000 WUC 0x40424000 0x1000 IOMUX 0x40428000 0x2000 DMA 0x4042A000 0x2000 CRC 0x40440000 0x2000 SPI0 0x40468000 0x2000 ADC0 (1) 0x4055A000 0x1000 Peripheral Name Base Address Size Peripheral Name Base Address Size Peripheral NameBase AddressSize ADC0 0x40004000 0x2000 COMP0 0x40008000 0x2000 OPA0 0x40020000 0x2000 OPA1 0x40022000 0x2000 VREF 0x40030000 0x2000 WWDT0 0x40080000 0x2000 TIMG0 0x40084000 0x2000 TIMG1 0x40086000 0x2000 TIMG2 0x40088000 0x2000 TIMG4 0x4008C000 0x2000 GPIO0 0x400A0000 0x2000 SYSCTL 0x400AF000 0x3000 DEBUGSS 0x400C7000 0x2000 EVENT 0x400C9000 0x3000 NVMNW 0x400CD000 0x2000 I2C0 0x400F0000 0x2000 I2C1 0x400F2000 0x2000 UART1 0x40100000 0x2000 UART0 0x40108000 0x2000 MCPUSS 0x40400000 0x2000 WUC 0x40424000 0x1000 IOMUX 0x40428000 0x2000 DMA 0x4042A000 0x2000 CRC 0x40440000 0x2000 SPI0 0x40468000 0x2000 ADC0 (1) 0x4055A000 0x1000 ADC0 0x40004000 0x2000 ADC00x400040000x2000 COMP0 0x40008000 0x2000 COMP00x400080000x2000 OPA0 0x40020000 0x2000 OPA00x400200000x2000 OPA1 0x40022000 0x2000 OPA10x400220000x2000 VREF 0x40030000 0x2000 VREF0x400300000x2000 WWDT0 0x40080000 0x2000 WWDT00x400800000x2000 TIMG0 0x40084000 0x2000 TIMG00x400840000x2000 TIMG1 0x40086000 0x2000 TIMG10x400860000x2000 TIMG2 0x40088000 0x2000 TIMG20x400880000x2000 TIMG4 0x4008C000 0x2000 TIMG40x4008C0000x2000 GPIO0 0x400A0000 0x2000 GPIO00x400A00000x2000 SYSCTL 0x400AF000 0x3000 SYSCTL0x400AF0000x3000 DEBUGSS 0x400C7000 0x2000 DEBUGSS0x400C70000x2000 EVENT 0x400C9000 0x3000 EVENT0x400C90000x3000 NVMNW 0x400CD000 0x2000 NVMNW0x400CD0000x2000 I2C0 0x400F0000 0x2000 I2C00x400F00000x2000 I2C1 0x400F2000 0x2000 I2C10x400F20000x2000 UART1 0x40100000 0x2000 UART10x401000000x2000 UART0 0x40108000 0x2000 UART00x401080000x2000 MCPUSS 0x40400000 0x2000 MCPUSS0x404000000x2000 WUC 0x40424000 0x1000 WUC0x404240000x1000 IOMUX 0x40428000 0x2000 IOMUX0x404280000x2000 DMA 0x4042A000 0x2000 DMA0x4042A0000x2000 CRC 0x40440000 0x2000 CRC0x404400000x2000 SPI0 0x40468000 0x2000 SPI00x404680000x2000 ADC0 (1) 0x4055A000 0x1000 ADC0 (1) (1)0x4055A0000x1000 (1) Aliased region of ADC0 memory-mapped registers. (1) Aliased region of ADC0 memory-mapped registers.(1) Peripheral Interrupt Vector #GUID-E85B0824-C3C2-42E1-ABB9-E274B22E95FC/TABLE_AXS_5GM_CRB shows the IRQ number and the interrupt group number for each peripherals in this device. Interrupt Vector Number Peripheral Name NVIC IRQ Group IIDX WWDT0 0 0 DEBUGSS 0 2 NVMNW 0 3 EVENT SUB PORT0 0 4 EVENT SUB PORT1 0 5 SYSCTL 0 6 GPIO0 1 0 COMP0 1 2 TIMG1 2 – ADC 4 – SPI0 9 – UART1 13 – UART0 15 – TIMG0 16 – TIMG2 18 – TIMG4 20 – I2C0 24 – I2C1 25 – DMA 31 – Peripheral Interrupt Vector #GUID-E85B0824-C3C2-42E1-ABB9-E274B22E95FC/TABLE_AXS_5GM_CRB shows the IRQ number and the interrupt group number for each peripherals in this device. Interrupt Vector Number Peripheral Name NVIC IRQ Group IIDX WWDT0 0 0 DEBUGSS 0 2 NVMNW 0 3 EVENT SUB PORT0 0 4 EVENT SUB PORT1 0 5 SYSCTL 0 6 GPIO0 1 0 COMP0 1 2 TIMG1 2 – ADC 4 – SPI0 9 – UART1 13 – UART0 15 – TIMG0 16 – TIMG2 18 – TIMG4 20 – I2C0 24 – I2C1 25 – DMA 31 – #GUID-E85B0824-C3C2-42E1-ABB9-E274B22E95FC/TABLE_AXS_5GM_CRB shows the IRQ number and the interrupt group number for each peripherals in this device. #GUID-E85B0824-C3C2-42E1-ABB9-E274B22E95FC/TABLE_AXS_5GM_CRB shows the IRQ number and the interrupt group number for each peripherals in this device.#GUID-E85B0824-C3C2-42E1-ABB9-E274B22E95FC/TABLE_AXS_5GM_CRB Interrupt Vector Number Peripheral Name NVIC IRQ Group IIDX WWDT0 0 0 DEBUGSS 0 2 NVMNW 0 3 EVENT SUB PORT0 0 4 EVENT SUB PORT1 0 5 SYSCTL 0 6 GPIO0 1 0 COMP0 1 2 TIMG1 2 – ADC 4 – SPI0 9 – UART1 13 – UART0 15 – TIMG0 16 – TIMG2 18 – TIMG4 20 – I2C0 24 – I2C1 25 – DMA 31 – Interrupt Vector Number Peripheral Name NVIC IRQ Group IIDX WWDT0 0 0 DEBUGSS 0 2 NVMNW 0 3 EVENT SUB PORT0 0 4 EVENT SUB PORT1 0 5 SYSCTL 0 6 GPIO0 1 0 COMP0 1 2 TIMG1 2 – ADC 4 – SPI0 9 – UART1 13 – UART0 15 – TIMG0 16 – TIMG2 18 – TIMG4 20 – I2C0 24 – I2C1 25 – DMA 31 – Peripheral Name NVIC IRQ Group IIDX Peripheral Name NVIC IRQ Group IIDX Peripheral NameNVIC IRQGroup IIDX WWDT0 0 0 DEBUGSS 0 2 NVMNW 0 3 EVENT SUB PORT0 0 4 EVENT SUB PORT1 0 5 SYSCTL 0 6 GPIO0 1 0 COMP0 1 2 TIMG1 2 – ADC 4 – SPI0 9 – UART1 13 – UART0 15 – TIMG0 16 – TIMG2 18 – TIMG4 20 – I2C0 24 – I2C1 25 – DMA 31 – WWDT0 0 0 WWDT0 00 DEBUGSS 0 2 DEBUGSS02 NVMNW 0 3 NVMNW03 EVENT SUB PORT0 0 4 EVENT SUB PORT004 EVENT SUB PORT1 0 5 EVENT SUB PORT105 SYSCTL 0 6 SYSCTL06 GPIO0 1 0 GPIO010 COMP0 1 2 COMP012 TIMG1 2 – TIMG12– ADC 4 – ADC4– SPI0 9 – SPI09– UART1 13 – UART113– UART0 15 – UART015– TIMG0 16 – TIMG016– TIMG2 18 – TIMG218– TIMG4 20 – TIMG420– I2C0 24 – I2C024– I2C1 25 – I2C125– DMA 31 – DMA31– Flash Memory A single bank of nonvolatile flash memory is provided for storing executable program code and application data. Key features of the flash include: In-circuit program and erase operations supported across the entire recommended supply range Small 1KB sector sizes (minimum erase resolution of 1KB) Up to 100000 program and erase cycles on the lower 32KB of the flash memory, with up to 10000 program and erase cycles on the remaining flash memory (devices with 32KB or less support 100000 cycles on the entire flash memory) For a complete description of the flash memory, see the NVM chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . Flash Memory A single bank of nonvolatile flash memory is provided for storing executable program code and application data. Key features of the flash include: In-circuit program and erase operations supported across the entire recommended supply range Small 1KB sector sizes (minimum erase resolution of 1KB) Up to 100000 program and erase cycles on the lower 32KB of the flash memory, with up to 10000 program and erase cycles on the remaining flash memory (devices with 32KB or less support 100000 cycles on the entire flash memory) For a complete description of the flash memory, see the NVM chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . A single bank of nonvolatile flash memory is provided for storing executable program code and application data. Key features of the flash include: In-circuit program and erase operations supported across the entire recommended supply range Small 1KB sector sizes (minimum erase resolution of 1KB) Up to 100000 program and erase cycles on the lower 32KB of the flash memory, with up to 10000 program and erase cycles on the remaining flash memory (devices with 32KB or less support 100000 cycles on the entire flash memory) For a complete description of the flash memory, see the NVM chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . A single bank of nonvolatile flash memory is provided for storing executable program code and application data.Key features of the flash include: In-circuit program and erase operations supported across the entire recommended supply range Small 1KB sector sizes (minimum erase resolution of 1KB) Up to 100000 program and erase cycles on the lower 32KB of the flash memory, with up to 10000 program and erase cycles on the remaining flash memory (devices with 32KB or less support 100000 cycles on the entire flash memory) In-circuit program and erase operations supported across the entire recommended supply rangeSmall 1KB sector sizes (minimum erase resolution of 1KB)Up to 100000 program and erase cycles on the lower 32KB of the flash memory, with up to 10000 program and erase cycles on the remaining flash memory (devices with 32KB or less support 100000 cycles on the entire flash memory)For a complete description of the flash memory, see the NVM chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual SRAM MSPM0Lxx MCUs include a low-power high-performance SRAM memory with zero wait state access across the supported CPU frequency range of the device. SRAM memory can be used for storing volatile information such as the call stack, heap, global data, and code. The SRAM memory content is fully retained in run, sleep, stop, and standby operating modes and is lost in shutdown mode. A write protection mechanism is provided to allow the application to prevent unintended modifications to a portion of the SRAM memory. SRAM write protection is useful when placing executable code into SRAM to provide a level of protection against unintentional overwrites of code by either the CPU or DMA. Placing code in SRAM can improve performance of critical loops by enabling zero wait state operation and lower power consumption. SRAM MSPM0Lxx MCUs include a low-power high-performance SRAM memory with zero wait state access across the supported CPU frequency range of the device. SRAM memory can be used for storing volatile information such as the call stack, heap, global data, and code. The SRAM memory content is fully retained in run, sleep, stop, and standby operating modes and is lost in shutdown mode. A write protection mechanism is provided to allow the application to prevent unintended modifications to a portion of the SRAM memory. SRAM write protection is useful when placing executable code into SRAM to provide a level of protection against unintentional overwrites of code by either the CPU or DMA. Placing code in SRAM can improve performance of critical loops by enabling zero wait state operation and lower power consumption. MSPM0Lxx MCUs include a low-power high-performance SRAM memory with zero wait state access across the supported CPU frequency range of the device. SRAM memory can be used for storing volatile information such as the call stack, heap, global data, and code. The SRAM memory content is fully retained in run, sleep, stop, and standby operating modes and is lost in shutdown mode. A write protection mechanism is provided to allow the application to prevent unintended modifications to a portion of the SRAM memory. SRAM write protection is useful when placing executable code into SRAM to provide a level of protection against unintentional overwrites of code by either the CPU or DMA. Placing code in SRAM can improve performance of critical loops by enabling zero wait state operation and lower power consumption. MSPM0Lxx MCUs include a low-power high-performance SRAM memory with zero wait state access across the supported CPU frequency range of the device. SRAM memory can be used for storing volatile information such as the call stack, heap, global data, and code. The SRAM memory content is fully retained in run, sleep, stop, and standby operating modes and is lost in shutdown mode. A write protection mechanism is provided to allow the application to prevent unintended modifications to a portion of the SRAM memory. SRAM write protection is useful when placing executable code into SRAM to provide a level of protection against unintentional overwrites of code by either the CPU or DMA. Placing code in SRAM can improve performance of critical loops by enabling zero wait state operation and lower power consumption. GPIO The general purpose input/output (GPIO) peripheral lets the application write data out and read data in through the device pins. Through the use of the Port A GPIO peripheral, these devices support up to 28 GPIO pins. The key features of the GPIO module include: 0 wait state MMR access from CPU Set, clear, or toggle multiple bits without the need of a read-modify-write construct in software "FastWake" feature enables low-power wakeup from STOP and STANDBY modes for any GPIO port User controlled input filtering GPIO The general purpose input/output (GPIO) peripheral lets the application write data out and read data in through the device pins. Through the use of the Port A GPIO peripheral, these devices support up to 28 GPIO pins. The key features of the GPIO module include: 0 wait state MMR access from CPU Set, clear, or toggle multiple bits without the need of a read-modify-write construct in software "FastWake" feature enables low-power wakeup from STOP and STANDBY modes for any GPIO port User controlled input filtering The general purpose input/output (GPIO) peripheral lets the application write data out and read data in through the device pins. Through the use of the Port A GPIO peripheral, these devices support up to 28 GPIO pins. The key features of the GPIO module include: 0 wait state MMR access from CPU Set, clear, or toggle multiple bits without the need of a read-modify-write construct in software "FastWake" feature enables low-power wakeup from STOP and STANDBY modes for any GPIO port User controlled input filtering The general purpose input/output (GPIO) peripheral lets the application write data out and read data in through the device pins. Through the use of the Port A GPIO peripheral, these devices support up to 28 GPIO pins.The key features of the GPIO module include: 0 wait state MMR access from CPU Set, clear, or toggle multiple bits without the need of a read-modify-write construct in software "FastWake" feature enables low-power wakeup from STOP and STANDBY modes for any GPIO port User controlled input filtering 0 wait state MMR access from CPUSet, clear, or toggle multiple bits without the need of a read-modify-write construct in software"FastWake" feature enables low-power wakeup from STOP and STANDBY modes for any GPIO portUser controlled input filtering IOMUX The IOMUX peripheral enables IO pad configuration and controls digital data flow to and from the device pins. The key features of the IOMUX include: IO pad configuration registers allow for programmable drive strength, speed, pullup or pulldown, and more Digital pin muxing allows for multiple peripheral signals to be routed to the same IO pad Pin functions and capabilities are user-configured using the PINCM register For more details, see the IOMUX chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . IOMUX The IOMUX peripheral enables IO pad configuration and controls digital data flow to and from the device pins. The key features of the IOMUX include: IO pad configuration registers allow for programmable drive strength, speed, pullup or pulldown, and more Digital pin muxing allows for multiple peripheral signals to be routed to the same IO pad Pin functions and capabilities are user-configured using the PINCM register For more details, see the IOMUX chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The IOMUX peripheral enables IO pad configuration and controls digital data flow to and from the device pins. The key features of the IOMUX include: IO pad configuration registers allow for programmable drive strength, speed, pullup or pulldown, and more Digital pin muxing allows for multiple peripheral signals to be routed to the same IO pad Pin functions and capabilities are user-configured using the PINCM register For more details, see the IOMUX chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The IOMUX peripheral enables IO pad configuration and controls digital data flow to and from the device pins. The key features of the IOMUX include: IO pad configuration registers allow for programmable drive strength, speed, pullup or pulldown, and more Digital pin muxing allows for multiple peripheral signals to be routed to the same IO pad Pin functions and capabilities are user-configured using the PINCM register IO pad configuration registers allow for programmable drive strength, speed, pullup or pulldown, and more Digital pin muxing allows for multiple peripheral signals to be routed to the same IO pad Pin functions and capabilities are user-configured using the PINCM register IO pad configuration registers allow for programmable drive strength, speed, pullup or pulldown, and moreDigital pin muxing allows for multiple peripheral signals to be routed to the same IO padPin functions and capabilities are user-configured using the PINCM registerFor more details, see the IOMUX chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual ADC The 12-bit analog-to-digital converter (ADC) module in these devices support fast 12-bit conversions with single-ended inputs. ADC features include: 12-bit output resolution at up to 1.68 Msps with greater than 11-bit ENOB HW averaging enables 14-bit conversion resolution at 105ksps Up to 10 external input channels Internal channels for temperature sensing, supply monitoring, and analog signal chain (interconnection with OPA, GPAMP, and others) Software selectable reference: Configurable internal dedicated ADC reference voltage of 1.4 V and 2.5 V (VREF) MCU supply voltage (VDD) External reference supplied to the ADC through the VREF+ and VREF- pins Operates in RUN, SLEEP, and STOP modes and supports triggers from STANDBY mode ADC0 Channel Mapping CHANNEL[0:7] SIGNAL NAME CHANNEL[8:15] SIGNAL NAME #GUID-2F456BA4-610F-47CC-869A-A4BC7D8436F6/LI_LYD_D5B_ZPB #GUID-2F456BA4-610F-47CC-869A-A4BC7D8436F6/GUID-CE37C01A-86CC-4266-8B64-2AEFEFEC39DC 0 A0 8 A8 1 A1 9 A9 2 A2 10 – 3 A3 11 Temperature Sensor 4 A4 12 OPA0 output 5 A5 13 OPA1 output 6 A6 14 GPAMP output 7 A7 15 Supply/Battery Monitor Italicized signal names are internal to the SoC. These signals are used for internal peripheral interconnections. For more information about device analog connections see . For more details, see the ADC chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . ADC The 12-bit analog-to-digital converter (ADC) module in these devices support fast 12-bit conversions with single-ended inputs. ADC features include: 12-bit output resolution at up to 1.68 Msps with greater than 11-bit ENOB HW averaging enables 14-bit conversion resolution at 105ksps Up to 10 external input channels Internal channels for temperature sensing, supply monitoring, and analog signal chain (interconnection with OPA, GPAMP, and others) Software selectable reference: Configurable internal dedicated ADC reference voltage of 1.4 V and 2.5 V (VREF) MCU supply voltage (VDD) External reference supplied to the ADC through the VREF+ and VREF- pins Operates in RUN, SLEEP, and STOP modes and supports triggers from STANDBY mode ADC0 Channel Mapping CHANNEL[0:7] SIGNAL NAME CHANNEL[8:15] SIGNAL NAME #GUID-2F456BA4-610F-47CC-869A-A4BC7D8436F6/LI_LYD_D5B_ZPB #GUID-2F456BA4-610F-47CC-869A-A4BC7D8436F6/GUID-CE37C01A-86CC-4266-8B64-2AEFEFEC39DC 0 A0 8 A8 1 A1 9 A9 2 A2 10 – 3 A3 11 Temperature Sensor 4 A4 12 OPA0 output 5 A5 13 OPA1 output 6 A6 14 GPAMP output 7 A7 15 Supply/Battery Monitor Italicized signal names are internal to the SoC. These signals are used for internal peripheral interconnections. For more information about device analog connections see . For more details, see the ADC chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The 12-bit analog-to-digital converter (ADC) module in these devices support fast 12-bit conversions with single-ended inputs. ADC features include: 12-bit output resolution at up to 1.68 Msps with greater than 11-bit ENOB HW averaging enables 14-bit conversion resolution at 105ksps Up to 10 external input channels Internal channels for temperature sensing, supply monitoring, and analog signal chain (interconnection with OPA, GPAMP, and others) Software selectable reference: Configurable internal dedicated ADC reference voltage of 1.4 V and 2.5 V (VREF) MCU supply voltage (VDD) External reference supplied to the ADC through the VREF+ and VREF- pins Operates in RUN, SLEEP, and STOP modes and supports triggers from STANDBY mode ADC0 Channel Mapping CHANNEL[0:7] SIGNAL NAME CHANNEL[8:15] SIGNAL NAME #GUID-2F456BA4-610F-47CC-869A-A4BC7D8436F6/LI_LYD_D5B_ZPB #GUID-2F456BA4-610F-47CC-869A-A4BC7D8436F6/GUID-CE37C01A-86CC-4266-8B64-2AEFEFEC39DC 0 A0 8 A8 1 A1 9 A9 2 A2 10 – 3 A3 11 Temperature Sensor 4 A4 12 OPA0 output 5 A5 13 OPA1 output 6 A6 14 GPAMP output 7 A7 15 Supply/Battery Monitor Italicized signal names are internal to the SoC. These signals are used for internal peripheral interconnections. For more information about device analog connections see . For more details, see the ADC chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The 12-bit analog-to-digital converter (ADC) module in these devices support fast 12-bit conversions with single-ended inputs. ADC features include: 12-bit output resolution at up to 1.68 Msps with greater than 11-bit ENOB HW averaging enables 14-bit conversion resolution at 105ksps Up to 10 external input channels Internal channels for temperature sensing, supply monitoring, and analog signal chain (interconnection with OPA, GPAMP, and others) Software selectable reference: Configurable internal dedicated ADC reference voltage of 1.4 V and 2.5 V (VREF) MCU supply voltage (VDD) External reference supplied to the ADC through the VREF+ and VREF- pins Operates in RUN, SLEEP, and STOP modes and supports triggers from STANDBY mode 12-bit output resolution at up to 1.68 Msps with greater than 11-bit ENOBHW averaging enables 14-bit conversion resolution at 105kspsUp to 10 external input channelsInternal channels for temperature sensing, supply monitoring, and analog signal chain (interconnection with OPA, GPAMP, and others)Software selectable reference: Configurable internal dedicated ADC reference voltage of 1.4 V and 2.5 V (VREF) MCU supply voltage (VDD) External reference supplied to the ADC through the VREF+ and VREF- pins Configurable internal dedicated ADC reference voltage of 1.4 V and 2.5 V (VREF) MCU supply voltage (VDD) External reference supplied to the ADC through the VREF+ and VREF- pins Configurable internal dedicated ADC reference voltage of 1.4 V and 2.5 V (VREF)MCU supply voltage (VDD)External reference supplied to the ADC through the VREF+ and VREF- pinsOperates in RUN, SLEEP, and STOP modes and supports triggers from STANDBY mode ADC0 Channel Mapping CHANNEL[0:7] SIGNAL NAME CHANNEL[8:15] SIGNAL NAME #GUID-2F456BA4-610F-47CC-869A-A4BC7D8436F6/LI_LYD_D5B_ZPB #GUID-2F456BA4-610F-47CC-869A-A4BC7D8436F6/GUID-CE37C01A-86CC-4266-8B64-2AEFEFEC39DC 0 A0 8 A8 1 A1 9 A9 2 A2 10 – 3 A3 11 Temperature Sensor 4 A4 12 OPA0 output 5 A5 13 OPA1 output 6 A6 14 GPAMP output 7 A7 15 Supply/Battery Monitor ADC0 Channel Mapping CHANNEL[0:7] SIGNAL NAME CHANNEL[8:15] SIGNAL NAME #GUID-2F456BA4-610F-47CC-869A-A4BC7D8436F6/LI_LYD_D5B_ZPB #GUID-2F456BA4-610F-47CC-869A-A4BC7D8436F6/GUID-CE37C01A-86CC-4266-8B64-2AEFEFEC39DC 0 A0 8 A8 1 A1 9 A9 2 A2 10 – 3 A3 11 Temperature Sensor 4 A4 12 OPA0 output 5 A5 13 OPA1 output 6 A6 14 GPAMP output 7 A7 15 Supply/Battery Monitor CHANNEL[0:7] SIGNAL NAME CHANNEL[8:15] SIGNAL NAME #GUID-2F456BA4-610F-47CC-869A-A4BC7D8436F6/LI_LYD_D5B_ZPB #GUID-2F456BA4-610F-47CC-869A-A4BC7D8436F6/GUID-CE37C01A-86CC-4266-8B64-2AEFEFEC39DC CHANNEL[0:7] SIGNAL NAME CHANNEL[8:15] SIGNAL NAME #GUID-2F456BA4-610F-47CC-869A-A4BC7D8436F6/LI_LYD_D5B_ZPB #GUID-2F456BA4-610F-47CC-869A-A4BC7D8436F6/GUID-CE37C01A-86CC-4266-8B64-2AEFEFEC39DC CHANNEL[0:7]SIGNAL NAMECHANNEL[8:15]SIGNAL NAME #GUID-2F456BA4-610F-47CC-869A-A4BC7D8436F6/LI_LYD_D5B_ZPB #GUID-2F456BA4-610F-47CC-869A-A4BC7D8436F6/GUID-CE37C01A-86CC-4266-8B64-2AEFEFEC39DC #GUID-2F456BA4-610F-47CC-869A-A4BC7D8436F6/LI_LYD_D5B_ZPB#GUID-2F456BA4-610F-47CC-869A-A4BC7D8436F6/GUID-CE37C01A-86CC-4266-8B64-2AEFEFEC39DC 0 A0 8 A8 1 A1 9 A9 2 A2 10 – 3 A3 11 Temperature Sensor 4 A4 12 OPA0 output 5 A5 13 OPA1 output 6 A6 14 GPAMP output 7 A7 15 Supply/Battery Monitor 0 A0 8 A8 0A08A8 1 A1 9 A9 1A19A9 2 A2 10 – 2A210– 3 A3 11 Temperature Sensor 3A311 Temperature Sensor Temperature Sensor 4 A4 12 OPA0 output 4A412 OPA0 output OPA0 output 5 A5 13 OPA1 output 5A513 OPA1 output OPA1 output 6 A6 14 GPAMP output 6A614 GPAMP output GPAMP output 7 A7 15 Supply/Battery Monitor 7A715 Supply/Battery Monitor Supply/Battery Monitor Italicized signal names are internal to the SoC. These signals are used for internal peripheral interconnections. For more information about device analog connections see . Italicized signal names are internal to the SoC. These signals are used for internal peripheral interconnections.ItalicizedFor more information about device analog connections see .For more details, see the ADC chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual Temperature Sensor The temperature sensor provides a voltage output that changes linearly with device temperature. The temperature sensor output is internally connected to one of ADC input channels to enable a temperature-to-digital conversion. A unit-specific single-point calibration value for the temperature sensor is provided in the factory constants memory region. This calibration value represents the ADC conversion result (in ADC code format) corresponding to the temperature sensor being measured in 12-bit mode with VDD = 3.3V at the factory trim temperature (TSTRIM). The ADC and VREF configuration for the above measurement is as the following: RES=0 (12-bit mode), VRSEL=0h (VDD), ADC tSample=12.5µs. This calibration value can be used with the temperature sensor temperature coefficient (TSc) to estimate the device temperature. See the temperature sensor section of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual for guidance on estimating the device temperature with the factory trim value. Temperature Sensor The temperature sensor provides a voltage output that changes linearly with device temperature. The temperature sensor output is internally connected to one of ADC input channels to enable a temperature-to-digital conversion. A unit-specific single-point calibration value for the temperature sensor is provided in the factory constants memory region. This calibration value represents the ADC conversion result (in ADC code format) corresponding to the temperature sensor being measured in 12-bit mode with VDD = 3.3V at the factory trim temperature (TSTRIM). The ADC and VREF configuration for the above measurement is as the following: RES=0 (12-bit mode), VRSEL=0h (VDD), ADC tSample=12.5µs. This calibration value can be used with the temperature sensor temperature coefficient (TSc) to estimate the device temperature. See the temperature sensor section of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual for guidance on estimating the device temperature with the factory trim value. The temperature sensor provides a voltage output that changes linearly with device temperature. The temperature sensor output is internally connected to one of ADC input channels to enable a temperature-to-digital conversion. A unit-specific single-point calibration value for the temperature sensor is provided in the factory constants memory region. This calibration value represents the ADC conversion result (in ADC code format) corresponding to the temperature sensor being measured in 12-bit mode with VDD = 3.3V at the factory trim temperature (TSTRIM). The ADC and VREF configuration for the above measurement is as the following: RES=0 (12-bit mode), VRSEL=0h (VDD), ADC tSample=12.5µs. This calibration value can be used with the temperature sensor temperature coefficient (TSc) to estimate the device temperature. See the temperature sensor section of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual for guidance on estimating the device temperature with the factory trim value. The temperature sensor provides a voltage output that changes linearly with device temperature. The temperature sensor output is internally connected to one of ADC input channels to enable a temperature-to-digital conversion.A unit-specific single-point calibration value for the temperature sensor is provided in the factory constants memory region. This calibration value represents the ADC conversion result (in ADC code format) corresponding to the temperature sensor being measured in 12-bit mode with VDD = 3.3V at the factory trim temperature (TSTRIM). The ADC and VREF configuration for the above measurement is as the following: RES=0 (12-bit mode), VRSEL=0h (VDD), ADC tSample=12.5µs. This calibration value can be used with the temperature sensor temperature coefficient (TSc) to estimate the device temperature. See the temperature sensor section of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual for guidance on estimating the device temperature with the factory trim value.TRIMSamplec MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual VREF The voltage reference module (VREF) in these devices contains a configurable voltage reference buffer dedicated for the on-board ADC. The devices also support connection of an external reference for applications in which higher accuracy is required. VREF features include: 1.4-V and 2.5-V user-selectable internal reference for ADC Internal reference supports ADC operation up to 200 ksps Support for bringing in an external reference for the ADC as well as for other analog peripherals on the VREF+ and VREF- device pins (24, 28, and 32-pin packages only) For more details, see the VREF chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . VREF The voltage reference module (VREF) in these devices contains a configurable voltage reference buffer dedicated for the on-board ADC. The devices also support connection of an external reference for applications in which higher accuracy is required. VREF features include: 1.4-V and 2.5-V user-selectable internal reference for ADC Internal reference supports ADC operation up to 200 ksps Support for bringing in an external reference for the ADC as well as for other analog peripherals on the VREF+ and VREF- device pins (24, 28, and 32-pin packages only) For more details, see the VREF chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The voltage reference module (VREF) in these devices contains a configurable voltage reference buffer dedicated for the on-board ADC. The devices also support connection of an external reference for applications in which higher accuracy is required. VREF features include: 1.4-V and 2.5-V user-selectable internal reference for ADC Internal reference supports ADC operation up to 200 ksps Support for bringing in an external reference for the ADC as well as for other analog peripherals on the VREF+ and VREF- device pins (24, 28, and 32-pin packages only) For more details, see the VREF chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The voltage reference module (VREF) in these devices contains a configurable voltage reference buffer dedicated for the on-board ADC. The devices also support connection of an external reference for applications in which higher accuracy is required.VREF features include: 1.4-V and 2.5-V user-selectable internal reference for ADC Internal reference supports ADC operation up to 200 ksps Support for bringing in an external reference for the ADC as well as for other analog peripherals on the VREF+ and VREF- device pins (24, 28, and 32-pin packages only) 1.4-V and 2.5-V user-selectable internal reference for ADCInternal reference supports ADC operation up to 200 kspsSupport for bringing in an external reference for the ADC as well as for other analog peripherals on the VREF+ and VREF- device pins (24, 28, and 32-pin packages only)For more details, see the VREF chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual COMP The comparator peripheral in the device compares the voltage levels on two inputs terminals and provides a digital output based on this comparison. The COMP supports the following key features: Programmable hysteresis Programmable reference voltage: Integrated 8-bit reference DAC, the output can also can connect to OPA input terminal internally as an output buffer. Configurable operation modes: High-speed mode (for the lowest propagation delay in timing-critical applications) Low-power mode (for monitoring slow-moving signals at the lowest power consumption) Programmable output glitch filter delay "Support output wake up device from all but the lowest low-power mode The IPSEL and IMSEL bits in comparator registers can be used to select the comparator channel inputs from device pins or from internal analog modules. COMP0 Input Channel Selection GUID-B2DFDAAE-EEC7-413E-B4AC-C1D0E3C5053E.html#unique_87_Connect_42_GUID-FA5669C8-C5A2-4D62-8FAF-5B607680FE12 IPSEL / IMSEL Bits Positive Terminal Input Negative Terminal Input 0x0 COMP0_IN0+ COMP0_IN0- 0x1 COMP0_IN1+ COMP0_IN1- 0x6 OPA1 output OPA0 output For more information about device analog connections, see . COMP0 Blanking Source Table CTL2.BLANKSRC Blanking Source Selected 0x0 Blanking source disabled 0x1 TIMG0.CC1 0x2 TIMG1.CC1 0x3 TIMG2.CC1 For more details, see the COMP chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . COMP The comparator peripheral in the device compares the voltage levels on two inputs terminals and provides a digital output based on this comparison. The COMP supports the following key features: Programmable hysteresis Programmable reference voltage: Integrated 8-bit reference DAC, the output can also can connect to OPA input terminal internally as an output buffer. Configurable operation modes: High-speed mode (for the lowest propagation delay in timing-critical applications) Low-power mode (for monitoring slow-moving signals at the lowest power consumption) Programmable output glitch filter delay "Support output wake up device from all but the lowest low-power mode The IPSEL and IMSEL bits in comparator registers can be used to select the comparator channel inputs from device pins or from internal analog modules. COMP0 Input Channel Selection GUID-B2DFDAAE-EEC7-413E-B4AC-C1D0E3C5053E.html#unique_87_Connect_42_GUID-FA5669C8-C5A2-4D62-8FAF-5B607680FE12 IPSEL / IMSEL Bits Positive Terminal Input Negative Terminal Input 0x0 COMP0_IN0+ COMP0_IN0- 0x1 COMP0_IN1+ COMP0_IN1- 0x6 OPA1 output OPA0 output For more information about device analog connections, see . COMP0 Blanking Source Table CTL2.BLANKSRC Blanking Source Selected 0x0 Blanking source disabled 0x1 TIMG0.CC1 0x2 TIMG1.CC1 0x3 TIMG2.CC1 For more details, see the COMP chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The comparator peripheral in the device compares the voltage levels on two inputs terminals and provides a digital output based on this comparison. The COMP supports the following key features: Programmable hysteresis Programmable reference voltage: Integrated 8-bit reference DAC, the output can also can connect to OPA input terminal internally as an output buffer. Configurable operation modes: High-speed mode (for the lowest propagation delay in timing-critical applications) Low-power mode (for monitoring slow-moving signals at the lowest power consumption) Programmable output glitch filter delay "Support output wake up device from all but the lowest low-power mode The IPSEL and IMSEL bits in comparator registers can be used to select the comparator channel inputs from device pins or from internal analog modules. COMP0 Input Channel Selection GUID-B2DFDAAE-EEC7-413E-B4AC-C1D0E3C5053E.html#unique_87_Connect_42_GUID-FA5669C8-C5A2-4D62-8FAF-5B607680FE12 IPSEL / IMSEL Bits Positive Terminal Input Negative Terminal Input 0x0 COMP0_IN0+ COMP0_IN0- 0x1 COMP0_IN1+ COMP0_IN1- 0x6 OPA1 output OPA0 output For more information about device analog connections, see . COMP0 Blanking Source Table CTL2.BLANKSRC Blanking Source Selected 0x0 Blanking source disabled 0x1 TIMG0.CC1 0x2 TIMG1.CC1 0x3 TIMG2.CC1 For more details, see the COMP chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The comparator peripheral in the device compares the voltage levels on two inputs terminals and provides a digital output based on this comparison. The COMP supports the following key features: Programmable hysteresis Programmable reference voltage: Integrated 8-bit reference DAC, the output can also can connect to OPA input terminal internally as an output buffer. Configurable operation modes: High-speed mode (for the lowest propagation delay in timing-critical applications) Low-power mode (for monitoring slow-moving signals at the lowest power consumption) Programmable output glitch filter delay "Support output wake up device from all but the lowest low-power mode The IPSEL and IMSEL bits in comparator registers can be used to select the comparator channel inputs from device pins or from internal analog modules. Programmable hysteresisProgrammable reference voltage: Integrated 8-bit reference DAC, the output can also can connect to OPA input terminal internally as an output buffer. Integrated 8-bit reference DAC, the output can also can connect to OPA input terminal internally as an output buffer. Integrated 8-bit reference DAC, the output can also can connect to OPA input terminal internally as an output buffer.Configurable operation modes: High-speed mode (for the lowest propagation delay in timing-critical applications) Low-power mode (for monitoring slow-moving signals at the lowest power consumption) High-speed mode (for the lowest propagation delay in timing-critical applications) Low-power mode (for monitoring slow-moving signals at the lowest power consumption) High-speed mode (for the lowest propagation delay in timing-critical applications)Low-power mode (for monitoring slow-moving signals at the lowest power consumption)Programmable output glitch filter delay"Support output wake up device from all but the lowest low-power modeThe IPSEL and IMSEL bits in comparator registers can be used to select the comparator channel inputs from device pins or from internal analog modules. COMP0 Input Channel Selection GUID-B2DFDAAE-EEC7-413E-B4AC-C1D0E3C5053E.html#unique_87_Connect_42_GUID-FA5669C8-C5A2-4D62-8FAF-5B607680FE12 IPSEL / IMSEL Bits Positive Terminal Input Negative Terminal Input 0x0 COMP0_IN0+ COMP0_IN0- 0x1 COMP0_IN1+ COMP0_IN1- 0x6 OPA1 output OPA0 output COMP0 Input Channel Selection GUID-B2DFDAAE-EEC7-413E-B4AC-C1D0E3C5053E.html#unique_87_Connect_42_GUID-FA5669C8-C5A2-4D62-8FAF-5B607680FE12 #GUID-B2DFDAAE-EEC7-413E-B4AC-C1D0E3C5053E/GUID-FA5669C8-C5A2-4D62-8FAF-5B607680FE12 #GUID-B2DFDAAE-EEC7-413E-B4AC-C1D0E3C5053E/GUID-FA5669C8-C5A2-4D62-8FAF-5B607680FE12 IPSEL / IMSEL Bits Positive Terminal Input Negative Terminal Input 0x0 COMP0_IN0+ COMP0_IN0- 0x1 COMP0_IN1+ COMP0_IN1- 0x6 OPA1 output OPA0 output IPSEL / IMSEL Bits Positive Terminal Input Negative Terminal Input IPSEL / IMSEL Bits Positive Terminal Input Negative Terminal Input IPSEL / IMSEL BitsPositive Terminal InputNegative Terminal Input 0x0 COMP0_IN0+ COMP0_IN0- 0x1 COMP0_IN1+ COMP0_IN1- 0x6 OPA1 output OPA0 output 0x0 COMP0_IN0+ COMP0_IN0- 0x0COMP0_IN0+COMP0_IN0- 0x1 COMP0_IN1+ COMP0_IN1- 0x1COMP0_IN1+COMP0_IN1- 0x6 OPA1 output OPA0 output 0x6OPA1 outputOPA0 output For more information about device analog connections, see . For more information about device analog connections, see . COMP0 Blanking Source Table CTL2.BLANKSRC Blanking Source Selected 0x0 Blanking source disabled 0x1 TIMG0.CC1 0x2 TIMG1.CC1 0x3 TIMG2.CC1 COMP0 Blanking Source Table CTL2.BLANKSRC Blanking Source Selected 0x0 Blanking source disabled 0x1 TIMG0.CC1 0x2 TIMG1.CC1 0x3 TIMG2.CC1 COMP0 Blanking Source Table CTL2.BLANKSRC Blanking Source Selected 0x0 Blanking source disabled 0x1 TIMG0.CC1 0x2 TIMG1.CC1 0x3 TIMG2.CC1 CTL2.BLANKSRC Blanking Source Selected CTL2.BLANKSRC Blanking Source Selected CTL2.BLANKSRCBlanking Source Selected 0x0 Blanking source disabled 0x1 TIMG0.CC1 0x2 TIMG1.CC1 0x3 TIMG2.CC1 0x0 Blanking source disabled 0x0Blanking source disabled 0x1 TIMG0.CC1 0x1TIMG0.CC1 0x2 TIMG1.CC1 0x2TIMG1.CC1 0x3 TIMG2.CC1 0x3TIMG2.CC1For more details, see the COMP chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual CRC The cyclical redundancy check (CRC) module provides a signature for an input data sequence. Key features of the CRC module include: Support for 16-bit CRC based on CRC16-CCITT Support for 32-bit CRC based on CRC32-ISO3309 Support for bit reversal For more details, see the CRC chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . CRC The cyclical redundancy check (CRC) module provides a signature for an input data sequence. Key features of the CRC module include: Support for 16-bit CRC based on CRC16-CCITT Support for 32-bit CRC based on CRC32-ISO3309 Support for bit reversal For more details, see the CRC chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The cyclical redundancy check (CRC) module provides a signature for an input data sequence. Key features of the CRC module include: Support for 16-bit CRC based on CRC16-CCITT Support for 32-bit CRC based on CRC32-ISO3309 Support for bit reversal For more details, see the CRC chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The cyclical redundancy check (CRC) module provides a signature for an input data sequence. Key features of the CRC module include: Support for 16-bit CRC based on CRC16-CCITT Support for 32-bit CRC based on CRC32-ISO3309 Support for bit reversal Support for 16-bit CRC based on CRC16-CCITTSupport for 32-bit CRC based on CRC32-ISO3309Support for bit reversalFor more details, see the CRC chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual GPAMP The general-purpose amplifier (GPAMP) peripheral is a chopper-stabilized general-purpose operational amplifier with rail-to-rail input and output. The GPAMP supports the following features: Software selectable chopper stabilization Rail-to-rail input and output Programmable internal unity gain feedback loop For more details, see the ADC chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . GPAMP The general-purpose amplifier (GPAMP) peripheral is a chopper-stabilized general-purpose operational amplifier with rail-to-rail input and output. The GPAMP supports the following features: Software selectable chopper stabilization Rail-to-rail input and output Programmable internal unity gain feedback loop For more details, see the ADC chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The general-purpose amplifier (GPAMP) peripheral is a chopper-stabilized general-purpose operational amplifier with rail-to-rail input and output. The GPAMP supports the following features: Software selectable chopper stabilization Rail-to-rail input and output Programmable internal unity gain feedback loop For more details, see the ADC chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The general-purpose amplifier (GPAMP) peripheral is a chopper-stabilized general-purpose operational amplifier with rail-to-rail input and output. The GPAMP supports the following features: Software selectable chopper stabilization Rail-to-rail input and output Programmable internal unity gain feedback loop Software selectable chopper stabilizationRail-to-rail input and outputProgrammable internal unity gain feedback loopFor more details, see the ADC chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual OPA The zero-drift op amps (OPAs) in these devices, OPA0 and OPA1, are chopper stabilized operational amplifiers with rail-to-rail input/output and a programmable gain stage feedback loop. The OPA peripherals support the following key features: Software-selectable zero-drift chopper stabilization for improved accuracy and drift performance Factory trimming to remove offset error Burnout current source (BCS) integrated to monitor sensor health Programmable gain amplifier (PGA) up to 32x The OPA features configurable input muxes P-MUX, N-MUX, and M-MUX to support various analog signal chain amplifier configurations that include general purpose, inverting, noninverting, unity gain, cascade, noninverting cascade, difference, and more. The following tables list the input channel mapping for each OPA. For more information about device analog connections, see For more details, see the OPA chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . OPA The zero-drift op amps (OPAs) in these devices, OPA0 and OPA1, are chopper stabilized operational amplifiers with rail-to-rail input/output and a programmable gain stage feedback loop. The OPA peripherals support the following key features: Software-selectable zero-drift chopper stabilization for improved accuracy and drift performance Factory trimming to remove offset error Burnout current source (BCS) integrated to monitor sensor health Programmable gain amplifier (PGA) up to 32x The OPA features configurable input muxes P-MUX, N-MUX, and M-MUX to support various analog signal chain amplifier configurations that include general purpose, inverting, noninverting, unity gain, cascade, noninverting cascade, difference, and more. The following tables list the input channel mapping for each OPA. For more information about device analog connections, see For more details, see the OPA chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The zero-drift op amps (OPAs) in these devices, OPA0 and OPA1, are chopper stabilized operational amplifiers with rail-to-rail input/output and a programmable gain stage feedback loop. The OPA peripherals support the following key features: Software-selectable zero-drift chopper stabilization for improved accuracy and drift performance Factory trimming to remove offset error Burnout current source (BCS) integrated to monitor sensor health Programmable gain amplifier (PGA) up to 32x The OPA features configurable input muxes P-MUX, N-MUX, and M-MUX to support various analog signal chain amplifier configurations that include general purpose, inverting, noninverting, unity gain, cascade, noninverting cascade, difference, and more. The following tables list the input channel mapping for each OPA. For more information about device analog connections, see For more details, see the OPA chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The zero-drift op amps (OPAs) in these devices, OPA0 and OPA1, are chopper stabilized operational amplifiers with rail-to-rail input/output and a programmable gain stage feedback loop.The OPA peripherals support the following key features: Software-selectable zero-drift chopper stabilization for improved accuracy and drift performance Factory trimming to remove offset error Burnout current source (BCS) integrated to monitor sensor health Programmable gain amplifier (PGA) up to 32x Software-selectable zero-drift chopper stabilization for improved accuracy and drift performanceFactory trimming to remove offset errorBurnout current source (BCS) integrated to monitor sensor healthProgrammable gain amplifier (PGA) up to 32xThe OPA features configurable input muxes P-MUX, N-MUX, and M-MUX to support various analog signal chain amplifier configurations that include general purpose, inverting, noninverting, unity gain, cascade, noninverting cascade, difference, and more. The following tables list the input channel mapping for each OPA. For more information about device analog connections, see For more details, see the OPA chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual I2C The inter-integrated circuit interface (I2C) peripherals in these devices provide bidirectional data transfer with other I2C devices on the bus and support the following key features: 7-bit and 10-bit addressing mode with multiple 7-bit target addresses Multiple-controller transmitter or receiver mode Target receiver or transmitter mode with configurable clock stretching Support Standard-mode (Sm), with a bit rate up to 100 kbit/s Support Fast-mode (Fm), with a bit rate up to 400 kbit/s Support Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s Supported on open drain IOs only (ODIO) Separated transmit and receive FIFOs support DMA data transfer Support SMBus 3.0 with PEC, ARP, timeout detection and host support Wakeup from low power mode on address match Support analog and digital glitch filter for input signal glitch suppression 8-entry transmit and receive FIFOs For more details, see the I2C chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . I2C The inter-integrated circuit interface (I2C) peripherals in these devices provide bidirectional data transfer with other I2C devices on the bus and support the following key features: 7-bit and 10-bit addressing mode with multiple 7-bit target addresses Multiple-controller transmitter or receiver mode Target receiver or transmitter mode with configurable clock stretching Support Standard-mode (Sm), with a bit rate up to 100 kbit/s Support Fast-mode (Fm), with a bit rate up to 400 kbit/s Support Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s Supported on open drain IOs only (ODIO) Separated transmit and receive FIFOs support DMA data transfer Support SMBus 3.0 with PEC, ARP, timeout detection and host support Wakeup from low power mode on address match Support analog and digital glitch filter for input signal glitch suppression 8-entry transmit and receive FIFOs For more details, see the I2C chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The inter-integrated circuit interface (I2C) peripherals in these devices provide bidirectional data transfer with other I2C devices on the bus and support the following key features: 7-bit and 10-bit addressing mode with multiple 7-bit target addresses Multiple-controller transmitter or receiver mode Target receiver or transmitter mode with configurable clock stretching Support Standard-mode (Sm), with a bit rate up to 100 kbit/s Support Fast-mode (Fm), with a bit rate up to 400 kbit/s Support Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s Supported on open drain IOs only (ODIO) Separated transmit and receive FIFOs support DMA data transfer Support SMBus 3.0 with PEC, ARP, timeout detection and host support Wakeup from low power mode on address match Support analog and digital glitch filter for input signal glitch suppression 8-entry transmit and receive FIFOs For more details, see the I2C chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The inter-integrated circuit interface (I2C) peripherals in these devices provide bidirectional data transfer with other I2C devices on the bus and support the following key features:2 7-bit and 10-bit addressing mode with multiple 7-bit target addresses Multiple-controller transmitter or receiver mode Target receiver or transmitter mode with configurable clock stretching Support Standard-mode (Sm), with a bit rate up to 100 kbit/s Support Fast-mode (Fm), with a bit rate up to 400 kbit/s Support Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s Supported on open drain IOs only (ODIO) Separated transmit and receive FIFOs support DMA data transfer Support SMBus 3.0 with PEC, ARP, timeout detection and host support Wakeup from low power mode on address match Support analog and digital glitch filter for input signal glitch suppression 8-entry transmit and receive FIFOs 7-bit and 10-bit addressing mode with multiple 7-bit target addressesMultiple-controller transmitter or receiver modeTarget receiver or transmitter mode with configurable clock stretchingSupport Standard-mode (Sm), with a bit rate up to 100 kbit/sSupport Fast-mode (Fm), with a bit rate up to 400 kbit/sSupport Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s Supported on open drain IOs only (ODIO) Supported on open drain IOs only (ODIO) Supported on open drain IOs only (ODIO)Separated transmit and receive FIFOs support DMA data transferSupport SMBus 3.0 with PEC, ARP, timeout detection and host support Wakeup from low power mode on address matchSupport analog and digital glitch filter for input signal glitch suppression8-entry transmit and receive FIFOsFor more details, see the I2C chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual SPI The serial peripheral interface (SPI) peripherals in these devices support the following key features: Support ULPCLK/2 bit rate and up to 16Mbits/s in both controller and peripheral mode Configurable as a controller or a peripheral Configurable chip select for both controller and peripheral Programmable clock prescaler and bit rate Programmable data frame size from 4 bits to 16 bits (controller mode) and 7 bits to 16 bit (peripheral mode) Supports PACKEN feature that allows the packing of 2 16 bit FIFO entries into a 32-bit value to improve CPU performance Transmit and receive FIFOs (4 entries each with 16 bits per entry) supporting DMA data transfer Supports TI mode, Motorola mode and National Microwire format For more details, see the SPI chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . SPI The serial peripheral interface (SPI) peripherals in these devices support the following key features: Support ULPCLK/2 bit rate and up to 16Mbits/s in both controller and peripheral mode Configurable as a controller or a peripheral Configurable chip select for both controller and peripheral Programmable clock prescaler and bit rate Programmable data frame size from 4 bits to 16 bits (controller mode) and 7 bits to 16 bit (peripheral mode) Supports PACKEN feature that allows the packing of 2 16 bit FIFO entries into a 32-bit value to improve CPU performance Transmit and receive FIFOs (4 entries each with 16 bits per entry) supporting DMA data transfer Supports TI mode, Motorola mode and National Microwire format For more details, see the SPI chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The serial peripheral interface (SPI) peripherals in these devices support the following key features: Support ULPCLK/2 bit rate and up to 16Mbits/s in both controller and peripheral mode Configurable as a controller or a peripheral Configurable chip select for both controller and peripheral Programmable clock prescaler and bit rate Programmable data frame size from 4 bits to 16 bits (controller mode) and 7 bits to 16 bit (peripheral mode) Supports PACKEN feature that allows the packing of 2 16 bit FIFO entries into a 32-bit value to improve CPU performance Transmit and receive FIFOs (4 entries each with 16 bits per entry) supporting DMA data transfer Supports TI mode, Motorola mode and National Microwire format For more details, see the SPI chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The serial peripheral interface (SPI) peripherals in these devices support the following key features: Support ULPCLK/2 bit rate and up to 16Mbits/s in both controller and peripheral mode Configurable as a controller or a peripheral Configurable chip select for both controller and peripheral Programmable clock prescaler and bit rate Programmable data frame size from 4 bits to 16 bits (controller mode) and 7 bits to 16 bit (peripheral mode) Supports PACKEN feature that allows the packing of 2 16 bit FIFO entries into a 32-bit value to improve CPU performance Transmit and receive FIFOs (4 entries each with 16 bits per entry) supporting DMA data transfer Supports TI mode, Motorola mode and National Microwire format Support ULPCLK/2 bit rate and up to 16Mbits/s in both controller and peripheral mode Configurable as a controller or a peripheral Configurable chip select for both controller and peripheral Programmable clock prescaler and bit rate Programmable data frame size from 4 bits to 16 bits (controller mode) and 7 bits to 16 bit (peripheral mode) Supports PACKEN feature that allows the packing of 2 16 bit FIFO entries into a 32-bit value to improve CPU performance Transmit and receive FIFOs (4 entries each with 16 bits per entry) supporting DMA data transfer Supports TI mode, Motorola mode and National Microwire format Support ULPCLK/2 bit rate and up to 16Mbits/s in both controller and peripheral mode 16Configurable as a controller or a peripheralConfigurable chip select for both controller and peripheralProgrammable clock prescaler and bit rateProgrammable data frame size from 4 bits to 16 bits (controller mode) and 7 bits to 16 bit (peripheral mode)Supports PACKEN feature that allows the packing of 2 16 bit FIFO entries into a 32-bit value to improve CPU performanceTransmit and receive FIFOs (4 entries each with 16 bits per entry) supporting DMA data transferSupports TI mode, Motorola mode and National Microwire formatFor more details, see the SPI chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual UART The UART peripherals provide the following key features: Standard asynchronous communication bits for start, stop, and parity Fully programmable serial interface 5, 6, 7 or 8 data bits Even, odd, stick, or no-parity bit generation and detection 1 or 2 stop bit generation Line-break detection Glitch filter on the input signals Programmable baud rate generation with oversampling by 16, 8 or 3 Local Interconnect Network (LIN) mode support Separated transmit and receive FIFOs support DAM data transfer Support transmit and receive loopback mode operation See #GUID-EB789472-7BE7-4F51-B659-FEED65B095DE/TABLE_DZ1_1M5_1RB for detail information on supported protocols UART Features UART Features UART0 (Extend) UART1 (Main) Active in Stop and Standby Mode Yes Yes Separate transmit and receive FIFOs Yes Yes Support hardware flow control Yes Yes Support 9-bit configuration Yes Yes Support LIN mode Yes - Support DALI Yes - Support IrDA Yes - Support ISO7816 Smart Card Yes - Support Manchester coding Yes - FIFO Depth 4 entries 4 entries For more details, see the UART chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . UART The UART peripherals provide the following key features: Standard asynchronous communication bits for start, stop, and parity Fully programmable serial interface 5, 6, 7 or 8 data bits Even, odd, stick, or no-parity bit generation and detection 1 or 2 stop bit generation Line-break detection Glitch filter on the input signals Programmable baud rate generation with oversampling by 16, 8 or 3 Local Interconnect Network (LIN) mode support Separated transmit and receive FIFOs support DAM data transfer Support transmit and receive loopback mode operation See #GUID-EB789472-7BE7-4F51-B659-FEED65B095DE/TABLE_DZ1_1M5_1RB for detail information on supported protocols UART Features UART Features UART0 (Extend) UART1 (Main) Active in Stop and Standby Mode Yes Yes Separate transmit and receive FIFOs Yes Yes Support hardware flow control Yes Yes Support 9-bit configuration Yes Yes Support LIN mode Yes - Support DALI Yes - Support IrDA Yes - Support ISO7816 Smart Card Yes - Support Manchester coding Yes - FIFO Depth 4 entries 4 entries For more details, see the UART chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The UART peripherals provide the following key features: Standard asynchronous communication bits for start, stop, and parity Fully programmable serial interface 5, 6, 7 or 8 data bits Even, odd, stick, or no-parity bit generation and detection 1 or 2 stop bit generation Line-break detection Glitch filter on the input signals Programmable baud rate generation with oversampling by 16, 8 or 3 Local Interconnect Network (LIN) mode support Separated transmit and receive FIFOs support DAM data transfer Support transmit and receive loopback mode operation See #GUID-EB789472-7BE7-4F51-B659-FEED65B095DE/TABLE_DZ1_1M5_1RB for detail information on supported protocols UART Features UART Features UART0 (Extend) UART1 (Main) Active in Stop and Standby Mode Yes Yes Separate transmit and receive FIFOs Yes Yes Support hardware flow control Yes Yes Support 9-bit configuration Yes Yes Support LIN mode Yes - Support DALI Yes - Support IrDA Yes - Support ISO7816 Smart Card Yes - Support Manchester coding Yes - FIFO Depth 4 entries 4 entries For more details, see the UART chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The UART peripherals provide the following key features: Standard asynchronous communication bits for start, stop, and parity Fully programmable serial interface 5, 6, 7 or 8 data bits Even, odd, stick, or no-parity bit generation and detection 1 or 2 stop bit generation Line-break detection Glitch filter on the input signals Programmable baud rate generation with oversampling by 16, 8 or 3 Local Interconnect Network (LIN) mode support Separated transmit and receive FIFOs support DAM data transfer Support transmit and receive loopback mode operation See #GUID-EB789472-7BE7-4F51-B659-FEED65B095DE/TABLE_DZ1_1M5_1RB for detail information on supported protocols Standard asynchronous communication bits for start, stop, and parity Fully programmable serial interface 5, 6, 7 or 8 data bits Even, odd, stick, or no-parity bit generation and detection 1 or 2 stop bit generation Line-break detection Glitch filter on the input signals Programmable baud rate generation with oversampling by 16, 8 or 3 Local Interconnect Network (LIN) mode support Separated transmit and receive FIFOs support DAM data transfer Support transmit and receive loopback mode operation See #GUID-EB789472-7BE7-4F51-B659-FEED65B095DE/TABLE_DZ1_1M5_1RB for detail information on supported protocols Standard asynchronous communication bits for start, stop, and parityFully programmable serial interface 5, 6, 7 or 8 data bits Even, odd, stick, or no-parity bit generation and detection 1 or 2 stop bit generation Line-break detection Glitch filter on the input signals Programmable baud rate generation with oversampling by 16, 8 or 3 Local Interconnect Network (LIN) mode support 5, 6, 7 or 8 data bits Even, odd, stick, or no-parity bit generation and detection 1 or 2 stop bit generation Line-break detection Glitch filter on the input signals Programmable baud rate generation with oversampling by 16, 8 or 3 Local Interconnect Network (LIN) mode support 5, 6, 7 or 8 data bitsEven, odd, stick, or no-parity bit generation and detection1 or 2 stop bit generationLine-break detectionGlitch filter on the input signalsProgrammable baud rate generation with oversampling by 16, 8 or 3Local Interconnect Network (LIN) mode supportSeparated transmit and receive FIFOs support DAM data transferSupport transmit and receive loopback mode operationSee #GUID-EB789472-7BE7-4F51-B659-FEED65B095DE/TABLE_DZ1_1M5_1RB for detail information on supported protocols#GUID-EB789472-7BE7-4F51-B659-FEED65B095DE/TABLE_DZ1_1M5_1RB UART Features UART Features UART0 (Extend) UART1 (Main) Active in Stop and Standby Mode Yes Yes Separate transmit and receive FIFOs Yes Yes Support hardware flow control Yes Yes Support 9-bit configuration Yes Yes Support LIN mode Yes - Support DALI Yes - Support IrDA Yes - Support ISO7816 Smart Card Yes - Support Manchester coding Yes - FIFO Depth 4 entries 4 entries UART Features UART Features UART0 (Extend) UART1 (Main) Active in Stop and Standby Mode Yes Yes Separate transmit and receive FIFOs Yes Yes Support hardware flow control Yes Yes Support 9-bit configuration Yes Yes Support LIN mode Yes - Support DALI Yes - Support IrDA Yes - Support ISO7816 Smart Card Yes - Support Manchester coding Yes - FIFO Depth 4 entries 4 entries UART Features UART0 (Extend) UART1 (Main) UART Features UART0 (Extend) UART1 (Main) UART FeaturesUART0 (Extend)UART1 (Main) Active in Stop and Standby Mode Yes Yes Separate transmit and receive FIFOs Yes Yes Support hardware flow control Yes Yes Support 9-bit configuration Yes Yes Support LIN mode Yes - Support DALI Yes - Support IrDA Yes - Support ISO7816 Smart Card Yes - Support Manchester coding Yes - FIFO Depth 4 entries 4 entries Active in Stop and Standby Mode Yes Yes Active in Stop and Standby ModeYesYes Separate transmit and receive FIFOs Yes Yes Separate transmit and receive FIFOsYesYes Support hardware flow control Yes Yes Support hardware flow controlYesYes Support 9-bit configuration Yes Yes Support 9-bit configurationYesYes Support LIN mode Yes - Support LIN modeYes- Support DALI Yes - Support DALIYes- Support IrDA Yes - Support IrDAYes- Support ISO7816 Smart Card Yes - Support ISO7816 Smart CardYes- Support Manchester coding Yes - Support Manchester codingYes- FIFO Depth 4 entries 4 entries FIFO Depth4 entries4 entriesFor more details, see the UART chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual WWDT The windowed watchdog timer (WWDT) can be used to supervise the operation of the device, specifically code execution. The WWDT can be used to generate a reset or an interrupt if the application software does not successfully reset the watchdog within a specified window of time. Key features of the WWDT include: 25-bit counter Programmable clock divider Eight software selectable watchdog timer periods Eight software selectable window sizes Support for stopping the WWDT automatically when entering a sleep mode Interval timer mode for applications which do not require watchdog functionality For more details, see the WWDT chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . WWDT The windowed watchdog timer (WWDT) can be used to supervise the operation of the device, specifically code execution. The WWDT can be used to generate a reset or an interrupt if the application software does not successfully reset the watchdog within a specified window of time. Key features of the WWDT include: 25-bit counter Programmable clock divider Eight software selectable watchdog timer periods Eight software selectable window sizes Support for stopping the WWDT automatically when entering a sleep mode Interval timer mode for applications which do not require watchdog functionality For more details, see the WWDT chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The windowed watchdog timer (WWDT) can be used to supervise the operation of the device, specifically code execution. The WWDT can be used to generate a reset or an interrupt if the application software does not successfully reset the watchdog within a specified window of time. Key features of the WWDT include: 25-bit counter Programmable clock divider Eight software selectable watchdog timer periods Eight software selectable window sizes Support for stopping the WWDT automatically when entering a sleep mode Interval timer mode for applications which do not require watchdog functionality For more details, see the WWDT chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The windowed watchdog timer (WWDT) can be used to supervise the operation of the device, specifically code execution. The WWDT can be used to generate a reset or an interrupt if the application software does not successfully reset the watchdog within a specified window of time. Key features of the WWDT include: 25-bit counter Programmable clock divider Eight software selectable watchdog timer periods Eight software selectable window sizes Support for stopping the WWDT automatically when entering a sleep mode Interval timer mode for applications which do not require watchdog functionality 25-bit counterProgrammable clock dividerEight software selectable watchdog timer periodsEight software selectable window sizesSupport for stopping the WWDT automatically when entering a sleep modeInterval timer mode for applications which do not require watchdog functionalityFor more details, see the WWDT chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual Timers (TIMx) The timer peripherals in these devices support the following key features. For specific configuration, see #GUID-3E3CAD8F-A052-4B0B-AB71-00B63C0F6173/TABLE_ZXW_LBJ_34B. Specific features for the general-purpose timer (TIMGx) include: 16-bit timers with up, down or up-down counting modes, with repeat-reload mode Selectable and configurable clock source 8-bit programmable prescaler to divide the counter clock frequency Two independent channels for Output compare Input capture PWM output One-shot mode Support quadrature encoder interface (QEI) for positioning and movement sensing Support synchronization and cross trigger among different TIMx instances in the same power domain Support interrupt/DMA trigger generation and cross peripherals (such as ADC) trigger capability Cross-trigger event logic for Hall sensor inputs Different TIMG Configurations TIM Name Power Domain Resolution Prescaler Capture/ Compare Channels External PWM Channels Phase Load Shadow Load Shadow CC TIMG0 PD0 16-bit 8-bit 2 2 - - - TIMG1 PD0 16-bit 8-bit 2 2 - - - TIMG2 PD0 16-bit 8-bit 2 2 - - - TIMG4 PD0 16-bit 8-bit 2 2 - Yes Yes TIMG Cross Trigger Map TSEL.ETSEL Selection TIMG0 TIMG1 TIMG2 TIMG4 0 TIMG0.TRIG0 TIMG0.TRIG0 TIMG0.TRIG0 TIMG0.TRIG0 1 TIMG1.TRIG0 TIMG1.TRIG0 TIMG1.TRIG0 TIMG1.TRIG0 2 TIMG2.TRIG0 TIMG2.TRIG0 TIMG2.TRIG0 TIMG2.TRIG0 3 TIMG4.TRIG0 TIMG4.TRIG0 TIMG4.TRIG0 TIMG4.TRIG0 4 to 15 Reserved 16 Event Subscriber Port 0 (FSUB0) 17 Event Subscriber Port 1 (FSUB1) 18to 31 Reserved For more details, see the timer chapters of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . Timers (TIMx) The timer peripherals in these devices support the following key features. For specific configuration, see #GUID-3E3CAD8F-A052-4B0B-AB71-00B63C0F6173/TABLE_ZXW_LBJ_34B. Specific features for the general-purpose timer (TIMGx) include: 16-bit timers with up, down or up-down counting modes, with repeat-reload mode Selectable and configurable clock source 8-bit programmable prescaler to divide the counter clock frequency Two independent channels for Output compare Input capture PWM output One-shot mode Support quadrature encoder interface (QEI) for positioning and movement sensing Support synchronization and cross trigger among different TIMx instances in the same power domain Support interrupt/DMA trigger generation and cross peripherals (such as ADC) trigger capability Cross-trigger event logic for Hall sensor inputs Different TIMG Configurations TIM Name Power Domain Resolution Prescaler Capture/ Compare Channels External PWM Channels Phase Load Shadow Load Shadow CC TIMG0 PD0 16-bit 8-bit 2 2 - - - TIMG1 PD0 16-bit 8-bit 2 2 - - - TIMG2 PD0 16-bit 8-bit 2 2 - - - TIMG4 PD0 16-bit 8-bit 2 2 - Yes Yes TIMG Cross Trigger Map TSEL.ETSEL Selection TIMG0 TIMG1 TIMG2 TIMG4 0 TIMG0.TRIG0 TIMG0.TRIG0 TIMG0.TRIG0 TIMG0.TRIG0 1 TIMG1.TRIG0 TIMG1.TRIG0 TIMG1.TRIG0 TIMG1.TRIG0 2 TIMG2.TRIG0 TIMG2.TRIG0 TIMG2.TRIG0 TIMG2.TRIG0 3 TIMG4.TRIG0 TIMG4.TRIG0 TIMG4.TRIG0 TIMG4.TRIG0 4 to 15 Reserved 16 Event Subscriber Port 0 (FSUB0) 17 Event Subscriber Port 1 (FSUB1) 18to 31 Reserved For more details, see the timer chapters of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The timer peripherals in these devices support the following key features. For specific configuration, see #GUID-3E3CAD8F-A052-4B0B-AB71-00B63C0F6173/TABLE_ZXW_LBJ_34B. Specific features for the general-purpose timer (TIMGx) include: 16-bit timers with up, down or up-down counting modes, with repeat-reload mode Selectable and configurable clock source 8-bit programmable prescaler to divide the counter clock frequency Two independent channels for Output compare Input capture PWM output One-shot mode Support quadrature encoder interface (QEI) for positioning and movement sensing Support synchronization and cross trigger among different TIMx instances in the same power domain Support interrupt/DMA trigger generation and cross peripherals (such as ADC) trigger capability Cross-trigger event logic for Hall sensor inputs Different TIMG Configurations TIM Name Power Domain Resolution Prescaler Capture/ Compare Channels External PWM Channels Phase Load Shadow Load Shadow CC TIMG0 PD0 16-bit 8-bit 2 2 - - - TIMG1 PD0 16-bit 8-bit 2 2 - - - TIMG2 PD0 16-bit 8-bit 2 2 - - - TIMG4 PD0 16-bit 8-bit 2 2 - Yes Yes TIMG Cross Trigger Map TSEL.ETSEL Selection TIMG0 TIMG1 TIMG2 TIMG4 0 TIMG0.TRIG0 TIMG0.TRIG0 TIMG0.TRIG0 TIMG0.TRIG0 1 TIMG1.TRIG0 TIMG1.TRIG0 TIMG1.TRIG0 TIMG1.TRIG0 2 TIMG2.TRIG0 TIMG2.TRIG0 TIMG2.TRIG0 TIMG2.TRIG0 3 TIMG4.TRIG0 TIMG4.TRIG0 TIMG4.TRIG0 TIMG4.TRIG0 4 to 15 Reserved 16 Event Subscriber Port 0 (FSUB0) 17 Event Subscriber Port 1 (FSUB1) 18to 31 Reserved For more details, see the timer chapters of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The timer peripherals in these devices support the following key features. For specific configuration, see #GUID-3E3CAD8F-A052-4B0B-AB71-00B63C0F6173/TABLE_ZXW_LBJ_34B.#GUID-3E3CAD8F-A052-4B0B-AB71-00B63C0F6173/TABLE_ZXW_LBJ_34BSpecific features for the general-purpose timer (TIMGx) include:general-purpose timer (TIMGx) 16-bit timers with up, down or up-down counting modes, with repeat-reload mode Selectable and configurable clock source 8-bit programmable prescaler to divide the counter clock frequency Two independent channels for Output compare Input capture PWM output One-shot mode Support quadrature encoder interface (QEI) for positioning and movement sensing Support synchronization and cross trigger among different TIMx instances in the same power domain Support interrupt/DMA trigger generation and cross peripherals (such as ADC) trigger capability Cross-trigger event logic for Hall sensor inputs 16-bit timers with up, down or up-down counting modes, with repeat-reload modeSelectable and configurable clock source8-bit programmable prescaler to divide the counter clock frequencyTwo independent channels for Output compare Input capture PWM output One-shot mode Output compare Input capture PWM output One-shot mode Output compareInput capturePWM outputOne-shot modeSupport quadrature encoder interface (QEI) for positioning and movement sensingSupport synchronization and cross trigger among different TIMx instances in the same power domainSupport interrupt/DMA trigger generation and cross peripherals (such as ADC) trigger capabilityCross-trigger event logic for Hall sensor inputs Different TIMG Configurations TIM Name Power Domain Resolution Prescaler Capture/ Compare Channels External PWM Channels Phase Load Shadow Load Shadow CC TIMG0 PD0 16-bit 8-bit 2 2 - - - TIMG1 PD0 16-bit 8-bit 2 2 - - - TIMG2 PD0 16-bit 8-bit 2 2 - - - TIMG4 PD0 16-bit 8-bit 2 2 - Yes Yes Different TIMG Configurations TIM Name Power Domain Resolution Prescaler Capture/ Compare Channels External PWM Channels Phase Load Shadow Load Shadow CC TIMG0 PD0 16-bit 8-bit 2 2 - - - TIMG1 PD0 16-bit 8-bit 2 2 - - - TIMG2 PD0 16-bit 8-bit 2 2 - - - TIMG4 PD0 16-bit 8-bit 2 2 - Yes Yes TIM Name Power Domain Resolution Prescaler Capture/ Compare Channels External PWM Channels Phase Load Shadow Load Shadow CC TIM Name Power Domain Resolution Prescaler Capture/ Compare Channels External PWM Channels Phase Load Shadow Load Shadow CC TIM NamePower DomainResolutionPrescalerCapture/ Compare Channels External PWM Channels External PWM ChannelsPhase LoadShadow LoadShadow CC TIMG0 PD0 16-bit 8-bit 2 2 - - - TIMG1 PD0 16-bit 8-bit 2 2 - - - TIMG2 PD0 16-bit 8-bit 2 2 - - - TIMG4 PD0 16-bit 8-bit 2 2 - Yes Yes TIMG0 PD0 16-bit 8-bit 2 2 - - - TIMG0PD016-bit8-bit2 2 2--- TIMG1 PD0 16-bit 8-bit 2 2 - - - TIMG1PD016-bit8-bit2 2 2--- TIMG2 PD0 16-bit 8-bit 2 2 - - - TIMG2PD016-bit8-bit2 2 2--- TIMG4 PD0 16-bit 8-bit 2 2 - Yes Yes TIMG4PD016-bit8-bit2 2 2-YesYes TIMG Cross Trigger Map TSEL.ETSEL Selection TIMG0 TIMG1 TIMG2 TIMG4 0 TIMG0.TRIG0 TIMG0.TRIG0 TIMG0.TRIG0 TIMG0.TRIG0 1 TIMG1.TRIG0 TIMG1.TRIG0 TIMG1.TRIG0 TIMG1.TRIG0 2 TIMG2.TRIG0 TIMG2.TRIG0 TIMG2.TRIG0 TIMG2.TRIG0 3 TIMG4.TRIG0 TIMG4.TRIG0 TIMG4.TRIG0 TIMG4.TRIG0 4 to 15 Reserved 16 Event Subscriber Port 0 (FSUB0) 17 Event Subscriber Port 1 (FSUB1) 18to 31 Reserved TIMG Cross Trigger Map TSEL.ETSEL Selection TIMG0 TIMG1 TIMG2 TIMG4 0 TIMG0.TRIG0 TIMG0.TRIG0 TIMG0.TRIG0 TIMG0.TRIG0 1 TIMG1.TRIG0 TIMG1.TRIG0 TIMG1.TRIG0 TIMG1.TRIG0 2 TIMG2.TRIG0 TIMG2.TRIG0 TIMG2.TRIG0 TIMG2.TRIG0 3 TIMG4.TRIG0 TIMG4.TRIG0 TIMG4.TRIG0 TIMG4.TRIG0 4 to 15 Reserved 16 Event Subscriber Port 0 (FSUB0) 17 Event Subscriber Port 1 (FSUB1) 18to 31 Reserved TSEL.ETSEL Selection TIMG0 TIMG1 TIMG2 TIMG4 TSEL.ETSEL Selection TIMG0 TIMG1 TIMG2 TIMG4 TSEL.ETSEL SelectionTIMG0TIMG1TIMG2TIMG4 0 TIMG0.TRIG0 TIMG0.TRIG0 TIMG0.TRIG0 TIMG0.TRIG0 1 TIMG1.TRIG0 TIMG1.TRIG0 TIMG1.TRIG0 TIMG1.TRIG0 2 TIMG2.TRIG0 TIMG2.TRIG0 TIMG2.TRIG0 TIMG2.TRIG0 3 TIMG4.TRIG0 TIMG4.TRIG0 TIMG4.TRIG0 TIMG4.TRIG0 4 to 15 Reserved 16 Event Subscriber Port 0 (FSUB0) 17 Event Subscriber Port 1 (FSUB1) 18to 31 Reserved 0 TIMG0.TRIG0 TIMG0.TRIG0 TIMG0.TRIG0 TIMG0.TRIG0 0TIMG0.TRIG0TIMG0.TRIG0TIMG0.TRIG0TIMG0.TRIG0 1 TIMG1.TRIG0 TIMG1.TRIG0 TIMG1.TRIG0 TIMG1.TRIG0 1TIMG1.TRIG0TIMG1.TRIG0TIMG1.TRIG0TIMG1.TRIG0 2 TIMG2.TRIG0 TIMG2.TRIG0 TIMG2.TRIG0 TIMG2.TRIG0 2TIMG2.TRIG0TIMG2.TRIG0TIMG2.TRIG0TIMG2.TRIG0 3 TIMG4.TRIG0 TIMG4.TRIG0 TIMG4.TRIG0 TIMG4.TRIG0 3TIMG4.TRIG0TIMG4.TRIG0TIMG4.TRIG0TIMG4.TRIG0 4 to 15 Reserved 4 to 15Reserved 16 Event Subscriber Port 0 (FSUB0) 16Event Subscriber Port 0 (FSUB0) 17 Event Subscriber Port 1 (FSUB1) 17Event Subscriber Port 1 (FSUB1) 18to 31 Reserved 18to 31ReservedFor more details, see the timer chapters of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual Device Analog Connections shows the internal analog connection of the device. Analog Connections Device Analog Connections shows the internal analog connection of the device. Analog Connections shows the internal analog connection of the device. Analog Connections Analog Connections Analog Connections Input/Output Diagrams The IOMUX manages the selection of which peripheral function is to be used on a digital IO and provides the controls for the output driver, input path, and the wake-up logic for wakeup from SHUTDOWN mode. For more information, see the IOMUX section of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The mixed-signal IO pin slice diagram for a full featured IO pin is shown in . Not all pins have analog functions, wake-up logic, drive strength control, and pullup or pulldown resistors available. See the device-specific data sheet for detailed information on what features are supported for a specific pin. Superset Input/Output Diagram Input/Output Diagrams The IOMUX manages the selection of which peripheral function is to be used on a digital IO and provides the controls for the output driver, input path, and the wake-up logic for wakeup from SHUTDOWN mode. For more information, see the IOMUX section of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The mixed-signal IO pin slice diagram for a full featured IO pin is shown in . Not all pins have analog functions, wake-up logic, drive strength control, and pullup or pulldown resistors available. See the device-specific data sheet for detailed information on what features are supported for a specific pin. Superset Input/Output Diagram The IOMUX manages the selection of which peripheral function is to be used on a digital IO and provides the controls for the output driver, input path, and the wake-up logic for wakeup from SHUTDOWN mode. For more information, see the IOMUX section of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The mixed-signal IO pin slice diagram for a full featured IO pin is shown in . Not all pins have analog functions, wake-up logic, drive strength control, and pullup or pulldown resistors available. See the device-specific data sheet for detailed information on what features are supported for a specific pin. Superset Input/Output Diagram MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual MSPM0 L-Series 32-MHz Microcontrollers Technical Reference ManualThe mixed-signal IO pin slice diagram for a full featured IO pin is shown in . Not all pins have analog functions, wake-up logic, drive strength control, and pullup or pulldown resistors available. See the device-specific data sheet for detailed information on what features are supported for a specific pin. Superset Input/Output Diagram Superset Input/Output Diagram Serial Wire Debug Interface A serial wire debug (SWD) two-wire interface is provided via an Arm compatible serial wire debug port (SW-DP) to enable access to multiple debug functions within the device. For a complete description of the debug functionality offered on MSPM0 devices, see the debug chapter of the technical reference manual. Serial Wire Debug Pin Requirements and Functions DEVICE SIGNAL DIRECTION SWD FUNCTION SWCLK Input Serial wire clock from debug probe SWDIO Input/Output Bi-directional (shared) serial wire data Serial Wire Debug Interface A serial wire debug (SWD) two-wire interface is provided via an Arm compatible serial wire debug port (SW-DP) to enable access to multiple debug functions within the device. For a complete description of the debug functionality offered on MSPM0 devices, see the debug chapter of the technical reference manual. Serial Wire Debug Pin Requirements and Functions DEVICE SIGNAL DIRECTION SWD FUNCTION SWCLK Input Serial wire clock from debug probe SWDIO Input/Output Bi-directional (shared) serial wire data A serial wire debug (SWD) two-wire interface is provided via an Arm compatible serial wire debug port (SW-DP) to enable access to multiple debug functions within the device. For a complete description of the debug functionality offered on MSPM0 devices, see the debug chapter of the technical reference manual. Serial Wire Debug Pin Requirements and Functions DEVICE SIGNAL DIRECTION SWD FUNCTION SWCLK Input Serial wire clock from debug probe SWDIO Input/Output Bi-directional (shared) serial wire data A serial wire debug (SWD) two-wire interface is provided via an Arm compatible serial wire debug port (SW-DP) to enable access to multiple debug functions within the device. For a complete description of the debug functionality offered on MSPM0 devices, see the debug chapter of the technical reference manual. Serial Wire Debug Pin Requirements and Functions DEVICE SIGNAL DIRECTION SWD FUNCTION SWCLK Input Serial wire clock from debug probe SWDIO Input/Output Bi-directional (shared) serial wire data Serial Wire Debug Pin Requirements and Functions DEVICE SIGNAL DIRECTION SWD FUNCTION SWCLK Input Serial wire clock from debug probe SWDIO Input/Output Bi-directional (shared) serial wire data DEVICE SIGNAL DIRECTION SWD FUNCTION DEVICE SIGNAL DIRECTION SWD FUNCTION DEVICE SIGNALDIRECTIONSWD FUNCTION SWCLK Input Serial wire clock from debug probe SWDIO Input/Output Bi-directional (shared) serial wire data SWCLK Input Serial wire clock from debug probe SWCLKInputSerial wire clock from debug probe SWDIO Input/Output Bi-directional (shared) serial wire data SWDIOInput/OutputBi-directional (shared) serial wire data Bootstrap Loader (BSL) The bootstrap loader (BSL) enables configuration of the device as well as programming of the device memory through a UART or I2C serial interface. Access to the device memory and configuration through the BSL is protected by a 256-bit user-defined password, and it is possible to completely disable the BSL in the device configuration, if desired. The BSL is enabled by default from TI to support use of the BSL for production programming. A minimum of two pins are required to use the BSL: the BSLRX and BSLTX signals (for UART), or the BSLSCL and BSLSDA signals (for I2C). Additionally, one or two additional pins (BSL_invoke and NRST) may be used for controlled invocation of the bootloader by an external host. If enabled, the BSL may be invoked (started) in the following ways: The BSL is invoked during the boot process if the BSL_invoke pin state matches the defined BSL_invoke logic level. If the device fast boot mode is enabled, this invocation check is skipped. An external host can force the device into the BSL by asserting the invoke condition and applying a reset pulse to the NRST pin to trigger a BOOTRST, after which the device will verify the invoke condition during the reboot process and start the BSL if the invoke condition matches the expected logic level. The BSL is automatically invoked during the boot process if the reset vector and stack pointer are left unprogrammed. As a result, a blank device from TI will invoke the BSL during the boot process without any need to provide a hardware invoke condition on the BSL_invoke pin. This enables production programming using just the serial interface signals. The BSL may be invoked at runtime from application software by issuing a SYSRST with BSL entry command. BSL Pin Requirements and Functions DEVICE SIGNAL CONNECTION BSL FUNCTION BSLRX Required for UART UART receive signal (RXD), an input BSLTX Required for UART UART transmit signal (TXD) an output BSLSCL Required for I2C I2C BSL clock signal (SCL) BSLSDA Required for I2C I2C BSL data signal (SDA) BSL_invoke Optional Active-high digital input used to start the BSL during boot NRST Optional Active-low reset pin used to trigger a reset and subsequent check of the invoke signal (BSL_invoke) Bootstrap Loader (BSL) The bootstrap loader (BSL) enables configuration of the device as well as programming of the device memory through a UART or I2C serial interface. Access to the device memory and configuration through the BSL is protected by a 256-bit user-defined password, and it is possible to completely disable the BSL in the device configuration, if desired. The BSL is enabled by default from TI to support use of the BSL for production programming. A minimum of two pins are required to use the BSL: the BSLRX and BSLTX signals (for UART), or the BSLSCL and BSLSDA signals (for I2C). Additionally, one or two additional pins (BSL_invoke and NRST) may be used for controlled invocation of the bootloader by an external host. If enabled, the BSL may be invoked (started) in the following ways: The BSL is invoked during the boot process if the BSL_invoke pin state matches the defined BSL_invoke logic level. If the device fast boot mode is enabled, this invocation check is skipped. An external host can force the device into the BSL by asserting the invoke condition and applying a reset pulse to the NRST pin to trigger a BOOTRST, after which the device will verify the invoke condition during the reboot process and start the BSL if the invoke condition matches the expected logic level. The BSL is automatically invoked during the boot process if the reset vector and stack pointer are left unprogrammed. As a result, a blank device from TI will invoke the BSL during the boot process without any need to provide a hardware invoke condition on the BSL_invoke pin. This enables production programming using just the serial interface signals. The BSL may be invoked at runtime from application software by issuing a SYSRST with BSL entry command. BSL Pin Requirements and Functions DEVICE SIGNAL CONNECTION BSL FUNCTION BSLRX Required for UART UART receive signal (RXD), an input BSLTX Required for UART UART transmit signal (TXD) an output BSLSCL Required for I2C I2C BSL clock signal (SCL) BSLSDA Required for I2C I2C BSL data signal (SDA) BSL_invoke Optional Active-high digital input used to start the BSL during boot NRST Optional Active-low reset pin used to trigger a reset and subsequent check of the invoke signal (BSL_invoke) The bootstrap loader (BSL) enables configuration of the device as well as programming of the device memory through a UART or I2C serial interface. Access to the device memory and configuration through the BSL is protected by a 256-bit user-defined password, and it is possible to completely disable the BSL in the device configuration, if desired. The BSL is enabled by default from TI to support use of the BSL for production programming. A minimum of two pins are required to use the BSL: the BSLRX and BSLTX signals (for UART), or the BSLSCL and BSLSDA signals (for I2C). Additionally, one or two additional pins (BSL_invoke and NRST) may be used for controlled invocation of the bootloader by an external host. If enabled, the BSL may be invoked (started) in the following ways: The BSL is invoked during the boot process if the BSL_invoke pin state matches the defined BSL_invoke logic level. If the device fast boot mode is enabled, this invocation check is skipped. An external host can force the device into the BSL by asserting the invoke condition and applying a reset pulse to the NRST pin to trigger a BOOTRST, after which the device will verify the invoke condition during the reboot process and start the BSL if the invoke condition matches the expected logic level. The BSL is automatically invoked during the boot process if the reset vector and stack pointer are left unprogrammed. As a result, a blank device from TI will invoke the BSL during the boot process without any need to provide a hardware invoke condition on the BSL_invoke pin. This enables production programming using just the serial interface signals. The BSL may be invoked at runtime from application software by issuing a SYSRST with BSL entry command. BSL Pin Requirements and Functions DEVICE SIGNAL CONNECTION BSL FUNCTION BSLRX Required for UART UART receive signal (RXD), an input BSLTX Required for UART UART transmit signal (TXD) an output BSLSCL Required for I2C I2C BSL clock signal (SCL) BSLSDA Required for I2C I2C BSL data signal (SDA) BSL_invoke Optional Active-high digital input used to start the BSL during boot NRST Optional Active-low reset pin used to trigger a reset and subsequent check of the invoke signal (BSL_invoke) The bootstrap loader (BSL) enables configuration of the device as well as programming of the device memory through a UART or I2C serial interface. Access to the device memory and configuration through the BSL is protected by a 256-bit user-defined password, and it is possible to completely disable the BSL in the device configuration, if desired. The BSL is enabled by default from TI to support use of the BSL for production programming.A minimum of two pins are required to use the BSL: the BSLRX and BSLTX signals (for UART), or the BSLSCL and BSLSDA signals (for I2C). Additionally, one or two additional pins (BSL_invoke and NRST) may be used for controlled invocation of the bootloader by an external host.2If enabled, the BSL may be invoked (started) in the following ways: The BSL is invoked during the boot process if the BSL_invoke pin state matches the defined BSL_invoke logic level. If the device fast boot mode is enabled, this invocation check is skipped. An external host can force the device into the BSL by asserting the invoke condition and applying a reset pulse to the NRST pin to trigger a BOOTRST, after which the device will verify the invoke condition during the reboot process and start the BSL if the invoke condition matches the expected logic level. The BSL is automatically invoked during the boot process if the reset vector and stack pointer are left unprogrammed. As a result, a blank device from TI will invoke the BSL during the boot process without any need to provide a hardware invoke condition on the BSL_invoke pin. This enables production programming using just the serial interface signals. The BSL may be invoked at runtime from application software by issuing a SYSRST with BSL entry command. The BSL is invoked during the boot process if the BSL_invoke pin state matches the defined BSL_invoke logic level. If the device fast boot mode is enabled, this invocation check is skipped. An external host can force the device into the BSL by asserting the invoke condition and applying a reset pulse to the NRST pin to trigger a BOOTRST, after which the device will verify the invoke condition during the reboot process and start the BSL if the invoke condition matches the expected logic level.The BSL is automatically invoked during the boot process if the reset vector and stack pointer are left unprogrammed. As a result, a blank device from TI will invoke the BSL during the boot process without any need to provide a hardware invoke condition on the BSL_invoke pin. This enables production programming using just the serial interface signals.The BSL may be invoked at runtime from application software by issuing a SYSRST with BSL entry command. BSL Pin Requirements and Functions DEVICE SIGNAL CONNECTION BSL FUNCTION BSLRX Required for UART UART receive signal (RXD), an input BSLTX Required for UART UART transmit signal (TXD) an output BSLSCL Required for I2C I2C BSL clock signal (SCL) BSLSDA Required for I2C I2C BSL data signal (SDA) BSL_invoke Optional Active-high digital input used to start the BSL during boot NRST Optional Active-low reset pin used to trigger a reset and subsequent check of the invoke signal (BSL_invoke) BSL Pin Requirements and Functions DEVICE SIGNAL CONNECTION BSL FUNCTION BSLRX Required for UART UART receive signal (RXD), an input BSLTX Required for UART UART transmit signal (TXD) an output BSLSCL Required for I2C I2C BSL clock signal (SCL) BSLSDA Required for I2C I2C BSL data signal (SDA) BSL_invoke Optional Active-high digital input used to start the BSL during boot NRST Optional Active-low reset pin used to trigger a reset and subsequent check of the invoke signal (BSL_invoke) DEVICE SIGNAL CONNECTION BSL FUNCTION DEVICE SIGNAL CONNECTION BSL FUNCTION DEVICE SIGNALCONNECTIONBSL FUNCTION BSLRX Required for UART UART receive signal (RXD), an input BSLTX Required for UART UART transmit signal (TXD) an output BSLSCL Required for I2C I2C BSL clock signal (SCL) BSLSDA Required for I2C I2C BSL data signal (SDA) BSL_invoke Optional Active-high digital input used to start the BSL during boot NRST Optional Active-low reset pin used to trigger a reset and subsequent check of the invoke signal (BSL_invoke) BSLRX Required for UART UART receive signal (RXD), an input BSLRXRequired for UARTUART receive signal (RXD), an input BSLTX Required for UART UART transmit signal (TXD) an output BSLTXRequired for UARTUART transmit signal (TXD) an output BSLSCL Required for I2C I2C BSL clock signal (SCL) BSLSCLRequired for I2CI2C BSL clock signal (SCL)2 BSLSDA Required for I2C I2C BSL data signal (SDA) BSLSDARequired for I2CI2C BSL data signal (SDA)2 BSL_invoke Optional Active-high digital input used to start the BSL during boot BSL_invokeOptionalActive-high digital input used to start the BSL during boot NRST Optional Active-low reset pin used to trigger a reset and subsequent check of the invoke signal (BSL_invoke) NRSTOptionalActive-low reset pin used to trigger a reset and subsequent check of the invoke signal (BSL_invoke) Device Factory Constants All devices include a memory-mapped FACTORY region which provides read-only data describing the capabilities of a device as well as any factory-provided trim information for use by application software. Refer to the Factory Constants chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . DEVICEID DEVICEID address is 0x41C4.0004, PARTNUM is bit 12 to 27, MANUFACTURER is bit 1 to 11. DEVICE DEVICEID.PARTNUM DEVICEID.MANUFACTURER MSPM0L1304 0xBB82 0x17 MSPM0L1305 0xBB82 0x17 MSPM0L1306 0xBB82 0x17 USERID USERID address is 0x41C4.0008, PART is bit 0 to 15, VARIANT is bit 16 to 23 DEVICE PART VARIANT DEVICE PART VARIANT M0L1306QRHBRQ1 0xDDD3 0xC2 M0L1305QRGERQ1 0x4845 0x74 M0L1306QDGS32RQ1 0xDDD3 0xC2 M0L1305QDGS20RQ1 0x4845 0xB7 M0L1306QDGS28RQ1 0xBB70 0xC2 M0L1305QDYYRQ1 0x4845 0xEC M0L1306QRGERQ1 0xDDD3 0xC2 M0L1304QRHBRQ1 0xAA4D 0xA9 M0L1306QDGS20RQ1 0xDDD3 0x59 M0L1304QDGS32RQ1 0xAA4D 0x91 M0L1306QDYYRQ1 0xBB70 0x9F M0L1304QDGS28RQ1 0xAA4D 0xB6 M0L1305QRHBRQ1 0x4845 0x78 M0L1304QRGERQ1 0xAA4D 0x91 M0L1305QDGS32RQ1 0x4845 0x74 M0L1304QDGS20RQ1 0xAA4D 0x91 M0L1305QDGS28RQ1 0x4845 0x74 M0L1304QDYYRQ1 0xAA4D 0xA0 Device Factory Constants All devices include a memory-mapped FACTORY region which provides read-only data describing the capabilities of a device as well as any factory-provided trim information for use by application software. Refer to the Factory Constants chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . DEVICEID DEVICEID address is 0x41C4.0004, PARTNUM is bit 12 to 27, MANUFACTURER is bit 1 to 11. DEVICE DEVICEID.PARTNUM DEVICEID.MANUFACTURER MSPM0L1304 0xBB82 0x17 MSPM0L1305 0xBB82 0x17 MSPM0L1306 0xBB82 0x17 USERID USERID address is 0x41C4.0008, PART is bit 0 to 15, VARIANT is bit 16 to 23 DEVICE PART VARIANT DEVICE PART VARIANT M0L1306QRHBRQ1 0xDDD3 0xC2 M0L1305QRGERQ1 0x4845 0x74 M0L1306QDGS32RQ1 0xDDD3 0xC2 M0L1305QDGS20RQ1 0x4845 0xB7 M0L1306QDGS28RQ1 0xBB70 0xC2 M0L1305QDYYRQ1 0x4845 0xEC M0L1306QRGERQ1 0xDDD3 0xC2 M0L1304QRHBRQ1 0xAA4D 0xA9 M0L1306QDGS20RQ1 0xDDD3 0x59 M0L1304QDGS32RQ1 0xAA4D 0x91 M0L1306QDYYRQ1 0xBB70 0x9F M0L1304QDGS28RQ1 0xAA4D 0xB6 M0L1305QRHBRQ1 0x4845 0x78 M0L1304QRGERQ1 0xAA4D 0x91 M0L1305QDGS32RQ1 0x4845 0x74 M0L1304QDGS20RQ1 0xAA4D 0x91 M0L1305QDGS28RQ1 0x4845 0x74 M0L1304QDYYRQ1 0xAA4D 0xA0 All devices include a memory-mapped FACTORY region which provides read-only data describing the capabilities of a device as well as any factory-provided trim information for use by application software. Refer to the Factory Constants chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . All devices include a memory-mapped FACTORY region which provides read-only data describing the capabilities of a device as well as any factory-provided trim information for use by application software. Refer to the Factory Constants chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual .Factory Constants MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual DEVICEID DEVICEID address is 0x41C4.0004, PARTNUM is bit 12 to 27, MANUFACTURER is bit 1 to 11. DEVICE DEVICEID.PARTNUM DEVICEID.MANUFACTURER MSPM0L1304 0xBB82 0x17 MSPM0L1305 0xBB82 0x17 MSPM0L1306 0xBB82 0x17 DEVICEID DEVICEID address is 0x41C4.0004, PARTNUM is bit 12 to 27, MANUFACTURER is bit 1 to 11. DEVICE DEVICEID.PARTNUM DEVICEID.MANUFACTURER MSPM0L1304 0xBB82 0x17 MSPM0L1305 0xBB82 0x17 MSPM0L1306 0xBB82 0x17 DEVICE DEVICEID.PARTNUM DEVICEID.MANUFACTURER DEVICE DEVICEID.PARTNUM DEVICEID.MANUFACTURER DEVICEDEVICEID.PARTNUMDEVICEID.MANUFACTURER MSPM0L1304 0xBB82 0x17 MSPM0L1305 0xBB82 0x17 MSPM0L1306 0xBB82 0x17 MSPM0L1304 0xBB82 0x17 MSPM0L13040xBB820x17 MSPM0L1305 0xBB82 0x17 MSPM0L13050xBB820x17 MSPM0L1306 0xBB82 0x17 MSPM0L13060xBB820x17 USERID USERID address is 0x41C4.0008, PART is bit 0 to 15, VARIANT is bit 16 to 23 DEVICE PART VARIANT DEVICE PART VARIANT M0L1306QRHBRQ1 0xDDD3 0xC2 M0L1305QRGERQ1 0x4845 0x74 M0L1306QDGS32RQ1 0xDDD3 0xC2 M0L1305QDGS20RQ1 0x4845 0xB7 M0L1306QDGS28RQ1 0xBB70 0xC2 M0L1305QDYYRQ1 0x4845 0xEC M0L1306QRGERQ1 0xDDD3 0xC2 M0L1304QRHBRQ1 0xAA4D 0xA9 M0L1306QDGS20RQ1 0xDDD3 0x59 M0L1304QDGS32RQ1 0xAA4D 0x91 M0L1306QDYYRQ1 0xBB70 0x9F M0L1304QDGS28RQ1 0xAA4D 0xB6 M0L1305QRHBRQ1 0x4845 0x78 M0L1304QRGERQ1 0xAA4D 0x91 M0L1305QDGS32RQ1 0x4845 0x74 M0L1304QDGS20RQ1 0xAA4D 0x91 M0L1305QDGS28RQ1 0x4845 0x74 M0L1304QDYYRQ1 0xAA4D 0xA0 USERIDUSERID address is 0x41C4.0008, PART is bit 0 to 15, VARIANT is bit 16 to 23 DEVICE PART VARIANT DEVICE PART VARIANT M0L1306QRHBRQ1 0xDDD3 0xC2 M0L1305QRGERQ1 0x4845 0x74 M0L1306QDGS32RQ1 0xDDD3 0xC2 M0L1305QDGS20RQ1 0x4845 0xB7 M0L1306QDGS28RQ1 0xBB70 0xC2 M0L1305QDYYRQ1 0x4845 0xEC M0L1306QRGERQ1 0xDDD3 0xC2 M0L1304QRHBRQ1 0xAA4D 0xA9 M0L1306QDGS20RQ1 0xDDD3 0x59 M0L1304QDGS32RQ1 0xAA4D 0x91 M0L1306QDYYRQ1 0xBB70 0x9F M0L1304QDGS28RQ1 0xAA4D 0xB6 M0L1305QRHBRQ1 0x4845 0x78 M0L1304QRGERQ1 0xAA4D 0x91 M0L1305QDGS32RQ1 0x4845 0x74 M0L1304QDGS20RQ1 0xAA4D 0x91 M0L1305QDGS28RQ1 0x4845 0x74 M0L1304QDYYRQ1 0xAA4D 0xA0 DEVICE PART VARIANT DEVICE PART VARIANT DEVICE PART VARIANT DEVICE PART VARIANT DEVICEPARTVARIANTDEVICEPARTVARIANT M0L1306QRHBRQ1 0xDDD3 0xC2 M0L1305QRGERQ1 0x4845 0x74 M0L1306QDGS32RQ1 0xDDD3 0xC2 M0L1305QDGS20RQ1 0x4845 0xB7 M0L1306QDGS28RQ1 0xBB70 0xC2 M0L1305QDYYRQ1 0x4845 0xEC M0L1306QRGERQ1 0xDDD3 0xC2 M0L1304QRHBRQ1 0xAA4D 0xA9 M0L1306QDGS20RQ1 0xDDD3 0x59 M0L1304QDGS32RQ1 0xAA4D 0x91 M0L1306QDYYRQ1 0xBB70 0x9F M0L1304QDGS28RQ1 0xAA4D 0xB6 M0L1305QRHBRQ1 0x4845 0x78 M0L1304QRGERQ1 0xAA4D 0x91 M0L1305QDGS32RQ1 0x4845 0x74 M0L1304QDGS20RQ1 0xAA4D 0x91 M0L1305QDGS28RQ1 0x4845 0x74 M0L1304QDYYRQ1 0xAA4D 0xA0 M0L1306QRHBRQ1 0xDDD3 0xC2 M0L1305QRGERQ1 0x4845 0x74 M0L1306QRHBRQ10xDDD30xC2M0L1305QRGERQ10x48450x74 M0L1306QDGS32RQ1 0xDDD3 0xC2 M0L1305QDGS20RQ1 0x4845 0xB7 M0L1306QDGS32RQ10xDDD30xC2M0L1305QDGS20RQ10x48450xB7 M0L1306QDGS28RQ1 0xBB70 0xC2 M0L1305QDYYRQ1 0x4845 0xEC M0L1306QDGS28RQ10xBB700xC2M0L1305QDYYRQ10x48450xEC M0L1306QRGERQ1 0xDDD3 0xC2 M0L1304QRHBRQ1 0xAA4D 0xA9 M0L1306QRGERQ10xDDD30xC2M0L1304QRHBRQ10xAA4D0xA9 M0L1306QDGS20RQ1 0xDDD3 0x59 M0L1304QDGS32RQ1 0xAA4D 0x91 M0L1306QDGS20RQ10xDDD30x59M0L1304QDGS32RQ10xAA4D0x91 M0L1306QDYYRQ1 0xBB70 0x9F M0L1304QDGS28RQ1 0xAA4D 0xB6 M0L1306QDYYRQ10xBB700x9FM0L1304QDGS28RQ10xAA4D0xB6 M0L1305QRHBRQ1 0x4845 0x78 M0L1304QRGERQ1 0xAA4D 0x91 M0L1305QRHBRQ10x48450x78M0L1304QRGERQ1 0xAA4D0x91 M0L1305QDGS32RQ1 0x4845 0x74 M0L1304QDGS20RQ1 0xAA4D 0x91 M0L1305QDGS32RQ10x48450x74M0L1304QDGS20RQ1 0xAA4D0x91 M0L1305QDGS28RQ1 0x4845 0x74 M0L1304QDYYRQ1 0xAA4D 0xA0 M0L1305QDGS28RQ10x48450x74M0L1304QDYYRQ10xAA4D0xA0 Identification Revision and Device Identification The hardware revision and device identification values are stored in the memory-mapped FACTORY region (see the Device Factory Constants section) which provides read-only data describing the capabilities of a device as well as any factory-provided trim information for use by application software. For more information, see the Factory Constants chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The device revision and identification information are also included as part of the top-side marking on the device package. The device-specific errata describes these markings (see ). Identification Revision and Device Identification The hardware revision and device identification values are stored in the memory-mapped FACTORY region (see the Device Factory Constants section) which provides read-only data describing the capabilities of a device as well as any factory-provided trim information for use by application software. For more information, see the Factory Constants chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The device revision and identification information are also included as part of the top-side marking on the device package. The device-specific errata describes these markings (see ). Revision and Device Identification The hardware revision and device identification values are stored in the memory-mapped FACTORY region (see the Device Factory Constants section) which provides read-only data describing the capabilities of a device as well as any factory-provided trim information for use by application software. For more information, see the Factory Constants chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . The device revision and identification information are also included as part of the top-side marking on the device package. The device-specific errata describes these markings (see ). Revision and Device Identification The hardware revision and device identification values are stored in the memory-mapped FACTORY region (see the Device Factory Constants section) which provides read-only data describing the capabilities of a device as well as any factory-provided trim information for use by application software. For more information, see the Factory Constants chapter of the MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual . Factory Constants MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual MSPM0 L-Series 32-MHz Microcontrollers Technical Reference ManualThe device revision and identification information are also included as part of the top-side marking on the device package. The device-specific errata describes these markings (see ). (see ) Applications, Implementation, and Layout Typical Application Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Schematic TI recommends connecting a combination of a 10-µF and a 0.1-µF low-ESR ceramic decoupling capacitor across the VDD and VSS pins, as well as placing these capacitors as close as possible to the supply pins that they decouple (within a few millimeters) to achieve a minimal loop area. The 10-µF bulk decoupling capacitor is a recommended value for most applications, but this capacitance may be adjusted if needed based upon the PCB design and application requirements. For example, larger bulk capacitors can be used, but this can affect the supply rail ramp-up time. The NRST reset pin must be pulled up to VDD (supply level) for the device to release from RESET state and start the boot process. TI recommends connecting an external 47-kΩ pullup resistor with a 10-nF pulldown capacitor for most applications, enabling the NRST pin to be controlled by another device or a debug probe. The SYSOSC frequency correction loop (FCL) circuit utilizes an external 100-kΩ with 0.1% tolerance resistor with a temperature coefficient (TCR) of 25ppm/C or better populated between the ROSC pin and VSS. This resistor establishes a reference current to stabilize the SYSOSC frequency through a correction loop. This resistor is required if the FCL feature is used for higher accuracy, and it is not required if the SYSOSC FCL is not enabled. When the FCL mode is not used, the PA2 pin may be used as a digital input/output pin. A 0.47-µF tank capacitor is required for the VCORE pin and must be placed close to the device with minimum distance to the device ground. Do not connect other circuits to the VCORE pin. For the 5-V-tolerant open drain (ODIO), a pullup resistor is required to output high for I2C and UART functions, as the open drain IO only implement a low-side NMOS driver and no high-side PMOS driver. The 5V-tolerant open drain IO are fail-safe and may have a voltage present even if VDD is not supplied. Basic Application Schematic Applications, Implementation, and Layout Typical Application Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Schematic TI recommends connecting a combination of a 10-µF and a 0.1-µF low-ESR ceramic decoupling capacitor across the VDD and VSS pins, as well as placing these capacitors as close as possible to the supply pins that they decouple (within a few millimeters) to achieve a minimal loop area. The 10-µF bulk decoupling capacitor is a recommended value for most applications, but this capacitance may be adjusted if needed based upon the PCB design and application requirements. For example, larger bulk capacitors can be used, but this can affect the supply rail ramp-up time. The NRST reset pin must be pulled up to VDD (supply level) for the device to release from RESET state and start the boot process. TI recommends connecting an external 47-kΩ pullup resistor with a 10-nF pulldown capacitor for most applications, enabling the NRST pin to be controlled by another device or a debug probe. The SYSOSC frequency correction loop (FCL) circuit utilizes an external 100-kΩ with 0.1% tolerance resistor with a temperature coefficient (TCR) of 25ppm/C or better populated between the ROSC pin and VSS. This resistor establishes a reference current to stabilize the SYSOSC frequency through a correction loop. This resistor is required if the FCL feature is used for higher accuracy, and it is not required if the SYSOSC FCL is not enabled. When the FCL mode is not used, the PA2 pin may be used as a digital input/output pin. A 0.47-µF tank capacitor is required for the VCORE pin and must be placed close to the device with minimum distance to the device ground. Do not connect other circuits to the VCORE pin. For the 5-V-tolerant open drain (ODIO), a pullup resistor is required to output high for I2C and UART functions, as the open drain IO only implement a low-side NMOS driver and no high-side PMOS driver. The 5V-tolerant open drain IO are fail-safe and may have a voltage present even if VDD is not supplied. Basic Application Schematic Typical Application Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. Schematic TI recommends connecting a combination of a 10-µF and a 0.1-µF low-ESR ceramic decoupling capacitor across the VDD and VSS pins, as well as placing these capacitors as close as possible to the supply pins that they decouple (within a few millimeters) to achieve a minimal loop area. The 10-µF bulk decoupling capacitor is a recommended value for most applications, but this capacitance may be adjusted if needed based upon the PCB design and application requirements. For example, larger bulk capacitors can be used, but this can affect the supply rail ramp-up time. The NRST reset pin must be pulled up to VDD (supply level) for the device to release from RESET state and start the boot process. TI recommends connecting an external 47-kΩ pullup resistor with a 10-nF pulldown capacitor for most applications, enabling the NRST pin to be controlled by another device or a debug probe. The SYSOSC frequency correction loop (FCL) circuit utilizes an external 100-kΩ with 0.1% tolerance resistor with a temperature coefficient (TCR) of 25ppm/C or better populated between the ROSC pin and VSS. This resistor establishes a reference current to stabilize the SYSOSC frequency through a correction loop. This resistor is required if the FCL feature is used for higher accuracy, and it is not required if the SYSOSC FCL is not enabled. When the FCL mode is not used, the PA2 pin may be used as a digital input/output pin. A 0.47-µF tank capacitor is required for the VCORE pin and must be placed close to the device with minimum distance to the device ground. Do not connect other circuits to the VCORE pin. For the 5-V-tolerant open drain (ODIO), a pullup resistor is required to output high for I2C and UART functions, as the open drain IO only implement a low-side NMOS driver and no high-side PMOS driver. The 5V-tolerant open drain IO are fail-safe and may have a voltage present even if VDD is not supplied. Basic Application Schematic Schematic TI recommends connecting a combination of a 10-µF and a 0.1-µF low-ESR ceramic decoupling capacitor across the VDD and VSS pins, as well as placing these capacitors as close as possible to the supply pins that they decouple (within a few millimeters) to achieve a minimal loop area. The 10-µF bulk decoupling capacitor is a recommended value for most applications, but this capacitance may be adjusted if needed based upon the PCB design and application requirements. For example, larger bulk capacitors can be used, but this can affect the supply rail ramp-up time. The NRST reset pin must be pulled up to VDD (supply level) for the device to release from RESET state and start the boot process. TI recommends connecting an external 47-kΩ pullup resistor with a 10-nF pulldown capacitor for most applications, enabling the NRST pin to be controlled by another device or a debug probe. The SYSOSC frequency correction loop (FCL) circuit utilizes an external 100-kΩ with 0.1% tolerance resistor with a temperature coefficient (TCR) of 25ppm/C or better populated between the ROSC pin and VSS. This resistor establishes a reference current to stabilize the SYSOSC frequency through a correction loop. This resistor is required if the FCL feature is used for higher accuracy, and it is not required if the SYSOSC FCL is not enabled. When the FCL mode is not used, the PA2 pin may be used as a digital input/output pin. A 0.47-µF tank capacitor is required for the VCORE pin and must be placed close to the device with minimum distance to the device ground. Do not connect other circuits to the VCORE pin. For the 5-V-tolerant open drain (ODIO), a pullup resistor is required to output high for I2C and UART functions, as the open drain IO only implement a low-side NMOS driver and no high-side PMOS driver. The 5V-tolerant open drain IO are fail-safe and may have a voltage present even if VDD is not supplied. Basic Application Schematic TI recommends connecting a combination of a 10-µF and a 0.1-µF low-ESR ceramic decoupling capacitor across the VDD and VSS pins, as well as placing these capacitors as close as possible to the supply pins that they decouple (within a few millimeters) to achieve a minimal loop area. The 10-µF bulk decoupling capacitor is a recommended value for most applications, but this capacitance may be adjusted if needed based upon the PCB design and application requirements. For example, larger bulk capacitors can be used, but this can affect the supply rail ramp-up time. The NRST reset pin must be pulled up to VDD (supply level) for the device to release from RESET state and start the boot process. TI recommends connecting an external 47-kΩ pullup resistor with a 10-nF pulldown capacitor for most applications, enabling the NRST pin to be controlled by another device or a debug probe. The SYSOSC frequency correction loop (FCL) circuit utilizes an external 100-kΩ with 0.1% tolerance resistor with a temperature coefficient (TCR) of 25ppm/C or better populated between the ROSC pin and VSS. This resistor establishes a reference current to stabilize the SYSOSC frequency through a correction loop. This resistor is required if the FCL feature is used for higher accuracy, and it is not required if the SYSOSC FCL is not enabled. When the FCL mode is not used, the PA2 pin may be used as a digital input/output pin. A 0.47-µF tank capacitor is required for the VCORE pin and must be placed close to the device with minimum distance to the device ground. Do not connect other circuits to the VCORE pin. For the 5-V-tolerant open drain (ODIO), a pullup resistor is required to output high for I2C and UART functions, as the open drain IO only implement a low-side NMOS driver and no high-side PMOS driver. The 5V-tolerant open drain IO are fail-safe and may have a voltage present even if VDD is not supplied. Basic Application Schematic TI recommends connecting a combination of a 10-µF and a 0.1-µF low-ESR ceramic decoupling capacitor across the VDD and VSS pins, as well as placing these capacitors as close as possible to the supply pins that they decouple (within a few millimeters) to achieve a minimal loop area. The 10-µF bulk decoupling capacitor is a recommended value for most applications, but this capacitance may be adjusted if needed based upon the PCB design and application requirements. For example, larger bulk capacitors can be used, but this can affect the supply rail ramp-up time.The NRST reset pin must be pulled up to VDD (supply level) for the device to release from RESET state and start the boot process. TI recommends connecting an external 47-kΩ pullup resistor with a 10-nF pulldown capacitor for most applications, enabling the NRST pin to be controlled by another device or a debug probe.The SYSOSC frequency correction loop (FCL) circuit utilizes an external 100-kΩ with 0.1% tolerance resistor with a temperature coefficient (TCR) of 25ppm/C or better populated between the ROSC pin and VSS. This resistor establishes a reference current to stabilize the SYSOSC frequency through a correction loop. This resistor is required if the FCL feature is used for higher accuracy, and it is not required if the SYSOSC FCL is not enabled. When the FCL mode is not used, the PA2 pin may be used as a digital input/output pin.A 0.47-µF tank capacitor is required for the VCORE pin and must be placed close to the device with minimum distance to the device ground. Do not connect other circuits to the VCORE pin.For the 5-V-tolerant open drain (ODIO), a pullup resistor is required to output high for I2C and UART functions, as the open drain IO only implement a low-side NMOS driver and no high-side PMOS driver. The 5V-tolerant open drain IO are fail-safe and may have a voltage present even if VDD is not supplied. Basic Application Schematic Basic Application Schematic Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. Getting Started and Next Steps Device Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP MCU devices and support tools. Each MSP MCU automotive family member has one of two prefixes: M0 or XM0. These prefixes represent evolutionary stages of product development from engineering prototypes (XM0) through fully qualified production devices (M0). X or XMS – Experimental device that is not necessarily representative of the final device's electrical specifications M0 – Fully qualified production device X and XMS devices are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (X) have a greater failure rate than the standard production devices. TI recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature range, package type, and distribution format. provides a legend for reading the complete device name. Device Nomenclature Device Nomenclature MCU Platform M0 = Arm-based 32-bit M0+XM0 = Experimental silicon Arm-based 32-bit M0+ Product Family L = 32-MHz frequency Device Subfamily 130 = ADC, 2x OPA, COMP Internal Memory 4 = 16KB flash, 2KB SRAM 5 = 32KB flash, 4KB SRAM 6 = 64KB flash, 4KB SRAM Temperature Range Q = –40°C to 125°C , AEC-Q100 qualified Package Type See and www.ti.com/packaging Distribution Format T = Small reel R = Large reel No marking = Tube or tray Qualification Q1 = Qualified for automotive applications For orderable part numbers of MSP devices in different package types, see the Package Option Addendum of this document, ti.com, or contact your TI sales representative. Tools and Software Design Kits and Evaluation Modules MSPM0 LaunchPad Development Kit: LP-MSPM0L1306 Empowers you to immediately start developing on the industry’s best integrated analog and most cost-optimized general purpose MSPM0 MCU family. Exposes all device pins and functionality; includes some built-in circuitry, out-of-box software demos, and on-board XDS110 debug probe for programming, debugging, and EnergyTrace technology. The LaunchPad ecosystem includes dozens of BoosterPack stackable plug-in modules to extend functionality. Embedded Software MSPM0 Software Development Kit (SDK) Contains software drivers, middleware libraries, documentation, tools, and code examples that create a familiar and easy user experience for all MSPM0 devices. Software Development Tools TI Cloud Tools Start your evaluation and development on a web browser without any installation. Cloud tools also have a downloadable, offline version. TI Resource Explorer Online portal to TI SDKs. Accessible in CCS IDE or in TI Cloud Tools. SysConfig Intuitive GUI to configure device and peripherals, resolve system conflicts, generate configuration code, and automate pin mux settings. Accessible in CCS IDE or in TI Cloud Tools. (offline version) MSP Academy Great starting point for all developers to learn about the MSPM0 MCU Platform with training modules that span a wide range of topics. Part of TIRex. GUI Composer GUIs that simplify evaluation of certain MSPM0 features, such as configuring and monitoring a fully integrated analog signal chain without any code needed. IDE and compiler tool chains Code Composer Studio™ (CCS) Includes TI Arm-Clang compiler. Supports all TI Arm Cortex MCUs and boasts competitive code size performance advantages, fast compile time, code coverage support, safety certification support, and completely free to use. IAR Embedded Workbench® IDE Keil® MDK IDE GNU Arm Embedded Tool Chain Documentation Support To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.The following documents describe the MSPM0 MCUs. Copies of these documents are available on the Internet at www.ti.com. Technical Reference Manual MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual This manual describes the modules and peripherals of the MSPM0L family of devices. Each description presents the module or peripheral in a general sense. Not all features and functions of all modules or peripherals are present on all devices. In addition, modules or peripherals can differ in their exact implementation on different devices. Pin functions, internal signal connections, and operational parameters differ from device to device. See the device-specific data sheet for these details. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Trademarks Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. Getting Started and Next Steps Getting Started and Next Steps Device Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP MCU devices and support tools. Each MSP MCU automotive family member has one of two prefixes: M0 or XM0. These prefixes represent evolutionary stages of product development from engineering prototypes (XM0) through fully qualified production devices (M0). X or XMS – Experimental device that is not necessarily representative of the final device's electrical specifications M0 – Fully qualified production device X and XMS devices are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (X) have a greater failure rate than the standard production devices. TI recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature range, package type, and distribution format. provides a legend for reading the complete device name. Device Nomenclature Device Nomenclature MCU Platform M0 = Arm-based 32-bit M0+XM0 = Experimental silicon Arm-based 32-bit M0+ Product Family L = 32-MHz frequency Device Subfamily 130 = ADC, 2x OPA, COMP Internal Memory 4 = 16KB flash, 2KB SRAM 5 = 32KB flash, 4KB SRAM 6 = 64KB flash, 4KB SRAM Temperature Range Q = –40°C to 125°C , AEC-Q100 qualified Package Type See and www.ti.com/packaging Distribution Format T = Small reel R = Large reel No marking = Tube or tray Qualification Q1 = Qualified for automotive applications For orderable part numbers of MSP devices in different package types, see the Package Option Addendum of this document, ti.com, or contact your TI sales representative. Device Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP MCU devices and support tools. Each MSP MCU automotive family member has one of two prefixes: M0 or XM0. These prefixes represent evolutionary stages of product development from engineering prototypes (XM0) through fully qualified production devices (M0). X or XMS – Experimental device that is not necessarily representative of the final device's electrical specifications M0 – Fully qualified production device X and XMS devices are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (X) have a greater failure rate than the standard production devices. TI recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature range, package type, and distribution format. provides a legend for reading the complete device name. Device Nomenclature Device Nomenclature MCU Platform M0 = Arm-based 32-bit M0+XM0 = Experimental silicon Arm-based 32-bit M0+ Product Family L = 32-MHz frequency Device Subfamily 130 = ADC, 2x OPA, COMP Internal Memory 4 = 16KB flash, 2KB SRAM 5 = 32KB flash, 4KB SRAM 6 = 64KB flash, 4KB SRAM Temperature Range Q = –40°C to 125°C , AEC-Q100 qualified Package Type See and www.ti.com/packaging Distribution Format T = Small reel R = Large reel No marking = Tube or tray Qualification Q1 = Qualified for automotive applications For orderable part numbers of MSP devices in different package types, see the Package Option Addendum of this document, ti.com, or contact your TI sales representative. To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP MCU devices and support tools. Each MSP MCU automotive family member has one of two prefixes: M0 or XM0. These prefixes represent evolutionary stages of product development from engineering prototypes (XM0) through fully qualified production devices (M0). X or XMS – Experimental device that is not necessarily representative of the final device's electrical specifications M0 – Fully qualified production device X and XMS devices are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (X) have a greater failure rate than the standard production devices. TI recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature range, package type, and distribution format. provides a legend for reading the complete device name. To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP MCU devices and support tools. Each MSP MCU automotive family member has one of two prefixes: M0 or XM0. These prefixes represent evolutionary stages of product development from engineering prototypes (XM0) through fully qualified production devices (M0). X or XMS – Experimental device that is not necessarily representative of the final device's electrical specifications X or XMS M0 – Fully qualified production deviceM0 X and XMS devices are shipped against the following disclaimer:X and XMS"Developmental product is intended for internal evaluation purposes." MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (X) have a greater failure rate than the standard production devices. TI recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature range, package type, and distribution format. provides a legend for reading the complete device name. Device Nomenclature Device Nomenclature MCU Platform M0 = Arm-based 32-bit M0+XM0 = Experimental silicon Arm-based 32-bit M0+ Product Family L = 32-MHz frequency Device Subfamily 130 = ADC, 2x OPA, COMP Internal Memory 4 = 16KB flash, 2KB SRAM 5 = 32KB flash, 4KB SRAM 6 = 64KB flash, 4KB SRAM Temperature Range Q = –40°C to 125°C , AEC-Q100 qualified Package Type See and www.ti.com/packaging Distribution Format T = Small reel R = Large reel No marking = Tube or tray Qualification Q1 = Qualified for automotive applications For orderable part numbers of MSP devices in different package types, see the Package Option Addendum of this document, ti.com, or contact your TI sales representative. Device Nomenclature Device Nomenclature Device Nomenclature MCU Platform M0 = Arm-based 32-bit M0+XM0 = Experimental silicon Arm-based 32-bit M0+ Product Family L = 32-MHz frequency Device Subfamily 130 = ADC, 2x OPA, COMP Internal Memory 4 = 16KB flash, 2KB SRAM 5 = 32KB flash, 4KB SRAM 6 = 64KB flash, 4KB SRAM Temperature Range Q = –40°C to 125°C , AEC-Q100 qualified Package Type See and www.ti.com/packaging Distribution Format T = Small reel R = Large reel No marking = Tube or tray Qualification Q1 = Qualified for automotive applications Device Nomenclature MCU Platform M0 = Arm-based 32-bit M0+XM0 = Experimental silicon Arm-based 32-bit M0+ Product Family L = 32-MHz frequency Device Subfamily 130 = ADC, 2x OPA, COMP Internal Memory 4 = 16KB flash, 2KB SRAM 5 = 32KB flash, 4KB SRAM 6 = 64KB flash, 4KB SRAM Temperature Range Q = –40°C to 125°C , AEC-Q100 qualified Package Type See and www.ti.com/packaging Distribution Format T = Small reel R = Large reel No marking = Tube or tray Qualification Q1 = Qualified for automotive applications MCU Platform M0 = Arm-based 32-bit M0+XM0 = Experimental silicon Arm-based 32-bit M0+ Product Family L = 32-MHz frequency Device Subfamily 130 = ADC, 2x OPA, COMP Internal Memory 4 = 16KB flash, 2KB SRAM 5 = 32KB flash, 4KB SRAM 6 = 64KB flash, 4KB SRAM Temperature Range Q = –40°C to 125°C , AEC-Q100 qualified Package Type See and www.ti.com/packaging Distribution Format T = Small reel R = Large reel No marking = Tube or tray Qualification Q1 = Qualified for automotive applications MCU Platform M0 = Arm-based 32-bit M0+XM0 = Experimental silicon Arm-based 32-bit M0+ MCU Platform MCU PlatformM0 = Arm-based 32-bit M0+XM0 = Experimental silicon Arm-based 32-bit M0+ XM0 = Experimental silicon Arm-based 32-bit M0+ Product Family L = 32-MHz frequency Product Family Product FamilyL = 32-MHz frequency Device Subfamily 130 = ADC, 2x OPA, COMP Device Subfamily Device Subfamily 130 = ADC, 2x OPA, COMP 130 = ADC, 2x OPA, COMP Internal Memory 4 = 16KB flash, 2KB SRAM 5 = 32KB flash, 4KB SRAM 6 = 64KB flash, 4KB SRAM Internal Memory Internal Memory 4 = 16KB flash, 2KB SRAM 5 = 32KB flash, 4KB SRAM 6 = 64KB flash, 4KB SRAM 4 = 16KB flash, 2KB SRAM5 = 32KB flash, 4KB SRAM6 = 64KB flash, 4KB SRAM Temperature Range Q = –40°C to 125°C , AEC-Q100 qualified Temperature Range Temperature Range Q = –40°C to 125°C , AEC-Q100 qualified Q = –40°C to 125°C , AEC-Q100 qualified Package Type See and www.ti.com/packaging Package Type Package TypeSee and www.ti.com/packaging and Distribution Format T = Small reel R = Large reel No marking = Tube or tray Distribution Format Distribution Format T = Small reel R = Large reel No marking = Tube or tray T = Small reel R = Large reel No marking = Tube or tray Qualification Q1 = Qualified for automotive applications Qualification QualificationQ1 = Qualified for automotive applicationsFor orderable part numbers of MSP devices in different package types, see the Package Option Addendum of this document, ti.com, or contact your TI sales representative.ti.com Tools and Software Design Kits and Evaluation Modules MSPM0 LaunchPad Development Kit: LP-MSPM0L1306 Empowers you to immediately start developing on the industry’s best integrated analog and most cost-optimized general purpose MSPM0 MCU family. Exposes all device pins and functionality; includes some built-in circuitry, out-of-box software demos, and on-board XDS110 debug probe for programming, debugging, and EnergyTrace technology. The LaunchPad ecosystem includes dozens of BoosterPack stackable plug-in modules to extend functionality. Embedded Software MSPM0 Software Development Kit (SDK) Contains software drivers, middleware libraries, documentation, tools, and code examples that create a familiar and easy user experience for all MSPM0 devices. Software Development Tools TI Cloud Tools Start your evaluation and development on a web browser without any installation. Cloud tools also have a downloadable, offline version. TI Resource Explorer Online portal to TI SDKs. Accessible in CCS IDE or in TI Cloud Tools. SysConfig Intuitive GUI to configure device and peripherals, resolve system conflicts, generate configuration code, and automate pin mux settings. Accessible in CCS IDE or in TI Cloud Tools. (offline version) MSP Academy Great starting point for all developers to learn about the MSPM0 MCU Platform with training modules that span a wide range of topics. Part of TIRex. GUI Composer GUIs that simplify evaluation of certain MSPM0 features, such as configuring and monitoring a fully integrated analog signal chain without any code needed. IDE and compiler tool chains Code Composer Studio™ (CCS) Includes TI Arm-Clang compiler. Supports all TI Arm Cortex MCUs and boasts competitive code size performance advantages, fast compile time, code coverage support, safety certification support, and completely free to use. IAR Embedded Workbench® IDE Keil® MDK IDE GNU Arm Embedded Tool Chain Tools and Software Design Kits and Evaluation Modules MSPM0 LaunchPad Development Kit: LP-MSPM0L1306 Empowers you to immediately start developing on the industry’s best integrated analog and most cost-optimized general purpose MSPM0 MCU family. Exposes all device pins and functionality; includes some built-in circuitry, out-of-box software demos, and on-board XDS110 debug probe for programming, debugging, and EnergyTrace technology. The LaunchPad ecosystem includes dozens of BoosterPack stackable plug-in modules to extend functionality. Embedded Software MSPM0 Software Development Kit (SDK) Contains software drivers, middleware libraries, documentation, tools, and code examples that create a familiar and easy user experience for all MSPM0 devices. Software Development Tools TI Cloud Tools Start your evaluation and development on a web browser without any installation. Cloud tools also have a downloadable, offline version. TI Resource Explorer Online portal to TI SDKs. Accessible in CCS IDE or in TI Cloud Tools. SysConfig Intuitive GUI to configure device and peripherals, resolve system conflicts, generate configuration code, and automate pin mux settings. Accessible in CCS IDE or in TI Cloud Tools. (offline version) MSP Academy Great starting point for all developers to learn about the MSPM0 MCU Platform with training modules that span a wide range of topics. Part of TIRex. GUI Composer GUIs that simplify evaluation of certain MSPM0 features, such as configuring and monitoring a fully integrated analog signal chain without any code needed. IDE and compiler tool chains Code Composer Studio™ (CCS) Includes TI Arm-Clang compiler. Supports all TI Arm Cortex MCUs and boasts competitive code size performance advantages, fast compile time, code coverage support, safety certification support, and completely free to use. IAR Embedded Workbench® IDE Keil® MDK IDE GNU Arm Embedded Tool Chain Design Kits and Evaluation Modules MSPM0 LaunchPad Development Kit: LP-MSPM0L1306 Empowers you to immediately start developing on the industry’s best integrated analog and most cost-optimized general purpose MSPM0 MCU family. Exposes all device pins and functionality; includes some built-in circuitry, out-of-box software demos, and on-board XDS110 debug probe for programming, debugging, and EnergyTrace technology. The LaunchPad ecosystem includes dozens of BoosterPack stackable plug-in modules to extend functionality. Embedded Software MSPM0 Software Development Kit (SDK) Contains software drivers, middleware libraries, documentation, tools, and code examples that create a familiar and easy user experience for all MSPM0 devices. Software Development Tools TI Cloud Tools Start your evaluation and development on a web browser without any installation. Cloud tools also have a downloadable, offline version. TI Resource Explorer Online portal to TI SDKs. Accessible in CCS IDE or in TI Cloud Tools. SysConfig Intuitive GUI to configure device and peripherals, resolve system conflicts, generate configuration code, and automate pin mux settings. Accessible in CCS IDE or in TI Cloud Tools. (offline version) MSP Academy Great starting point for all developers to learn about the MSPM0 MCU Platform with training modules that span a wide range of topics. Part of TIRex. GUI Composer GUIs that simplify evaluation of certain MSPM0 features, such as configuring and monitoring a fully integrated analog signal chain without any code needed. IDE and compiler tool chains Code Composer Studio™ (CCS) Includes TI Arm-Clang compiler. Supports all TI Arm Cortex MCUs and boasts competitive code size performance advantages, fast compile time, code coverage support, safety certification support, and completely free to use. IAR Embedded Workbench® IDE Keil® MDK IDE GNU Arm Embedded Tool Chain Design Kits and Evaluation Modules Design Kits and Evaluation Modules MSPM0 LaunchPad Development Kit: LP-MSPM0L1306 Empowers you to immediately start developing on the industry’s best integrated analog and most cost-optimized general purpose MSPM0 MCU family. Exposes all device pins and functionality; includes some built-in circuitry, out-of-box software demos, and on-board XDS110 debug probe for programming, debugging, and EnergyTrace technology. The LaunchPad ecosystem includes dozens of BoosterPack stackable plug-in modules to extend functionality. Embedded Software MSPM0 Software Development Kit (SDK) Contains software drivers, middleware libraries, documentation, tools, and code examples that create a familiar and easy user experience for all MSPM0 devices. Software Development Tools TI Cloud Tools Start your evaluation and development on a web browser without any installation. Cloud tools also have a downloadable, offline version. TI Resource Explorer Online portal to TI SDKs. Accessible in CCS IDE or in TI Cloud Tools. SysConfig Intuitive GUI to configure device and peripherals, resolve system conflicts, generate configuration code, and automate pin mux settings. Accessible in CCS IDE or in TI Cloud Tools. (offline version) MSP Academy Great starting point for all developers to learn about the MSPM0 MCU Platform with training modules that span a wide range of topics. Part of TIRex. GUI Composer GUIs that simplify evaluation of certain MSPM0 features, such as configuring and monitoring a fully integrated analog signal chain without any code needed. IDE and compiler tool chains Code Composer Studio™ (CCS) Includes TI Arm-Clang compiler. Supports all TI Arm Cortex MCUs and boasts competitive code size performance advantages, fast compile time, code coverage support, safety certification support, and completely free to use. IAR Embedded Workbench® IDE Keil® MDK IDE GNU Arm Embedded Tool Chain MSPM0 LaunchPad Development Kit: LP-MSPM0L1306 Empowers you to immediately start developing on the industry’s best integrated analog and most cost-optimized general purpose MSPM0 MCU family. Exposes all device pins and functionality; includes some built-in circuitry, out-of-box software demos, and on-board XDS110 debug probe for programming, debugging, and EnergyTrace technology. The LaunchPad ecosystem includes dozens of BoosterPack stackable plug-in modules to extend functionality. MSPM0 LaunchPad Development Kit: LP-MSPM0L1306 MSPM0 LaunchPad Development Kit: LP-MSPM0L1306 Empowers you to immediately start developing on the industry’s best integrated analog and most cost-optimized general purpose MSPM0 MCU family. Exposes all device pins and functionality; includes some built-in circuitry, out-of-box software demos, and on-board XDS110 debug probe for programming, debugging, and EnergyTrace technology.EnergyTraceThe LaunchPad ecosystem includes dozens of BoosterPack stackable plug-in modules to extend functionality. BoosterPack BoosterPack Embedded Software Embedded Software Embedded Software MSPM0 Software Development Kit (SDK) Contains software drivers, middleware libraries, documentation, tools, and code examples that create a familiar and easy user experience for all MSPM0 devices. MSPM0 Software Development Kit (SDK) MSPM0 Software Development Kit (SDK) Contains software drivers, middleware libraries, documentation, tools, and code examples that create a familiar and easy user experience for all MSPM0 devices. Contains software drivers, middleware libraries, documentation, tools, and code examples that create a familiar and easy user experience for all MSPM0 devices. Software Development Tools Software Development Tools Software Development Tools TI Cloud Tools Start your evaluation and development on a web browser without any installation. Cloud tools also have a downloadable, offline version. TI Cloud Tools TI Cloud ToolsStart your evaluation and development on a web browser without any installation. Cloud tools also have a downloadable, offline version. TI Resource Explorer Online portal to TI SDKs. Accessible in CCS IDE or in TI Cloud Tools. TI Resource Explorer TI Resource Explorer Online portal to TI SDKs. Accessible in CCS IDE or in TI Cloud Tools. SysConfig Intuitive GUI to configure device and peripherals, resolve system conflicts, generate configuration code, and automate pin mux settings. Accessible in CCS IDE or in TI Cloud Tools. (offline version) SysConfig SysConfig Intuitive GUI to configure device and peripherals, resolve system conflicts, generate configuration code, and automate pin mux settings. Accessible in CCS IDE or in TI Cloud Tools. (offline version) (offline version) MSP Academy Great starting point for all developers to learn about the MSPM0 MCU Platform with training modules that span a wide range of topics. Part of TIRex. MSP Academy MSP AcademyGreat starting point for all developers to learn about the MSPM0 MCU Platform with training modules that span a wide range of topics. Part of TIRex. GUI Composer GUIs that simplify evaluation of certain MSPM0 features, such as configuring and monitoring a fully integrated analog signal chain without any code needed. GUI Composer GUI Composer GUIs that simplify evaluation of certain MSPM0 features, such as configuring and monitoring a fully integrated analog signal chain without any code needed. IDE and compiler tool chains IDE and compiler tool chains IDE and compiler tool chains Code Composer Studio™ (CCS) Includes TI Arm-Clang compiler. Supports all TI Arm Cortex MCUs and boasts competitive code size performance advantages, fast compile time, code coverage support, safety certification support, and completely free to use. Code Composer Studio™ (CCS) Code Composer Studio™ (CCS) Includes TI Arm-Clang compiler. Supports all TI Arm Cortex MCUs and boasts competitive code size performance advantages, fast compile time, code coverage support, safety certification support, and completely free to use.TI Arm-Clang IAR Embedded Workbench® IDE IAR Embedded Workbench® IDE IAR Embedded Workbench® IDE Keil® MDK IDE Keil® MDK IDE Keil® MDK IDE GNU Arm Embedded Tool Chain GNU Arm Embedded Tool Chain GNU Arm Embedded Tool Chain Documentation Support To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.The following documents describe the MSPM0 MCUs. Copies of these documents are available on the Internet at www.ti.com. Technical Reference Manual MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual This manual describes the modules and peripherals of the MSPM0L family of devices. Each description presents the module or peripheral in a general sense. Not all features and functions of all modules or peripherals are present on all devices. In addition, modules or peripherals can differ in their exact implementation on different devices. Pin functions, internal signal connections, and operational parameters differ from device to device. See the device-specific data sheet for these details. Documentation Support To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.The following documents describe the MSPM0 MCUs. Copies of these documents are available on the Internet at www.ti.com. Technical Reference Manual MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual This manual describes the modules and peripherals of the MSPM0L family of devices. Each description presents the module or peripheral in a general sense. Not all features and functions of all modules or peripherals are present on all devices. In addition, modules or peripherals can differ in their exact implementation on different devices. Pin functions, internal signal connections, and operational parameters differ from device to device. See the device-specific data sheet for these details. To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.The following documents describe the MSPM0 MCUs. Copies of these documents are available on the Internet at www.ti.com.To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.ti.comNotificationswww.ti.com Technical Reference Manual MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual This manual describes the modules and peripherals of the MSPM0L family of devices. Each description presents the module or peripheral in a general sense. Not all features and functions of all modules or peripherals are present on all devices. In addition, modules or peripherals can differ in their exact implementation on different devices. Pin functions, internal signal connections, and operational parameters differ from device to device. See the device-specific data sheet for these details. Technical Reference Manual MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual This manual describes the modules and peripherals of the MSPM0L family of devices. Each description presents the module or peripheral in a general sense. Not all features and functions of all modules or peripherals are present on all devices. In addition, modules or peripherals can differ in their exact implementation on different devices. Pin functions, internal signal connections, and operational parameters differ from device to device. See the device-specific data sheet for these details. MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual This manual describes the modules and peripherals of the MSPM0L family of devices. Each description presents the module or peripheral in a general sense. Not all features and functions of all modules or peripherals are present on all devices. In addition, modules or peripherals can differ in their exact implementation on different devices. Pin functions, internal signal connections, and operational parameters differ from device to device. See the device-specific data sheet for these details. MSPM0 L-Series 32-MHz Microcontrollers Technical Reference Manual MSPM0 L-Series 32-MHz Microcontrollers Technical Reference ManualThis manual describes the modules and peripherals of the MSPM0L family of devices. Each description presents the module or peripheral in a general sense. Not all features and functions of all modules or peripherals are present on all devices. In addition, modules or peripherals can differ in their exact implementation on different devices. Pin functions, internal signal connections, and operational parameters differ from device to device. See the device-specific data sheet for these details. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. Support Resources TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. TI E2E support forumsTI E2ELinked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.Terms of Use Trademarks Trademarks Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary This glossary lists and explains terms, acronyms, and definitions. TI Glossary TI GlossaryThis glossary lists and explains terms, acronyms, and definitions. Revision History yes 20230524 20231219 Revision History yes 20230524 20231219 yes 20230524 20231219 yes2023052420231219 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 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Distribution Format	T = Small reel R = Large reel No marking = Tube or tray
Qualification	Q1 = Qualified for automotive applications

For orderable part numbers of MSP devices in different package types, see the Package Option Addendum of this document, ti.com, or contact your TI sales representative.