SLASF94A May 2024 – October 2024 MSPM0L1227 , MSPM0L1228 , MSPM0L2227 , MSPM0L2228
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
The direct memory access (DMA) controller allows movement of data from one memory address to another without CPU intervention. For example, the DMA can be used to move data from ADC conversion memory to SRAM. The DMA reduces system power consumption by allowing the CPU to remain in low power mode, without having to awaken to move data to or from a peripheral.
The DMA in these devices support the following key features:
Table 8-2 lists the available triggers for the DMA which are configured using the DMATCTL.DMATSEL control bits in the DMA memory mapped registers.
DMACTL.DMATSEL | TRIGGER SOURCE | DMACTL.DMATSEL | TRIGGER SOURCE |
---|---|---|---|
0 | Software | 13 | SPI1 Publisher 1 |
1 | Generic Subscriber 0 (FSUB_0) | 14 | SPI1 Publisher 2 |
2 | Generic Subscriber 0 (FSUB_1) | 15 | UART0 Publisher 1 |
3 | AES Publisher 1 | 16 | UART0 Publisher 2 |
4 | AES Publisher 1 | 17 | UART1 Publisher 1 |
5 | I2C0 Publisher 1 | 18 | UART1 Publisher 2 |
6 | I2C0 Publisher 2 | 19 | UART2 Publisher 1 |
7 | I2C1 Publisher 1 | 20 | UART2 Publisher 2 |
8 | I2C1 Publisher 2 | 21 | UART3 Publisher 1 |
9 | I2C2 Publisher 1 | 22 | UART3 Publisher 2 |
10 | I2C2 Publisher 2 | 23 | UART4 Publisher 1 |
11 | SPI0 Publisher 1 | 24 | UART4 Publisher 2 |
12 | SPI1 Publisher 2 | 25 | ADC0 Publisher 2 |
For more details, see the DMA chapter of the MSPM0 L-Series 32MHz Microcontrollers Technical Reference Manual.