SBOSA00B December   2019  – August 2020 OPA1637

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Characterization Configuration
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Super-Beta Input Bipolar Transistors
      2. 8.3.2 Power Down
      3. 8.3.3 Flexible Gain Setting
      4. 8.3.4 Amplifier Overload Power Limit
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Driving Capacitive Loads
      2. 9.1.2 Operating the Power-Down Feature
      3. 9.1.3 I/O Headroom Considerations
      4. 9.1.4 Noise Performance
    2. 9.2 Typical Applications
      1. 9.2.1 Current-Output Audio DAC Buffer to Class-D Amplifier
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 An MFB Filter Driving an ADC Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Differential Microphone Input to Line Level
        1. 9.2.3.1 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Layout Recommendations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.1.2 Operating the Power-Down Feature

The power-down feature on the OPA1637 allows the device to be put into a low power-consumption state, in which quiescent current is minimized. To force the device into the low-power state, drive the PD pin lower than the power-down threshold voltage (VVS+ – 2 V). Driving the PD pin lower than the power-down threshold voltage forces the internal logic to disable both the differential and common-mode amplifiers. The PD pin has an internal pullup current that allows the pin to be used in an open-drain MOSFET configuration without an additional pullup resistor, as seen in Figure 9-2. In this configuration, the logic level can be referenced to the MOSFET, and the voltage at the PD pin is level-shifted to account for use with high supply voltages. Be sure to select an N-type MOSFET with a maximum BVDSS greater than the total supply voltage. For applications that do not use the power-down feature, tie the PD pin to the positive supply voltage.

GUID-439F1FF4-3907-484E-B753-CE88257A64CB-low.gifFigure 9-2 Power-Down ( PD) Pin Interface With Low-Voltage Logic Level Signals

When PD is low (device is in power down) the output pins will be in a high-impedance state. When the device is in the power-down state, the outputs are high impedance, and the output voltage is no longer controlled by the amplifier, but dependant on the input and load configuration. In this case, the input voltage between IN– and IN+ can drift to a voltage that may forward-bias the input protection diodes. Take care to avoid high currents flowing through the input diodes by using an input resistor to limit the current to less than 10 mA. In Figure 9-3, the OPA1637 is configured in a differential gain of 5 with 100-Ω input resistors. When the device enters power down, the voltage between IN– and IN+ increases until the internal protection diode is forward-biased. In this case, exceeding a voltage on VIN with RIN= 0 Ω of 2.5 V (diode forward voltage estimated at 0.5 V) results in a current greater than 10 mA. To avoid this high current, select RIN so that the maximum current flow is less than 10 mA when VIN is at maximum voltage.

GUID-39A44E4B-58C6-464C-B021-5BC926F4AEF4-low.gifFigure 9-3 Path of Input Current Flow When PD = Low