SBOS981J October   2019  – April 2021 OPA2607 , OPA607

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Operating Voltage
      2. 8.3.2 Rail-to-Rail Output and Driving Capacitive Loads
      3. 8.3.3 Input and ESD Protection
      4. 8.3.4 Decompensated Architecture with Wide Gain-Bandwidth Product
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operating Mode
      2. 8.4.2 Power Down Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 100-kΩ Gain Transimpedance Design
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Noninverting Gain of 3 V/V
      3. 9.2.3 High-Input Impedance (Hi-Z), High-Gain Signal Front-End
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
        3. 9.2.3.3 Application Curves
      4. 9.2.4 Low-Cost, Low Side, High-Speed Current Sensing
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
        3. 9.2.4.3 Application Curves
      5. 9.2.5 Ultrasonic Flow Meters
        1. 9.2.5.1 Design Requirements
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Support Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4.2 Power Down Mode

The OPAx607 devices feature a Power Down mode for power critical applications. Under logic control, the amplifier can be switched from normal operation (consuming ≤ 1 mA) to a Power Down current of less than 1 µA. When the PD pin is connected high, the amplifier is active. Connecting the PD pin to logic low disables the amplifier and places the output in a high-impedance state. The output of an op amp is high impedance similar to a tri-state high-impedance gate under a Power Down condition; however, the feedback network behaves as a parallel load.

If the Power Down mode is not used, connect PD to the positive supply pin or leave floating. See the Power Down (Device Enabled When Floating) section in Section 7.5 table for the enable and disable threshold voltages. The PD pin can be left floating to keep the op amp always enabled, which is primarily possible because of the presence of an internal pullup resistor within the op amp that, by default, always keeps the PD pin weakly tied to VS+. However it is also acceptable to strengthen the pull up from the PD pin by connecting a low value resistance from the PD pin to VS+. This helps make the part less susceptible to noise and transient pick up on the PD pin. Looking at the PD pin bias current in Figure 7-21 can help us get an accurate understanding of the voltage required to be applied on the PD pin for enabling and powering down. Note: the hysteresis present in Figure 7-21 help with single shot power up and power down of OPAx607 devices.

The PD pin exhibits a special type of ESD protection which allows users to apply any voltage between VS– to 6 V irrespective of the voltage at the VS+. Special ESD structure at the PD pin helps in relaxing the requirements on power sequencing during power up and power down condition. Refer to Figure 8-4 for details of the internal ESD structure. The absolute voltage limits applicable on PD pin can be found in Section 7.1 table. Another key care about in PD condition is to ensure the IN+ and IN– are not exposed to a high differential voltage continuously. In a power up condition the op-amp's loop gain ensure the IN+ pin and the IN– track each other closely. However in PD condition the op-amp is inactive and IN– will be usually weakly tied to GND through the RG resistor. Exposing the IN+ pin continuously to a high voltage in such a condition will result in irreversible offset voltage (VOS) shift.