SBOS309E August   2004  – December 2024 OPA2830

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configurations and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics VS = ±5V
    6. 6.6  Electrical Characteristics VS = 5V
    7. 6.7  Electrical Characteristics VS = 3V
    8. 6.8  Typical Characteristics: VS = ±5V
    9. 6.9  Typical Characteristics: VS = ±5V, Differential Configuration
    10. 6.10 Typical Characteristics: VS = 5V
    11. 6.11 Typical Characteristics: VS = 5V, Differential Configuration
    12. 6.12 Typical Characteristics: VS = 3V
    13. 6.13 Typical Characteristics: VS = 3V, Differential Configuration
  8. Parameter Measurement Information
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Wideband Voltage-Feedback Operation
      2. 8.1.2  Single-Supply ADC Interface
      3. 8.1.3  DC Level-Shifting
      4. 8.1.4  AC-Coupled Output Video Line Driver
      5. 8.1.5  Noninverting Amplifier With Reduced Peaking
      6. 8.1.6  Single-Supply Active Filter
      7. 8.1.7  Differential Low-Pass Active Filters
      8. 8.1.8  High-Pass Filters
      9. 8.1.9  High-Performance DAC Transimpedance Amplifier
      10. 8.1.10 Operating Suggestions Optimizing Resistor Values
      11. 8.1.11 Bandwidth vs Gain: Noninverting Operation
      12. 8.1.12 Inverting Amplifier Operation
      13. 8.1.13 Output Current and Voltages
      14. 8.1.14 Driving Capacitive Loads
      15. 8.1.15 Distortion Performance
      16. 8.1.16 Noise Performance
      17. 8.1.17 DC Accuracy and Offset Control
    2. 8.2 Power Supply Recommendations
      1. 8.2.1 Thermal Analysis
    3. 8.3 Layout
      1. 8.3.1 Board Layout Guidelines
        1. 8.3.1.1 Input and ESD Protection
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Design-In Tools
        1. 9.1.1.1 Demonstration Fixtures
        2. 9.1.1.2 Macro-model and Applications Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DGK|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Thermal Analysis

The maximum desired junction temperature sets the maximum allowed internal power dissipation. Do not exceed the maximum junction temperature of 150°C.

The operating junction temperature (TJ) is given by TA + PD × θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is the specified no-load supply current times the total supply voltage across the device. PDL depends on the required output signal and load; however, for resistive loads connected to mid-supply (VS/2), PDL is at a maximum when the output is fixed at a voltage equal to VS/4 or 3VS/4. Under this condition, PDL = VS2 / (16 × RL), where RL includes feedback network loading.

The power in the output stage, and not into the load, determines internal power dissipation.

As a worst-case example, compute the maximum TJ using an OPA2830 (VSSOP-8 package) in the circuit of Figure 8-3 operating at the maximum specified ambient temperature of 85°C and driving a 150Ω load at 2.5VDC on both outputs.

PD = 10V × 11.9mA + 2 × [52 / (16 × (150Ω || 1500Ω))] = 142mW

Maximum TJ = +85°C + (0.142W × 122.6°C/W) = 102.5°C.

Although this result is still much less than the specified maximum junction temperature, system reliability considerations require lower junction temperatures. The highest possible internal dissipation occurs if the load requires current to be forced into the output at high output voltages or sourced from the output at low output voltages. This configuration forces a high current through a large internal voltage drop in the output transistors.