SBOS771B December   2016  – November 2024 OPA4277-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Bare Die Information
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Protection
      2. 6.3.2 Input Bias Current Cancellation
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • JDJ|28
  • HFR|14
  • KGD|0
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

Figure 4-1 HFR Package, 14-Pin CFP (Top View)
Table 4-1 Pin Functions: CFP
PIN TYPE DESCRIPTION
NO. NAME
1 OUT A Output Output channel A
2 –IN A Input Inverting input channel A
3 +IN A Input Noninverting input channel A
4 V+ — Positive (highest) power supply
5 +IN B Input Noninverting input channel B
6 –IN B Input Inverting input channel B
7 OUT B Output Output channel B
8 OUT C Output Output channel C
9 –IN C Input Inverting input channel C
10 +IN C Input Noninverting input channel C
11 V– — Negative (lowest) power supply
12 +IN D Input Noninverting input channel D
13 –IN D Input Inverting input channel D
14 OUT D Output Output channel D
Figure 4-2 JDJ Package, 28-Pin CDIP (Top View)
Table 4-2 Pin Functions: CDIP
PIN TYPE DESCRIPTION
NO. NAME
1, 3, 4, 8, 11, 12, 14, 15, 17, 18, 21, 25, 26, 28 NC — Not connected
2 OUT A Output Output (channel A)
5 –IN A Input Inverting input (channel A)
6 +IN A Input Noninverting input (channel A)
7 +VS — Positive (highest) power supply
9 +IN B Input Noninverting input (channel B)
10 –IN B Input Inverting input (channel B)
13 OUT B Output Output (channel B)
16 OUT C Output Output (channel C)
19 –IN C Input Inverting input (channel C)
20 +IN C Input Noninverting input (channel C)
22 –VS — Negative (lowest) power supply
23 +IN D Input Noninverting input (channel D)
24 –IN D Input Inverting input (channel D)
27 OUT D Output Output (channel D)